samsung_sm8750/android_kernel_samsung_sm8750
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: meson-g12a: add missing fclk_div2 to spicc

Browse Source 
commit daf004f87c3520c414992893e2eadd5db5f86a5a upstream.

SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes
are wrong on this clock. This causes the spicc module to output sclk at
2.5x the expected rate when clock index 3 is picked.

Adding the missing fclk_div2 resolves this.

[jbrunet: amended commit description]
Fixes: a18c8e0b76 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc: stable@vger.kernel.org # 6.1
Signed-off-by: Da Xue <da@libre.computer>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Da Xue
2025-05-12 10:26:16 -04:00
committed by Greg Kroah-Hartman
parent ebb8060561
commit f24d422452
1 changed files with 1 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/meson/g12a.c
View File

@@ -3971,6 +3971,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
{ .hw = &g12a_clk81.hw }, { .hw = &g12a_clk81.hw },
{ .hw = &g12a_fclk_div4.hw }, { .hw = &g12a_fclk_div4.hw },
{ .hw = &g12a_fclk_div3.hw }, { .hw = &g12a_fclk_div3.hw },
{ .hw = &g12a_fclk_div2.hw },
{ .hw = &g12a_fclk_div5.hw }, { .hw = &g12a_fclk_div5.hw },
{ .hw = &g12a_fclk_div7.hw }, { .hw = &g12a_fclk_div7.hw },
}; };