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net: ethernet: mtk_eth_soc: net: revise NETSYSv3 hardware configuration

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[ Upstream commit 491ef1117c56476f199b481f8c68820fe4c3a7c2 ]

Change hardware configuration for the NETSYSv3.
 - Enable PSE dummy page mechanism for the GDM1/2/3
 - Enable PSE drop mechanism when the WDMA Rx ring full
 - Enable PSE no-drop mechanism for packets from the WDMA Tx
 - Correct PSE free drop threshold
 - Correct PSE CDMA high threshold

Fixes: 1953f134a1 ("net: ethernet: mtk_eth_soc: add NETSYS_V3 version support")
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/b71f8fd9d4bb69c646c4d558f9331dd965068606.1744907886.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Bo-Cun Chen
2025-04-17 17:41:07 +01:00
committed by Greg Kroah-Hartman
parent dd6cb0a857
commit e9f67da077
2 changed files with 29 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/net/ethernet/mediatek/mtk_eth_soc.c
View File

@@ -3949,11 +3949,27 @@ static int mtk_hw_init(struct mtk_eth *eth, bool reset)
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) { if (mtk_is_netsys_v3_or_greater(eth)) {
/* PSE should not drop port1, port8 and port9 packets */ /* PSE dummy page mechanism */
mtk_w32(eth, 0x00000302, PSE_DROP_CFG); mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) | PSE_DUMMY_WORK_GDM(2) |
PSE_DUMMY_WORK_GDM(3) | DUMMY_PAGE_THR, PSE_DUMY_REQ);
/* PSE free buffer drop threshold */
mtk_w32(eth, 0x00600009, PSE_IQ_REV(8));
/* PSE should not drop port8, port9 and port13 packets from
* WDMA Tx
*/
mtk_w32(eth, 0x00002300, PSE_DROP_CFG);
/* PSE should drop packets to port8, port9 and port13 on WDMA Rx
* ring full
*/
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(0));
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(1));
mtk_w32(eth, 0x00002300, PSE_PPE_DROP(2));
/* GDM and CDM Threshold */ /* GDM and CDM Threshold */
mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); mtk_w32(eth, 0x08000707, MTK_CDMW0_THRES);
mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES);
/* Disable GDM1 RX CRC stripping */ /* Disable GDM1 RX CRC stripping */
@@ -3970,7 +3986,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool reset)
mtk_w32(eth, 0x00000300, PSE_DROP_CFG); mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
/* PSE should drop packets to port 8/9 on WDMA Rx ring full */ /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); mtk_w32(eth, 0x00000300, PSE_PPE_DROP(0));
/* PSE Free Queue Flow Control */ /* PSE Free Queue Flow Control */
mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);

10
drivers/net/ethernet/mediatek/mtk_eth_soc.h
View File

@@ -149,7 +149,15 @@
#define PSE_FQFC_CFG1 0x100 #define PSE_FQFC_CFG1 0x100
#define PSE_FQFC_CFG2 0x104 #define PSE_FQFC_CFG2 0x104
#define PSE_DROP_CFG 0x108 #define PSE_DROP_CFG 0x108
#define PSE_PPE0_DROP 0x110 #define PSE_PPE_DROP(x) (0x110 + ((x) * 0x4))
/* PSE Last FreeQ Page Request Control */
#define PSE_DUMY_REQ 0x10C
/* PSE_DUMY_REQ is not a typo but actually called like that also in
* MediaTek's datasheet
*/
#define PSE_DUMMY_WORK_GDM(x) BIT(16 + (x))
#define DUMMY_PAGE_THR 0x1
/* PSE Input Queue Reservation Register*/ /* PSE Input Queue Reservation Register*/
#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2)) #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))