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Revert "drm/amd/display: more liberal vmin/vmax update for freesync"

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commit 1b824eef269db44d068bbc0de74c94a8e8f9ce02 upstream.

This reverts commit cfb2d41831ee5647a4ae0ea7c24971a92d5dfa0d since it
causes regressions on certain configs. Revert until the issue can be
isolated and debugged.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4238
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Aurabindo Pillai
2025-05-21 16:05:39 -04:00
committed by Greg Kroah-Hartman
parent 9f837b359d
commit e9019e2214
1 changed files with 5 additions and 11 deletions
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14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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@@ -610,22 +610,16 @@ static void dm_crtc_high_irq(void *interrupt_params)
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
if (acrtc->dm_irq_params.stream && if (acrtc->dm_irq_params.stream &&
acrtc->dm_irq_params.vrr_params.supported) { acrtc->dm_irq_params.vrr_params.supported &&
bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; acrtc->dm_irq_params.freesync_config.state ==
bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; VRR_STATE_ACTIVE_VARIABLE) {
bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
mod_freesync_handle_v_update(adev->dm.freesync_module, mod_freesync_handle_v_update(adev->dm.freesync_module,
acrtc->dm_irq_params.stream, acrtc->dm_irq_params.stream,
&acrtc->dm_irq_params.vrr_params); &acrtc->dm_irq_params.vrr_params);
/* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */ dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) {
dc_stream_adjust_vmin_vmax(adev->dm.dc,
acrtc->dm_irq_params.stream,
&acrtc->dm_irq_params.vrr_params.adjust); &acrtc->dm_irq_params.vrr_params.adjust);
} }
}
/* /*
* If there aren't any active_planes then DCH HUBP may be clock-gated. * If there aren't any active_planes then DCH HUBP may be clock-gated.