nvmem: qfprom: switch to 4-byte aligned reads

[ Upstream commit 3566a737db87a9bf360c2fd36433c5149f805f2e ]

All platforms since Snapdragon 8 Gen1 (SM8450) require using 4-byte
reads to access QFPROM data. While older platforms were more than happy
with 1-byte reads, change the qfprom driver to use 4-byte reads for all
the platforms. Specify stride and word size of 4 bytes. To retain
compatibility with the existing DT and to simplify porting data from
vendor kernels, use fixup_dt_cell_info in order to bump alignment
requirements.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20250411112251.68002-12-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Dmitry Baryshkov
2025-04-11 12:22:49 +01:00
committed by Greg Kroah-Hartman
parent 35d77c8d88
commit beb6382add

View File

@@ -321,19 +321,32 @@ static int qfprom_reg_read(void *context,
unsigned int reg, void *_val, size_t bytes)
{
struct qfprom_priv *priv = context;
u8 *val = _val;
int i = 0, words = bytes;
u32 *val = _val;
void __iomem *base = priv->qfpcorrected;
int words = DIV_ROUND_UP(bytes, sizeof(u32));
int i;
if (read_raw_data && priv->qfpraw)
base = priv->qfpraw;
while (words--)
*val++ = readb(base + reg + i++);
for (i = 0; i < words; i++)
*val++ = readl(base + reg + i * sizeof(u32));
return 0;
}
/* Align reads to word boundary */
static void qfprom_fixup_dt_cell_info(struct nvmem_device *nvmem,
struct nvmem_cell_info *cell)
{
unsigned int byte_offset = cell->offset % sizeof(u32);
cell->bit_offset += byte_offset * BITS_PER_BYTE;
cell->offset -= byte_offset;
if (byte_offset && !cell->nbits)
cell->nbits = cell->bytes * BITS_PER_BYTE;
}
static void qfprom_runtime_disable(void *data)
{
pm_runtime_disable(data);
@@ -358,10 +371,11 @@ static int qfprom_probe(struct platform_device *pdev)
struct nvmem_config econfig = {
.name = "qfprom",
.add_legacy_fixed_of_cells = true,
.stride = 1,
.word_size = 1,
.stride = 4,
.word_size = 4,
.id = NVMEM_DEVID_AUTO,
.reg_read = qfprom_reg_read,
.fixup_dt_cell_info = qfprom_fixup_dt_cell_info,
};
struct device *dev = &pdev->dev;
struct resource *res;