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media: ccs-pll: Start VT pre-PLL multiplier search from correct value

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commit 06d2d478b09e6764fb6161d1621fc10d9f0f2860 upstream.

The ccs_pll_calculate_vt_tree() function does a search over possible VT
PLL configurations to find the "best" one. If the sensor does not support
odd pre-PLL divisors and the minimum value (with constraints) isn't 1,
other odd values could be errorneously searched (and selected) for the
pre-PLL divisor. Fix this.

Fixes: 415ddd9939 ("media: ccs-pll: Split limits and PLL configuration into front and back parts")
Cc: stable@vger.kernel.org
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sakari Ailus
2025-02-18 23:47:13 +02:00
committed by Greg Kroah-Hartman
parent eb7a4ea0a1
commit ae2fe66065
1 changed files with 2 additions and 0 deletions
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2
drivers/media/i2c/ccs-pll.c
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@@ -397,6 +397,8 @@ static int ccs_pll_calculate_vt_tree(struct device *dev,
min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div, min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div,
pll->ext_clk_freq_hz / pll->ext_clk_freq_hz /
lim_fr->max_pll_ip_clk_freq_hz); lim_fr->max_pll_ip_clk_freq_hz);
if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER))
min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div);
dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n", dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n",
min_pre_pll_clk_div, max_pre_pll_clk_div); min_pre_pll_clk_div, max_pre_pll_clk_div);