[S390] Inline assembly cleanup.
Major cleanup of all s390 inline assemblies. They now have a common coding style. Quite a few have been shortened, mainly by using register asm variables. Use of the EX_TABLE macro helps as well. The atomic ops, bit ops and locking inlines new use the Q-constraint if a newer gcc is used. That results in slightly better code. Thanks to Christian Borntraeger for proof reading the changes. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Martin Schwidefsky
@@ -23,74 +23,68 @@ struct task_struct;
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extern struct task_struct *__switch_to(void *, void *);
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#ifdef __s390x__
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#define __FLAG_SHIFT 56
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#else /* ! __s390x__ */
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#define __FLAG_SHIFT 24
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#endif /* ! __s390x__ */
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static inline void save_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile (
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" std 0,8(%1)\n"
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" std 2,24(%1)\n"
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" std 4,40(%1)\n"
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" std 6,56(%1)"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
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asm volatile(
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" std 0,8(%1)\n"
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" std 2,24(%1)\n"
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" std 4,40(%1)\n"
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" std 6,56(%1)"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" stfpc 0(%1)\n"
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" std 1,16(%1)\n"
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" std 3,32(%1)\n"
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" std 5,48(%1)\n"
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" std 7,64(%1)\n"
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" std 8,72(%1)\n"
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" std 9,80(%1)\n"
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" std 10,88(%1)\n"
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" std 11,96(%1)\n"
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" std 12,104(%1)\n"
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" std 13,112(%1)\n"
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" std 14,120(%1)\n"
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" std 15,128(%1)\n"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
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" stfpc 0(%1)\n"
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" std 1,16(%1)\n"
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" std 3,32(%1)\n"
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" std 5,48(%1)\n"
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" std 7,64(%1)\n"
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" std 8,72(%1)\n"
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" std 9,80(%1)\n"
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" std 10,88(%1)\n"
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" std 11,96(%1)\n"
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" std 12,104(%1)\n"
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" std 13,112(%1)\n"
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" std 14,120(%1)\n"
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" std 15,128(%1)\n"
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: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
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}
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static inline void restore_fp_regs(s390_fp_regs *fpregs)
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{
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asm volatile (
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" ld 0,8(%0)\n"
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" ld 2,24(%0)\n"
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" ld 4,40(%0)\n"
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" ld 6,56(%0)"
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: : "a" (fpregs), "m" (*fpregs) );
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asm volatile(
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" ld 0,8(%0)\n"
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" ld 2,24(%0)\n"
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" ld 4,40(%0)\n"
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" ld 6,56(%0)"
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: : "a" (fpregs), "m" (*fpregs));
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if (!MACHINE_HAS_IEEE)
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return;
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asm volatile(
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" lfpc 0(%0)\n"
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" ld 1,16(%0)\n"
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" ld 3,32(%0)\n"
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" ld 5,48(%0)\n"
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" ld 7,64(%0)\n"
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" ld 8,72(%0)\n"
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" ld 9,80(%0)\n"
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" ld 10,88(%0)\n"
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" ld 11,96(%0)\n"
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" ld 12,104(%0)\n"
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" ld 13,112(%0)\n"
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" ld 14,120(%0)\n"
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" ld 15,128(%0)\n"
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: : "a" (fpregs), "m" (*fpregs) );
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" lfpc 0(%0)\n"
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" ld 1,16(%0)\n"
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" ld 3,32(%0)\n"
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" ld 5,48(%0)\n"
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" ld 7,64(%0)\n"
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" ld 8,72(%0)\n"
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" ld 9,80(%0)\n"
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" ld 10,88(%0)\n"
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" ld 11,96(%0)\n"
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" ld 12,104(%0)\n"
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" ld 13,112(%0)\n"
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" ld 14,120(%0)\n"
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" ld 15,128(%0)\n"
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: : "a" (fpregs), "m" (*fpregs));
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}
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static inline void save_access_regs(unsigned int *acrs)
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{
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asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
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asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
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}
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static inline void restore_access_regs(unsigned int *acrs)
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{
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asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
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asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
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}
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#define switch_to(prev,next,last) do { \
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@@ -126,7 +120,7 @@ extern void account_system_vtime(struct task_struct *);
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account_vtime(prev); \
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} while (0)
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#define nop() __asm__ __volatile__ ("nop")
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#define nop() asm volatile("nop")
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#define xchg(ptr,x) \
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({ \
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@@ -147,15 +141,15 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) addr)
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: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
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"m" (*(int *) addr) : "memory", "cc", "0" );
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"m" (*(int *) addr) : "memory", "cc", "0");
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x = old >> shift;
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break;
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case 2:
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@@ -163,36 +157,36 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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" l %0,0(%4)\n"
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"0: lr 0,%0\n"
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" nr 0,%3\n"
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" or 0,%2\n"
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" cs %0,0,0(%4)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) addr)
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: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
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"m" (*(int *) addr) : "memory", "cc", "0" );
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"m" (*(int *) addr) : "memory", "cc", "0");
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x = old >> shift;
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break;
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case 4:
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asm volatile (
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" l %0,0(%3)\n"
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"0: cs %0,%2,0(%3)\n"
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" jl 0b\n"
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asm volatile(
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" l %0,0(%3)\n"
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"0: cs %0,%2,0(%3)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(int *) ptr)
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: "d" (x), "a" (ptr), "m" (*(int *) ptr)
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: "memory", "cc" );
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: "memory", "cc");
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x = old;
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break;
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#ifdef __s390x__
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case 8:
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asm volatile (
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" lg %0,0(%3)\n"
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"0: csg %0,%2,0(%3)\n"
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" jl 0b\n"
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asm volatile(
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" lg %0,0(%3)\n"
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"0: csg %0,%2,0(%3)\n"
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" jl 0b\n"
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: "=&d" (old), "=m" (*(long *) ptr)
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: "d" (x), "a" (ptr), "m" (*(long *) ptr)
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: "memory", "cc" );
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: "memory", "cc");
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x = old;
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break;
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#endif /* __s390x__ */
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@@ -224,55 +218,55 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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shift = (3 ^ (addr & 3)) << 3;
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addr ^= addr & 3;
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asm volatile(
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp)
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: "d" (old << shift), "d" (new << shift), "a" (ptr),
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"d" (~(255 << shift))
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: "memory", "cc" );
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: "memory", "cc");
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return prev >> shift;
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case 2:
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addr = (unsigned long) ptr;
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shift = (2 ^ (addr & 2)) << 3;
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addr ^= addr & 2;
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asm volatile(
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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" l %0,0(%4)\n"
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"0: nr %0,%5\n"
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" lr %1,%0\n"
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" or %0,%2\n"
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" or %1,%3\n"
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" cs %0,%1,0(%4)\n"
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" jnl 1f\n"
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" xr %1,%0\n"
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" nr %1,%5\n"
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" jnz 0b\n"
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"1:"
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: "=&d" (prev), "=&d" (tmp)
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: "d" (old << shift), "d" (new << shift), "a" (ptr),
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"d" (~(65535 << shift))
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: "memory", "cc" );
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: "memory", "cc");
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return prev >> shift;
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case 4:
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asm volatile (
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" cs %0,%2,0(%3)\n"
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asm volatile(
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" cs %0,%2,0(%3)\n"
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: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
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: "memory", "cc" );
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: "memory", "cc");
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return prev;
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#ifdef __s390x__
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case 8:
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asm volatile (
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" csg %0,%2,0(%3)\n"
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asm volatile(
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" csg %0,%2,0(%3)\n"
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: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
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: "memory", "cc" );
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: "memory", "cc");
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return prev;
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#endif /* __s390x__ */
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}
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@@ -289,8 +283,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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* all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
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*/
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#define eieio() __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
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# define SYNC_OTHER_CORES(x) eieio()
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#define eieio() asm volatile("bcr 15,0" : : : "memory")
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#define SYNC_OTHER_CORES(x) eieio()
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#define mb() eieio()
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#define rmb() eieio()
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#define wmb() eieio()
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@@ -307,117 +301,56 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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#ifdef __s390x__
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" lctlg 0,0,0(%0)\n" \
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"0: ex %1,0(1)" \
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: : "a" (&array), "a" (((low)<<4)+(high)), \
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"m" (*(addrtype *)(array)) : "1" ); \
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" lctlg %1,%2,0(%0)\n" \
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: : "a" (&array), "i" (low), "i" (high), \
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"m" (*(addrtype *)(array))); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" stctg 0,0,0(%1)\n" \
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"0: ex %2,0(1)" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" stctg %2,%3,0(%1)\n" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "i" (low), "i" (high)); \
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})
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#define __ctl_set_bit(cr, bit) ({ \
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__u8 __dummy[24]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctg 0,0,0(%1)\n" \
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" lctlg 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" lg 0,0(%1)\n" \
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" ogr 0,%3\n" /* set the bit */ \
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" stg 0,0(%1)\n" \
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"1: ex %2,6(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (1L<<(bit)) \
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: "cc", "0", "1" ); \
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})
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#define __ctl_clear_bit(cr, bit) ({ \
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__u8 __dummy[16]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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" stctg 0,0,0(%1)\n" \
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" lctlg 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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" lg 0,0(%1)\n" \
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" ngr 0,%3\n" /* set the bit */ \
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" stg 0,0(%1)\n" \
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"1: ex %2,6(1)" /* execute lctl */ \
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: "=m" (__dummy) \
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: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
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"a" (cr*17), "a" (~(1L<<(bit))) \
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: "cc", "0", "1" ); \
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})
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#else /* __s390x__ */
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" lctl 0,0,0(%0)\n" \
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"0: ex %1,0(1)" \
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: : "a" (&array), "a" (((low)<<4)+(high)), \
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"m" (*(addrtype *)(array)) : "1" ); \
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#define __ctl_load(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" lctl %1,%2,0(%0)\n" \
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: : "a" (&array), "i" (low), "i" (high), \
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"m" (*(addrtype *)(array))); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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asm volatile( \
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" stctl %2,%3,0(%1)\n" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "i" (low), "i" (high)); \
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})
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#define __ctl_store(array, low, high) ({ \
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typedef struct { char _[sizeof(array)]; } addrtype; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" \
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" stctl 0,0,0(%1)\n" \
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"0: ex %2,0(1)" \
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: "=m" (*(addrtype *)(array)) \
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: "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
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})
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#define __ctl_set_bit(cr, bit) ({ \
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__u8 __dummy[16]; \
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__asm__ __volatile__ ( \
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" bras 1,0f\n" /* skip indirect insns */ \
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||||
" stctl 0,0,0(%1)\n" \
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||||
" lctl 0,0,0(%1)\n" \
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"0: ex %2,0(1)\n" /* execute stctl */ \
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||||
" l 0,0(%1)\n" \
|
||||
" or 0,%3\n" /* set the bit */ \
|
||||
" st 0,0(%1)\n" \
|
||||
"1: ex %2,4(1)" /* execute lctl */ \
|
||||
: "=m" (__dummy) \
|
||||
: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
|
||||
"a" (cr*17), "a" (1<<(bit)) \
|
||||
: "cc", "0", "1" ); \
|
||||
})
|
||||
|
||||
#define __ctl_clear_bit(cr, bit) ({ \
|
||||
__u8 __dummy[16]; \
|
||||
__asm__ __volatile__ ( \
|
||||
" bras 1,0f\n" /* skip indirect insns */ \
|
||||
" stctl 0,0,0(%1)\n" \
|
||||
" lctl 0,0,0(%1)\n" \
|
||||
"0: ex %2,0(1)\n" /* execute stctl */ \
|
||||
" l 0,0(%1)\n" \
|
||||
" nr 0,%3\n" /* set the bit */ \
|
||||
" st 0,0(%1)\n" \
|
||||
"1: ex %2,4(1)" /* execute lctl */ \
|
||||
: "=m" (__dummy) \
|
||||
: "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
|
||||
"a" (cr*17), "a" (~(1<<(bit))) \
|
||||
: "cc", "0", "1" ); \
|
||||
})
|
||||
#endif /* __s390x__ */
|
||||
|
||||
#define __ctl_set_bit(cr, bit) ({ \
|
||||
unsigned long __dummy; \
|
||||
__ctl_store(__dummy, cr, cr); \
|
||||
__dummy |= 1UL << (bit); \
|
||||
__ctl_load(__dummy, cr, cr); \
|
||||
})
|
||||
|
||||
#define __ctl_clear_bit(cr, bit) ({ \
|
||||
unsigned long __dummy; \
|
||||
__ctl_store(__dummy, cr, cr); \
|
||||
__dummy &= ~(1UL << (bit)); \
|
||||
__ctl_load(__dummy, cr, cr); \
|
||||
})
|
||||
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
/*
|
||||
@@ -427,8 +360,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
|
||||
static inline void
|
||||
__set_psw_mask(unsigned long mask)
|
||||
{
|
||||
local_save_flags(mask);
|
||||
__load_psw_mask(mask);
|
||||
__load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
|
||||
}
|
||||
|
||||
#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
|
||||
|
||||
Reference in New Issue
Block a user