samsung_sm8750/android_kernel_samsung_sm8750
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: dts: mediatek: mt8195: Reparent vdec1/2 and venc1 power domains

Browse Source 
[ Upstream commit 394f29033324e2317bfd6a7ed99b9a60832b36a2 ]

By hardware, the first and second core of the video decoder IP
need the VDEC_SOC to be powered up in order to be able to be
accessed (both internally, by firmware, and externally, by the
kernel).
Similarly, for the video encoder IP, the second core needs the
first core to be powered up in order to be accessible.

Fix that by reparenting the VDEC1/2 power domains to be children
of VDEC0 (VDEC_SOC), and the VENC1 to be a child of VENC0.

Fixes: 2b515194bf ("arm64: dts: mt8195: Add power domains controller")
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20250402090615.25871-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
2025-04-02 11:06:15 +02:00
committed by Greg Kroah-Hartman
parent 8af84ebd27
commit 62f142f9b8
1 changed files with 27 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@@ -617,22 +617,6 @@
#size-cells = <0>; #size-cells = <0>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
power-domain@MT8195_POWER_DOMAIN_VDEC1 {
reg = <MT8195_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec1-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
reg = <MT8195_POWER_DOMAIN_VDOSYS0>; reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&topckgen CLK_TOP_CFG_VDO0>, clocks = <&topckgen CLK_TOP_CFG_VDO0>,
@@ -678,15 +662,25 @@
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "vdec0-0"; clock-names = "vdec0-0";
mediatek,infracfg = <&infracfg_ao>; mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDEC2 { power-domain@MT8195_POWER_DOMAIN_VDEC1 {
reg = <MT8195_POWER_DOMAIN_VDEC2>; reg = <MT8195_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; clocks = <&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec2-0"; clock-names = "vdec1-0";
mediatek,infracfg = <&infracfg_ao>; mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
};
power-domain@MT8195_POWER_DOMAIN_VDEC2 {
reg = <MT8195_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
clock-names = "vdec2-0";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
}; };
power-domain@MT8195_POWER_DOMAIN_VENC { power-domain@MT8195_POWER_DOMAIN_VENC {
@@ -694,7 +688,17 @@
clocks = <&vencsys CLK_VENC_LARB>; clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb"; clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>; mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>; #power-domain-cells = <0>;
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
}; };
power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {