Add samsung specific changes

2025-08-11 14:29:00 +02:00
parent c66122e619
commit 4d134a1294
2688 changed files with 1127995 additions and 11475 deletions
--- a/include/dt-bindings/clock/qcom,gcc-parrot.h
+++ b/include/dt-bindings/clock/qcom,gcc-parrot.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_PARROT_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_PARROT_H
+
+/* GCC clocks */
+#define GCC_GPLL0					0
+#define GCC_GPLL0_OUT_EVEN				1
+#define GCC_GPLL0_OUT_ODD				2
+#define GCC_GPLL1					3
+#define GCC_GPLL10					4
+#define GCC_GPLL4					5
+#define GCC_GPLL9					6
+#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK			7
+#define GCC_AGGRE_UFS_PHY_AXI_CLK			8
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK		9
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK			10
+#define GCC_BOOT_ROM_AHB_CLK				11
+#define GCC_CAMERA_AHB_CLK				12
+#define GCC_CAMERA_HF_AXI_CLK				13
+#define GCC_CAMERA_SF_AXI_CLK				14
+#define GCC_CAMERA_SLEEP_CLK				15
+#define GCC_CAMERA_XO_CLK				16
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK			17
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK			18
+#define GCC_DDRSS_GPU_AXI_CLK				19
+#define GCC_DDRSS_PCIE_SF_TBU_CLK			20
+#define GCC_DISP_AHB_CLK				21
+#define GCC_DISP_HF_AXI_CLK				22
+#define GCC_DISP_XO_CLK					23
+#define GCC_EUSB3_0_CLKREF_EN				24
+#define GCC_GP1_CLK					25
+#define GCC_GP1_CLK_SRC					26
+#define GCC_GP2_CLK					27
+#define GCC_GP2_CLK_SRC					28
+#define GCC_GP3_CLK					29
+#define GCC_GP3_CLK_SRC					30
+#define GCC_GPU_CFG_AHB_CLK				31
+#define GCC_GPU_GPLL0_CLK_SRC				32
+#define GCC_GPU_GPLL0_DIV_CLK_SRC			33
+#define GCC_GPU_MEMNOC_GFX_CLK				34
+#define GCC_GPU_SNOC_DVM_GFX_CLK			35
+#define GCC_PCIE_0_AUX_CLK				36
+#define GCC_PCIE_0_AUX_CLK_SRC				37
+#define GCC_PCIE_0_CFG_AHB_CLK				38
+#define GCC_PCIE_0_CLKREF_EN				39
+#define GCC_PCIE_0_MSTR_AXI_CLK				40
+#define GCC_PCIE_0_PHY_RCHNG_CLK			41
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC			42
+#define GCC_PCIE_0_PIPE_CLK				43
+#define GCC_PCIE_0_PIPE_CLK_SRC				44
+#define GCC_PCIE_0_PIPE_DIV2_CLK			45
+#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC			46
+#define GCC_PCIE_0_SLV_AXI_CLK				47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK			48
+#define GCC_PDM2_CLK					49
+#define GCC_PDM2_CLK_SRC				50
+#define GCC_PDM_AHB_CLK					51
+#define GCC_PDM_XO4_CLK					52
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK			53
+#define GCC_QMIP_CAMERA_RT_AHB_CLK			54
+#define GCC_QMIP_DISP_AHB_CLK				55
+#define GCC_QMIP_GPU_AHB_CLK				56
+#define GCC_QMIP_PCIE_AHB_CLK				57
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK			58
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK			59
+#define GCC_QUPV3_WRAP0_CORE_CLK			60
+#define GCC_QUPV3_WRAP0_QSPI0_CLK			61
+#define GCC_QUPV3_WRAP0_S0_CLK				62
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC			63
+#define GCC_QUPV3_WRAP0_S1_CLK				64
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC			65
+#define GCC_QUPV3_WRAP0_S2_CLK				66
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC			67
+#define GCC_QUPV3_WRAP0_S3_CLK				68
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC			69
+#define GCC_QUPV3_WRAP0_S4_CLK				70
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC			71
+#define GCC_QUPV3_WRAP0_S5_CLK				72
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC			73
+#define GCC_QUPV3_WRAP0_S5_DIV_CLK_SRC			74
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK			75
+#define GCC_QUPV3_WRAP1_CORE_CLK			76
+#define GCC_QUPV3_WRAP1_QSPI0_CLK			77
+#define GCC_QUPV3_WRAP1_S0_CLK				78
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC			79
+#define GCC_QUPV3_WRAP1_S1_CLK				80
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC			81
+#define GCC_QUPV3_WRAP1_S2_CLK				82
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC			83
+#define GCC_QUPV3_WRAP1_S3_CLK				84
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC			85
+#define GCC_QUPV3_WRAP1_S4_CLK				86
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC			87
+#define GCC_QUPV3_WRAP1_S5_CLK				88
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC			89
+#define GCC_QUPV3_WRAP1_S5_DIV_CLK_SRC			90
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK			91
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK			92
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK			93
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK			94
+#define GCC_SDCC1_AHB_CLK				95
+#define GCC_SDCC1_APPS_CLK				96
+#define GCC_SDCC1_APPS_CLK_SRC				97
+#define GCC_SDCC1_ICE_CORE_CLK				98
+#define GCC_SDCC1_ICE_CORE_CLK_SRC			99
+#define GCC_SDCC2_AHB_CLK				100
+#define GCC_SDCC2_APPS_CLK				101
+#define GCC_SDCC2_APPS_CLK_SRC				102
+#define GCC_UFS_0_CLKREF_EN				103
+#define GCC_UFS_PAD_CLKREF_EN				104
+#define GCC_UFS_PHY_AHB_CLK				105
+#define GCC_UFS_PHY_AXI_CLK				106
+#define GCC_UFS_PHY_AXI_CLK_SRC				107
+#define GCC_UFS_PHY_ICE_CORE_CLK			108
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC			109
+#define GCC_UFS_PHY_PHY_AUX_CLK				110
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC			111
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK			112
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC			113
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK			114
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC			115
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK			116
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC			117
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK			118
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC			119
+#define GCC_USB30_PRIM_MASTER_CLK			120
+#define GCC_USB30_PRIM_MASTER_CLK_SRC			121
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK			122
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC		123
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC	124
+#define GCC_USB30_PRIM_SLEEP_CLK			125
+#define GCC_USB3_0_CLKREF_EN				126
+#define GCC_USB3_PRIM_PHY_AUX_CLK			127
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC			128
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK			129
+#define GCC_USB3_PRIM_PHY_PIPE_CLK			130
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC			131
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK			132
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK			133
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK			134
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK		135
+#define GCC_VIDEO_AHB_CLK				136
+#define GCC_VIDEO_AXI0_CLK				137
+#define GCC_VIDEO_THROTTLE_CORE_CLK			138
+#define GCC_VIDEO_XO_CLK				139
+
+/* GCC resets */
+#define GCC_CAMERA_BCR					0
+#define GCC_DISPLAY_BCR					1
+#define GCC_EMMC_BCR					2
+#define GCC_GPU_BCR					3
+#define GCC_PCIE_0_BCR					4
+#define GCC_PCIE_0_LINK_DOWN_BCR			5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR			6
+#define GCC_PCIE_0_PHY_BCR				7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR		8
+#define GCC_PCIE_PHY_CFG_AHB_BCR			9
+#define GCC_PCIE_PHY_COM_BCR				10
+#define GCC_PDM_BCR					11
+#define GCC_QUPV3_WRAPPER_0_BCR				12
+#define GCC_QUPV3_WRAPPER_1_BCR				13
+#define GCC_QUSB2PHY_PRIM_BCR				14
+#define GCC_QUSB2PHY_SEC_BCR				15
+#define GCC_SDCC2_BCR					16
+#define GCC_UFS_PHY_BCR					17
+#define GCC_USB30_PRIM_BCR				18
+#define GCC_USB3_DP_PHY_PRIM_BCR			19
+#define GCC_USB3_DP_PHY_SEC_BCR				20
+#define GCC_USB3_PHY_PRIM_BCR				21
+#define GCC_USB3_PHY_SEC_BCR				22
+#define GCC_USB3PHY_PHY_PRIM_BCR			23
+#define GCC_USB3PHY_PHY_SEC_BCR				24
+#define GCC_VIDEO_AXI0_CLK_ARES				25
+#define GCC_VIDEO_BCR					26
+
+#endif