Add samsung specific changes
This commit is contained in:
242
drivers/cpufreq/qcom-cpufreq-hw-debug.c
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242
drivers/cpufreq/qcom-cpufreq-hw-debug.c
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#define pr_fmt(fmt) "cpufreq_hw_debug: %s: " fmt, __func__
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/panic_notifier.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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enum debug_hw_regs_data {
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REG_PERF_STATE,
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REG_CYCLE_CNTR,
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REG_PSTATE_STATUS,
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REG_EPSS_DEBUG_STATUS,
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REG_EPSS_DEBUG_SRB,
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REG_EPSS_DEBUG_LUT,
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REG_ARRAY_SIZE,
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};
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struct cpufreq_hwregs {
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void __iomem *base[REG_ARRAY_SIZE];
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int domain_cnt;
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};
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struct cpufreq_register_data {
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char *name;
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u16 offset;
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};
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static struct cpufreq_hwregs *hw_regs;
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static const u16 *offsets;
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static struct kobj_attribute cpufreq_hwregs_attr;
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static struct kobject *cpufreqhw_kobj;
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static const u16 cpufreq_qcom_std_data[] = {
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[REG_PERF_STATE] = 0x920,
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[REG_CYCLE_CNTR] = 0x9c0,
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[REG_PSTATE_STATUS] = 0x700,
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};
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static const u16 cpufreq_qcom_std_epss_data[] = {
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[REG_PERF_STATE] = 0x320,
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[REG_CYCLE_CNTR] = 0x3c4,
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[REG_PSTATE_STATUS] = 0x020,
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[REG_EPSS_DEBUG_STATUS] = 0x01c,
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[REG_EPSS_DEBUG_SRB] = 0x0bc,
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[REG_EPSS_DEBUG_LUT] = 0x100,
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};
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static ssize_t cpufreq_hwregs_show(struct kobject *kobj,
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struct kobj_attribute *attr, char *buf)
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{
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int i, j, size = ARRAY_SIZE(cpufreq_qcom_std_data);
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u32 regval, count = 0;
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static struct cpufreq_register_data data[] = {
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{"PERF_STATE_DESIRED", REG_PERF_STATE},
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{"CYCLE_CNTR_VAL", REG_CYCLE_CNTR},
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{"PSTATE_STATUS", REG_PSTATE_STATUS},
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{"EPSS_DEBUG_STATUS", REG_EPSS_DEBUG_STATUS},
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{"EPSS_DEBUG_SRB", REG_EPSS_DEBUG_SRB},
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{"EPSS_DEBUG_LUT", REG_EPSS_DEBUG_LUT},
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};
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if (offsets == cpufreq_qcom_std_epss_data)
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size = ARRAY_SIZE(cpufreq_qcom_std_epss_data);
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for (i = 0; i < hw_regs->domain_cnt; i++) {
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count += scnprintf(buf + count, PAGE_SIZE,
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"FREQUENCY DOMAIN %d\n", i);
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for (j = 0; j < size; j++) {
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regval = readl_relaxed(hw_regs->base[i] +
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offsets[data[j].offset]);
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count += scnprintf(buf + count, PAGE_SIZE,
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"%25s: 0x%.8x\n", data[j].name, regval);
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}
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}
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return count;
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}
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static int cpufreq_panic_callback(struct notifier_block *nfb,
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unsigned long event, void *unused)
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{
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int i, j, size = ARRAY_SIZE(cpufreq_qcom_std_data);
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u32 regval;
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static struct cpufreq_register_data data[] = {
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{"PERF_STATE_DESIRED", REG_PERF_STATE},
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{"CYCLE_CNTR_VAL", REG_CYCLE_CNTR},
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{"PSTATE_STATUS", REG_PSTATE_STATUS},
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{"EPSS_DEBUG_STATUS", REG_EPSS_DEBUG_STATUS},
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{"EPSS_DEBUG_SRB", REG_EPSS_DEBUG_SRB},
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{"EPSS_DEBUG_LUT", REG_EPSS_DEBUG_LUT},
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};
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if (offsets == cpufreq_qcom_std_epss_data)
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size = ARRAY_SIZE(cpufreq_qcom_std_epss_data);
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for (i = 0; i < hw_regs->domain_cnt; i++) {
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pr_err("FREQUENCY DOMAIN %d\n", i);
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for (j = 0; j < size; j++) {
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regval = readl_relaxed(hw_regs->base[i] +
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offsets[data[j].offset]);
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pr_err("%25s: 0x%.8x\n", data[j].name, regval);
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}
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}
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return NOTIFY_OK;
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}
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static struct notifier_block cpufreq_panic_notifier = {
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.notifier_call = cpufreq_panic_callback,
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.priority = 1,
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};
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static int cpufreq_get_hwregs(struct platform_device *pdev)
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{
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struct of_phandle_args args;
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struct property *prop;
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struct resource res;
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void __iomem *base;
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int i, ret;
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offsets = of_device_get_match_data(&pdev->dev);
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if (!offsets)
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return -EINVAL;
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hw_regs = devm_kzalloc(&pdev->dev, sizeof(*hw_regs), GFP_KERNEL);
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if (!hw_regs)
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return -ENOMEM;
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prop = of_find_property(pdev->dev.of_node, "qcom,freq-hw-domain", NULL);
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if (!prop)
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return -EINVAL;
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hw_regs->domain_cnt = prop->length / (2 * sizeof(prop->length));
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for (i = 0; i < hw_regs->domain_cnt; i++) {
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,freq-hw-domain", 1, i, &args);
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of_node_put(pdev->dev.of_node);
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if (ret)
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return ret;
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ret = of_address_to_resource(args.np, args.args[0], &res);
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if (ret)
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return ret;
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base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
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if (!base)
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return -ENOMEM;
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hw_regs->base[i] = base;
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}
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atomic_notifier_chain_register(&panic_notifier_list,
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&cpufreq_panic_notifier);
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return 0;
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}
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static int enable_cpufreq_hw_debug(struct platform_device *pdev)
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{
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int ret;
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ret = cpufreq_get_hwregs(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to map cpufreq hw regs\n");
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return ret;
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}
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cpufreqhw_kobj = kobject_create_and_add("qcom-cpufreq-hw",
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kernel_kobj);
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if (!cpufreqhw_kobj)
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return -ENOMEM;
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sysfs_attr_init(&cpufreq_hwregs_attr.attr);
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cpufreq_hwregs_attr.attr.name = "print_cpufreq_debug_regs";
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cpufreq_hwregs_attr.show = cpufreq_hwregs_show;
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cpufreq_hwregs_attr.attr.mode = 0444;
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ret = sysfs_create_file(cpufreqhw_kobj, &cpufreq_hwregs_attr.attr);
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if (ret) {
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dev_err(&pdev->dev, "Failed to create sysfs entry\n");
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kobject_put(cpufreqhw_kobj);
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}
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return ret;
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}
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static int qcom_cpufreq_hw_debug_probe(struct platform_device *pdev)
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{
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return enable_cpufreq_hw_debug(pdev);
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}
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static int qcom_cpufreq_hw_debug_remove(struct platform_device *pdev)
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{
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sysfs_remove_file(kernel_kobj, &cpufreq_hwregs_attr.attr);
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kobject_put(cpufreqhw_kobj);
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return 0;
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}
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static const struct of_device_id qcom_cpufreq_hw_debug_match[] = {
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{ .compatible = "qcom,cpufreq-hw-debug",
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.data = &cpufreq_qcom_std_data },
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{ .compatible = "qcom,cpufreq-hw-epss-debug",
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.data = &cpufreq_qcom_std_epss_data },
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{}
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};
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static struct platform_driver qcom_cpufreq_hw_debug = {
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.probe = qcom_cpufreq_hw_debug_probe,
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.remove = qcom_cpufreq_hw_debug_remove,
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.driver = {
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.name = "qcom-cpufreq-hw-debug",
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.of_match_table = qcom_cpufreq_hw_debug_match,
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},
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};
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static int __init qcom_cpufreq_hw_debug_init(void)
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{
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return platform_driver_register(&qcom_cpufreq_hw_debug);
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}
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fs_initcall(qcom_cpufreq_hw_debug_init);
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static void __exit qcom_cpufreq_hw_debug_exit(void)
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{
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return platform_driver_unregister(&qcom_cpufreq_hw_debug);
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}
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module_exit(qcom_cpufreq_hw_debug_exit);
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MODULE_DESCRIPTION("QTI clock driver for CPUFREQ HW debug");
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MODULE_LICENSE("GPL");
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