Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits)
MIPS: Delete unused function add_temporary_entry.
MIPS: Set default pci cache line size.
MIPS: Flush huge TLB
MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM.
MIPS: Octeon: Add support for OCTEON II PCIe
MIPS: Octeon: Update PCI Latency timer and enable more error reporting.
MIPS: Alchemy: Update cpu-feature-overrides
MIPS: Alchemy: db1200: Improve PB1200 detection.
MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.
MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller
MIPS: Alchemy: irq: register pm at irq init time
MIPS: Alchemy: Touchscreen support on DB1100
MIPS: Alchemy: Hook up IrDA on DB1000/DB1100
net/irda: convert au1k_ir to platform driver.
MIPS: Alchemy: remove unused board headers
MTD: nand: make au1550nd.c a platform_driver
MIPS: Netlogic: Mark Netlogic chips as SMT capable
MIPS: Netlogic: Add support for XLP 3XX cores
MIPS: Netlogic: Merge some of XLR/XLP wakup code
MIPS: Netlogic: Add default XLP config.
...
Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c,
traps.c} and drivers/tty/serial/Makefile
This commit is contained in:
@@ -4,8 +4,11 @@
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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@@ -14,6 +17,8 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/cpu-info.h>
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/*
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* Indicate whether we respect the PCI setup left by the firmware.
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*
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@@ -157,10 +162,32 @@ out:
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"Skipping PCI bus scan due to resource conflict\n");
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}
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static void __init pcibios_set_cache_line_size(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the highest level in the
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* cache hierarchy.
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*/
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lsize = c->dcache.linesz;
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lsize = c->scache.linesz ? : lsize;
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lsize = c->tcache.linesz ? : lsize;
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose;
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pcibios_set_cache_line_size();
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/* Scan all of the recorded PCI controllers. */
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for (hose = hose_head; hose; hose = hose->next)
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pcibios_scanbus(hose);
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