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arm64: dts: qcom: sm8550: add UART14 nodes

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[ Upstream commit 75cac7090298978c12c59dbca377d957f6f8a8bb ]

Add the Geni High Speed UART QUP instance 2 element 6
node and associated default pinctrl.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230911-topic-sm8550-upstream-bt-v4-1-a5a428c77418@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stable-dep-of: 5ff1fbb30597 ("platform/x86: think-lmi: Fix class device unregistration")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Neil Armstrong
2023-09-11 09:28:46 +02:00
committed by Greg Kroah-Hartman
parent 0deb3eb78e
commit 3df1e72b7b
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/qcom/sm8550.dtsi
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@@ -1064,6 +1064,20 @@
status = "disabled";
};
uart14: serial@898000 {
compatible = "qcom,geni-uart";
reg = <0 0x898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c15: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0089c000 0 0x4000>;
@@ -3640,6 +3654,22 @@
bias-disable;
};
qup_uart14_default: qup-uart14-default-state {
/* TX, RX */
pins = "gpio78", "gpio79";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-up;
};
qup_uart14_cts_rts: qup-uart14-cts-rts-state {
/* CTS, RTS */
pins = "gpio76", "gpio77";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-down;
};
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";