From 51e4d60e6ba50cc53150885549318c3470d44e3c Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 10 May 2022 16:54:39 -0700 Subject: [PATCH 01/46] drm/msm/dpu: add writeback support for sc7180 Add writeback support for sc7180 devices. This has been validated on sc7180 chromebook using IGT writeback test suite. localhost /usr/local/libexec/igt-gpu-tools # ./kms_writeback Starting subtest: writeback-pixel-formats Subtest writeback-pixel-formats: SUCCESS (0.001s) Starting subtest: writeback-invalid-parameters Subtest writeback-invalid-parameters: SUCCESS (0.004s) Starting subtest: writeback-fb-id Subtest writeback-fb-id: SUCCESS (0.009s) Starting subtest: writeback-check-output Subtest writeback-check-output: SUCCESS (0.203s) Adding this will increase IGT coverage on chromebooks and also allow using writeback functionality for other use-cases as necessary. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/485787/ Link: https://lore.kernel.org/r/20220510235439.31916-1-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 400ebceb56bb..210becd2a9b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1803,6 +1803,8 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .pingpong = sc7180_pp, .intf_count = ARRAY_SIZE(sc7180_intf), .intf = sc7180_intf, + .wb_count = ARRAY_SIZE(sm8250_wb), + .wb = sm8250_wb, .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, From 2d8a4edb672dbd997ee1d82eb13b08def29b4329 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:41 +0300 Subject: [PATCH 02/46] drm/msm/dpu: use feature bit for LM combined alpha check Rather than checking hwversion, follow the usual patter and add special bit to the lm->features to check whether the LM has combined or separate alpha registers. While we are at it, rename dpu_hw_lm_setup_blend_config_sdm845() to dpu_hw_lm_setup_blend_config_combined_alpha(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/488155/ Link: https://lore.kernel.org/r/20220602202447.1755115-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 19 +++++++++++-------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 210becd2a9b7..9309e2b8a41c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -50,11 +50,14 @@ #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) -#define MIXER_SDM845_MASK \ +#define MIXER_MSM8998_MASK \ (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) +#define MIXER_SDM845_MASK \ + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) + #define MIXER_SC7180_MASK \ - (BIT(DPU_DIM_LAYER)) + (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) @@ -936,17 +939,17 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { }; static const struct dpu_lm_cfg msm8998_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, + LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, + LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, + LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, + LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, + LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, + LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 8cb6d1f25bf9..80bc09b1f1b3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -145,6 +145,7 @@ enum { * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration * @DPU_MIXER_GC Gamma correction block * @DPU_DIM_LAYER Layer mixer supports dim layer + * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register * @DPU_MIXER_MAX maximum value */ enum { @@ -152,6 +153,7 @@ enum { DPU_MIXER_SOURCESPLIT, DPU_MIXER_GC, DPU_DIM_LAYER, + DPU_MIXER_COMBINED_ALPHA, DPU_MIXER_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 462f5082099e..25d2eba28e71 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -148,7 +148,7 @@ static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) return 0; } -static void dpu_hw_lm_setup_blend_config_sdm845(struct dpu_hw_mixer *ctx, +static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -204,8 +204,8 @@ static void _setup_mixer_ops(const struct dpu_mdss_cfg *m, unsigned long features) { ops->setup_mixer_out = dpu_hw_lm_setup_out; - if (m->hwversion >= DPU_HW_VER_400) - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_sdm845; + if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features)) + ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha; else ops->setup_blend_config = dpu_hw_lm_setup_blend_config; ops->setup_alpha_out = dpu_hw_lm_setup_color3; From c87443150a982727dbd1f57bc91649864b471ab2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:42 +0300 Subject: [PATCH 03/46] drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog Rather than detecting VBIF_XINL_QOS_LVL_REMAP_000 based on the hwversion, push the offset to the hw_catalog. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488156/ Link: https://lore.kernel.org/r/20220602202447.1755115-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 4 ++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 9309e2b8a41c..6647cdedbd75 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1339,6 +1339,7 @@ static const struct dpu_vbif_cfg msm8998_vbif[] = { .default_ot_wr_limit = 32, .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), .xin_halt_timeout = 0x4000, + .qos_rp_remap_size = 0x20, .dynamic_ot_rd_tbl = { .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), .cfg = msm8998_ot_rdwr_cfg, @@ -1366,6 +1367,7 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { .base = 0, .len = 0x1040, .features = BIT(DPU_VBIF_QOS_REMAP), .xin_halt_timeout = 0x4000, + .qos_rp_remap_size = 0x40, .qos_rt_tbl = { .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), .priority_lvl = sdm845_rt_pri_lvl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 80bc09b1f1b3..f70de97f492a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -709,6 +709,7 @@ struct dpu_vbif_qos_tbl { * @ot_rd_limit default OT read limit * @ot_wr_limit default OT write limit * @xin_halt_timeout maximum time (in usec) for xin to halt + * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space * @dynamic_ot_rd_tbl dynamic OT read configuration table * @dynamic_ot_wr_tbl dynamic OT write configuration table * @qos_rt_tbl real-time QoS priority table @@ -721,6 +722,7 @@ struct dpu_vbif_cfg { u32 default_ot_rd_limit; u32 default_ot_wr_limit; u32 xin_halt_timeout; + u32 qos_rp_remap_size; struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; struct dpu_vbif_qos_tbl qos_rt_tbl; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index b757054e1c23..046854c3fbed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -30,7 +30,7 @@ #define VBIF_XIN_HALT_CTRL0 0x0200 #define VBIF_XIN_HALT_CTRL1 0x0204 #define VBIF_XINL_QOS_RP_REMAP_000 0x0550 -#define VBIF_XINL_QOS_LVL_REMAP_000(v) (v < DPU_HW_VER_400 ? 0x570 : 0x0590) +#define VBIF_XINL_QOS_LVL_REMAP_000(vbif) (VBIF_XINL_QOS_RP_REMAP_000 + (vbif)->cap->qos_rp_remap_size) static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif, u32 *pnd_errors, u32 *src_errors) @@ -163,7 +163,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif, c = &vbif->hw; - reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion); + reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(vbif); reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8); reg_shift = (xin_id & 0x7) * 4; From 129ae533fabfbbbfe59aabf6a26cce2cfeccbf23 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:43 +0300 Subject: [PATCH 04/46] drm/msm/dpu: remove hwversion field from data structures The driver should not depend on hw revision for detecting features. Instead it should use features from the hw catalog. Drop the hwversion field from struct dpu_mdss_cfg and struct dpu_hw_blk_reg_map. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488160/ Link: https://lore.kernel.org/r/20220602202447.1755115-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 1 - 15 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 6647cdedbd75..61271d9013a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -2004,7 +2004,6 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { if (cfg_handler[i].hw_rev == hw_rev) { cfg_handler[i].cfg_init(dpu_cfg); - dpu_cfg->hwversion = hw_rev; return dpu_cfg; } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index f70de97f492a..4225f58d8f97 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -826,8 +826,6 @@ struct dpu_perf_cfg { * @mdss_irqs: Bitmap with the irqs supported by the target */ struct dpu_mdss_cfg { - u32 hwversion; - const struct dpu_caps *caps; u32 mdp_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index c33e7ef611a6..7d416bf4ae91 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -61,7 +61,6 @@ static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl, b->base_off = addr; b->blk_off = m->ctl[i].base; b->length = m->ctl[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_CTL; return &m->ctl[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 4ad8991fc7d9..6f20d6b6dddd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -169,7 +169,6 @@ static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, b->base_off = addr; b->blk_off = m->dsc[i].base; b->length = m->dsc[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_DSC; return &m->dsc[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index 355894a3b48c..3e63bf4fa64e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -83,7 +83,6 @@ static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp, b->base_off = addr; b->blk_off = m->dspp[i].base; b->length = m->dspp[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_DSPP; return &m->dspp[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 61284e6c313d..01bb2d84c3a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -403,7 +403,6 @@ static void __intr_offset(struct dpu_mdss_cfg *m, { hw->base_off = addr; hw->blk_off = m->mdp[0].base; - hw->hwversion = m->hwversion; } struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 3f4d2c6e1b45..b2ca8d19fdd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -80,7 +80,6 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, b->base_off = addr; b->blk_off = m->intf[i].base; b->length = m->intf[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_INTF; return &m->intf[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index 25d2eba28e71..b41993269d09 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -46,7 +46,6 @@ static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, b->base_off = addr; b->blk_off = m->mixer[i].base; b->length = m->mixer[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_LM; return &m->mixer[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c index c06d595d5df0..b053d68d38da 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -26,7 +26,6 @@ static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d idx, b->base_off = addr; b->blk_off = m->merge_3d[i].base; b->length = m->merge_3d[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_PINGPONG; return &m->merge_3d[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 47c6ab6caf95..6538e195cfe9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -54,7 +54,6 @@ static const struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, b->base_off = addr; b->blk_off = m->pingpong[i].base; b->length = m->pingpong[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_PINGPONG; return &m->pingpong[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 0a0864dff783..ab7f1a4cc578 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -772,7 +772,6 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, b->base_off = addr; b->blk_off = catalog->sspp[i].base; b->length = catalog->sspp[i].len; - b->hwversion = catalog->hwversion; b->log_mask = DPU_DBG_MASK_SSPP; return &catalog->sspp[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index ab3ef162b666..12d3b0067275 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -288,7 +288,6 @@ static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, b->base_off = addr; b->blk_off = m->mdp[i].base; b->length = m->mdp[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_TOP; return &m->mdp[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index e4a65eb4f769..550b2e2b3e34 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -21,14 +21,12 @@ * @blk_off: pipe offset relative to mdss offset * @length length of register block offset * @xin_id xin id - * @hwversion mdss hw version number */ struct dpu_hw_blk_reg_map { void __iomem *base_off; u32 blk_off; u32 length; u32 xin_id; - u32 hwversion; u32 log_mask; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c index 046854c3fbed..789ecc531b43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c @@ -223,7 +223,6 @@ static const struct dpu_vbif_cfg *_top_offset(enum dpu_vbif vbif, b->base_off = addr; b->blk_off = m->vbif[i].base; b->length = m->vbif[i].len; - b->hwversion = m->hwversion; b->log_mask = DPU_DBG_MASK_VBIF; return &m->vbif[i]; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index bcccce292937..084439fdd3a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -63,7 +63,6 @@ static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb, b->base_off = addr; b->blk_off = m->wb[i].base; b->length = m->wb[i].len; - b->hwversion = m->hwversion; return &m->wb[i]; } } From 477db4feea03e6b93071d2152efac761b8cab22d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:44 +0300 Subject: [PATCH 05/46] drm/msm/dpu: change catalog->perf to be a const pointer Change dpu_mdss_cfg::perf to be a const pointer rather than embedding the dpu_perf_cfg struct into the struct dpu_mdss_cfg. Reported-by: kernel test robot Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488158/ Link: https://lore.kernel.org/r/20220602202447.1755115-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 20 +++++++++---------- .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 +++++----- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 16 +++++++-------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++--------- 5 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index a7492dd6ed65..31767d0f7353 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -53,7 +53,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms, crtc_plane_bw += pstate->plane_fetch_bw; } - bw_factor = kms->catalog->perf.bw_inefficiency_factor; + bw_factor = kms->catalog->perf->bw_inefficiency_factor; if (bw_factor) { crtc_plane_bw *= bw_factor; do_div(crtc_plane_bw, 100); @@ -90,7 +90,7 @@ static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms, crtc_clk = max(pstate->plane_clk, crtc_clk); } - clk_factor = kms->catalog->perf.clk_inefficiency_factor; + clk_factor = kms->catalog->perf->clk_inefficiency_factor; if (clk_factor) { crtc_clk *= clk_factor; do_div(crtc_clk, 100); @@ -128,7 +128,7 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, perf->core_clk_rate = kms->perf.fix_core_clk_rate; } else { perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc); - perf->max_per_pipe_ib = kms->catalog->perf.min_dram_ib; + perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib; perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state); } @@ -189,7 +189,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw); - threshold = kms->catalog->perf.max_bw_high; + threshold = kms->catalog->perf->max_bw_high; DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); @@ -413,7 +413,7 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { struct dpu_core_perf *perf = file->private_data; - struct dpu_perf_cfg *cfg = &perf->catalog->perf; + const struct dpu_perf_cfg *cfg = perf->catalog->perf; u32 perf_mode = 0; int ret; @@ -480,15 +480,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) debugfs_create_u32("enable_bw_release", 0600, entry, (u32 *)&perf->enable_bw_release); debugfs_create_u32("threshold_low", 0600, entry, - (u32 *)&catalog->perf.max_bw_low); + (u32 *)&catalog->perf->max_bw_low); debugfs_create_u32("threshold_high", 0600, entry, - (u32 *)&catalog->perf.max_bw_high); + (u32 *)&catalog->perf->max_bw_high); debugfs_create_u32("min_core_ib", 0600, entry, - (u32 *)&catalog->perf.min_core_ib); + (u32 *)&catalog->perf->min_core_ib); debugfs_create_u32("min_llcc_ib", 0600, entry, - (u32 *)&catalog->perf.min_llcc_ib); + (u32 *)&catalog->perf->min_llcc_ib); debugfs_create_u32("min_dram_ib", 0600, entry, - (u32 *)&catalog->perf.min_dram_ib); + (u32 *)&catalog->perf->min_dram_ib); debugfs_create_file("perf_mode", 0600, entry, (u32 *)perf, &dpu_core_perf_mode_fops); debugfs_create_u64("fix_core_clk_rate", 0600, entry, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 0ec809ab06e7..0793ab213670 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -104,7 +104,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) struct dpu_hw_wb *hw_wb; struct dpu_hw_wb_qos_cfg qos_cfg; struct dpu_mdss_cfg *catalog; - struct dpu_qos_lut_tbl *qos_lut_tb; + const struct dpu_qos_lut_tbl *qos_lut_tb; if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { DPU_ERROR("invalid parameter(s)\n"); @@ -118,11 +118,11 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg)); qos_cfg.danger_safe_en = true; qos_cfg.danger_lut = - catalog->perf.danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; + catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; - qos_cfg.safe_lut = catalog->perf.safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; + qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; - qos_lut_tb = &catalog->perf.qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; + qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0); if (hw_wb->ops.setup_qos_lut) @@ -166,7 +166,7 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, if (hw_wb->ops.setup_cdp) { memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); - cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf.cdp_cfg + cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg [DPU_PERF_CDP_USAGE_NRT].wr_enable; cdp_cfg.ubwc_meta_enable = DPU_FORMAT_IS_UBWC(wb_cfg->dest.format); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 61271d9013a1..8d19bb190aae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1750,7 +1750,7 @@ static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(msm8998_vbif), .vbif = msm8998_vbif, .reg_dma_count = 0, - .perf = msm8998_perf_data, + .perf = &msm8998_perf_data, .mdss_irqs = IRQ_SM8250_MASK, }; } @@ -1781,7 +1781,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif = sdm845_vbif, .reg_dma_count = 1, .dma_cfg = sdm845_regdma, - .perf = sdm845_perf_data, + .perf = &sdm845_perf_data, .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1814,7 +1814,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif = sdm845_vbif, .reg_dma_count = 1, .dma_cfg = sdm845_regdma, - .perf = sc7180_perf_data, + .perf = &sc7180_perf_data, .mdss_irqs = IRQ_SC7180_MASK, }; } @@ -1847,7 +1847,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif = sdm845_vbif, .reg_dma_count = 1, .dma_cfg = sm8150_regdma, - .perf = sm8150_perf_data, + .perf = &sm8150_perf_data, .mdss_irqs = IRQ_SDM845_MASK, }; } @@ -1878,7 +1878,7 @@ static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif = sdm845_vbif, .reg_dma_count = 1, .dma_cfg = sm8150_regdma, - .perf = sc8180x_perf_data, + .perf = &sc8180x_perf_data, .mdss_irqs = IRQ_SC8180X_MASK, }; } @@ -1913,7 +1913,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .wb = sm8250_wb, .reg_dma_count = 1, .dma_cfg = sm8250_regdma, - .perf = sm8250_perf_data, + .perf = &sm8250_perf_data, .mdss_irqs = IRQ_SM8250_MASK, }; } @@ -1936,7 +1936,7 @@ static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .intf = sc7280_intf, .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, - .perf = sc7280_perf_data, + .perf = &sc7280_perf_data, .mdss_irqs = IRQ_SC7280_MASK, }; } @@ -1968,7 +1968,7 @@ static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif = sdm845_vbif, .reg_dma_count = 1, .dma_cfg = sdm845_regdma, - .perf = qcm2290_perf_data, + .perf = &qcm2290_perf_data, .mdss_irqs = IRQ_SC7180_MASK, }; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4225f58d8f97..64ed96b2fa3d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -868,7 +868,7 @@ struct dpu_mdss_cfg { /* Add additional block data structures here */ - struct dpu_perf_cfg perf; + const struct dpu_perf_cfg *perf; const struct dpu_format_extended *dma_formats; const struct dpu_format_extended *cursor_formats; const struct dpu_format_extended *vig_formats; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 5b5aef249390..b887f45596f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -160,7 +160,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; vfp = mode->vsync_start - mode->vdisplay; - hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; + hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -309,7 +309,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, } qos_lut = _dpu_hw_get_qos_lut( - &pdpu->catalog->perf.qos_lut_tbl[lut_usage], total_fl); + &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, @@ -336,9 +336,9 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, u32 danger_lut, safe_lut; if (!pdpu->is_rt_pipe) { - danger_lut = pdpu->catalog->perf.danger_lut_tbl + danger_lut = pdpu->catalog->perf->danger_lut_tbl [DPU_QOS_LUT_USAGE_NRT]; - safe_lut = pdpu->catalog->perf.safe_lut_tbl + safe_lut = pdpu->catalog->perf->safe_lut_tbl [DPU_QOS_LUT_USAGE_NRT]; } else { fmt = dpu_get_dpu_format_ext( @@ -346,14 +346,14 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, fb->modifier); if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { - danger_lut = pdpu->catalog->perf.danger_lut_tbl + danger_lut = pdpu->catalog->perf->danger_lut_tbl [DPU_QOS_LUT_USAGE_LINEAR]; - safe_lut = pdpu->catalog->perf.safe_lut_tbl + safe_lut = pdpu->catalog->perf->safe_lut_tbl [DPU_QOS_LUT_USAGE_LINEAR]; } else { - danger_lut = pdpu->catalog->perf.danger_lut_tbl + danger_lut = pdpu->catalog->perf->danger_lut_tbl [DPU_QOS_LUT_USAGE_MACROTILE]; - safe_lut = pdpu->catalog->perf.safe_lut_tbl + safe_lut = pdpu->catalog->perf->safe_lut_tbl [DPU_QOS_LUT_USAGE_MACROTILE]; } } @@ -1225,7 +1225,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); - cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg + cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg [DPU_PERF_CDP_USAGE_RT].rd_enable; cdp_cfg.ubwc_meta_enable = DPU_FORMAT_IS_UBWC(fmt); From 481d5dbb93ae5083e20bcf973d8b6696ee54be86 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:45 +0300 Subject: [PATCH 06/46] drm/msm/dpu: change catalog->dma_cfg to be a const pointer Change dpu_mdss_cfg::dma_cfg to be a const pointer rather than embedding the dpu_reg_dma_cfg struct into the struct dpu_mdss_cfg. Reported-by: kernel test robot Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488162/ Link: https://lore.kernel.org/r/20220602202447.1755115-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8d19bb190aae..0578e0c560d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1780,7 +1780,7 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, - .dma_cfg = sdm845_regdma, + .dma_cfg = &sdm845_regdma, .perf = &sdm845_perf_data, .mdss_irqs = IRQ_SDM845_MASK, }; @@ -1813,7 +1813,7 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, - .dma_cfg = sdm845_regdma, + .dma_cfg = &sdm845_regdma, .perf = &sc7180_perf_data, .mdss_irqs = IRQ_SC7180_MASK, }; @@ -1846,7 +1846,7 @@ static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, - .dma_cfg = sm8150_regdma, + .dma_cfg = &sm8150_regdma, .perf = &sm8150_perf_data, .mdss_irqs = IRQ_SDM845_MASK, }; @@ -1877,7 +1877,7 @@ static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, - .dma_cfg = sm8150_regdma, + .dma_cfg = &sm8150_regdma, .perf = &sc8180x_perf_data, .mdss_irqs = IRQ_SC8180X_MASK, }; @@ -1912,7 +1912,7 @@ static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .wb_count = ARRAY_SIZE(sm8250_wb), .wb = sm8250_wb, .reg_dma_count = 1, - .dma_cfg = sm8250_regdma, + .dma_cfg = &sm8250_regdma, .perf = &sm8250_perf_data, .mdss_irqs = IRQ_SM8250_MASK, }; @@ -1967,7 +1967,7 @@ static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg) .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .reg_dma_count = 1, - .dma_cfg = sdm845_regdma, + .dma_cfg = &sdm845_regdma, .perf = &qcm2290_perf_data, .mdss_irqs = IRQ_SC7180_MASK, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 64ed96b2fa3d..60b403ac9f0f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -859,7 +859,7 @@ struct dpu_mdss_cfg { const struct dpu_wb_cfg *wb; u32 reg_dma_count; - struct dpu_reg_dma_cfg dma_cfg; + const struct dpu_reg_dma_cfg *dma_cfg; u32 ad_count; From 3208496720a180985b35ec7ccad8334ce885d3a8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:46 +0300 Subject: [PATCH 07/46] drm/msm/dpu: constify struct dpu_mdss_cfg Mark struct dpu_mdss_cfg instance as a const pointer. This is mostly a preparation for the next patch. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488164/ Link: https://lore.kernel.org/r/20220602202447.1755115-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 +++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 9 ++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 +++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +- 17 files changed, 29 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 31767d0f7353..1d9d83d7b99e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -468,7 +468,7 @@ static const struct file_operations dpu_core_perf_mode_fops = { int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) { struct dpu_core_perf *perf = &dpu_kms->perf; - struct dpu_mdss_cfg *catalog = perf->catalog; + const struct dpu_mdss_cfg *catalog = perf->catalog; struct dentry *entry; entry = debugfs_create_dir("core_perf", parent); @@ -517,7 +517,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, - struct dpu_mdss_cfg *catalog, + const struct dpu_mdss_cfg *catalog, struct clk *core_clk) { perf->dev = dev; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 8dfcc6db7176..e3795995e145 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -68,7 +68,7 @@ struct dpu_core_perf_tune { struct dpu_core_perf { struct drm_device *dev; struct dentry *debugfs_root; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; struct clk *core_clk; u64 core_clk_rate; u64 max_core_clk_rate; @@ -119,7 +119,7 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf); */ int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, - struct dpu_mdss_cfg *catalog, + const struct dpu_mdss_cfg *catalog, struct clk *core_clk); struct dpu_kms; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index a1b8c4592943..5e88ddd0f4fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1205,7 +1205,7 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) mutex_unlock(&dpu_enc->enc_lock); } -static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, +static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, enum dpu_intf_type type, u32 controller_id) { int i = 0; @@ -1222,7 +1222,7 @@ static enum dpu_intf dpu_encoder_get_intf(struct dpu_mdss_cfg *catalog, return INTF_MAX; } -static enum dpu_wb dpu_encoder_get_wb(struct dpu_mdss_cfg *catalog, +static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog, enum dpu_intf_type type, u32 controller_id) { int i = 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 0793ab213670..2ba9e64445b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -103,7 +103,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_wb *hw_wb; struct dpu_hw_wb_qos_cfg qos_cfg; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; const struct dpu_qos_lut_tbl *qos_lut_tb; if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0578e0c560d3..535337a9e74f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1987,17 +1987,12 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init}, }; -void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) -{ - kfree(dpu_cfg); -} - -struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) +const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev) { int i; struct dpu_mdss_cfg *dpu_cfg; - dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); + dpu_cfg = devm_kzalloc(dev, sizeof(*dpu_cfg), GFP_KERNEL); if (!dpu_cfg) return ERR_PTR(-ENOMEM); @@ -2009,7 +2004,7 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) } DPU_ERROR("unsupported chipset id:%X\n", hw_rev); - dpu_hw_catalog_deinit(dpu_cfg); + return ERR_PTR(-ENODEV); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 60b403ac9f0f..c317fa27daa0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -884,16 +884,11 @@ struct dpu_mdss_hw_cfg_handler { /** * dpu_hw_catalog_init - dpu hardware catalog init API retrieves * hardcoded target specific catalog information in config structure + * @dev: DPU device * @hw_rev: caller needs provide the hardware revision. * * Return: dpu config structure */ -struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); - -/** - * dpu_hw_catalog_deinit - dpu hardware catalog cleanup - * @dpu_cfg: pointer returned from init function - */ -void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); +const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev); #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 6f20d6b6dddd..184a1b27b13d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -158,7 +158,7 @@ static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, } static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc, - struct dpu_mdss_cfg *m, + const struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *b) { @@ -186,7 +186,7 @@ static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, }; struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, - struct dpu_mdss_cfg *m) + const struct dpu_mdss_cfg *m) { struct dpu_hw_dsc *c; struct dpu_dsc_cfg *cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h index b39ee4ed32f7..45e4118f1fa2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -64,7 +64,7 @@ struct dpu_hw_dsc { * Returns: Error code or allocated dpu_hw_dsc context */ struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr, - struct dpu_mdss_cfg *m); + const struct dpu_mdss_cfg *m); /** * dpu_hw_dsc_destroy - destroys dsc driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 01bb2d84c3a0..d83503ea2419 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -398,7 +398,7 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx) return intr_status; } -static void __intr_offset(struct dpu_mdss_cfg *m, +static void __intr_offset(const struct dpu_mdss_cfg *m, void __iomem *addr, struct dpu_hw_blk_reg_map *hw) { hw->base_off = addr; @@ -406,7 +406,7 @@ static void __intr_offset(struct dpu_mdss_cfg *m, } struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, - struct dpu_mdss_cfg *m) + const struct dpu_mdss_cfg *m) { struct dpu_hw_intr *intr; int nirq = MDP_INTR_MAX * 32; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 4154c5e2b4ae..46443955443c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -67,7 +67,7 @@ struct dpu_hw_intr { * @m : pointer to mdss catalog data */ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, - struct dpu_mdss_cfg *m); + const struct dpu_mdss_cfg *m); /** * dpu_hw_intr_destroy(): Cleanup interrutps hw object diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index ab7f1a4cc578..da4c7e4f304b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -761,7 +761,7 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, void __iomem *addr, - struct dpu_mdss_cfg *catalog, + const struct dpu_mdss_cfg *catalog, struct dpu_hw_blk_reg_map *b) { int i; @@ -782,7 +782,7 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, } struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, - void __iomem *addr, struct dpu_mdss_cfg *catalog, + void __iomem *addr, const struct dpu_mdss_cfg *catalog, bool is_virtual_pipe) { struct dpu_hw_pipe *hw_pipe; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index a81e16657d61..7f7338fcddeb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -360,7 +360,7 @@ struct dpu_hw_sspp_ops { struct dpu_hw_pipe { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; const struct dpu_mdp_cfg *mdp; /* Pipe */ @@ -381,7 +381,7 @@ struct dpu_kms; * @is_virtual_pipe: is this pipe virtual pipe */ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, - void __iomem *addr, struct dpu_mdss_cfg *catalog, + void __iomem *addr, const struct dpu_mdss_cfg *catalog, bool is_virtual_pipe); /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e23e2552e802..324f01b92433 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -745,7 +745,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) unsigned int num_encoders; struct msm_drm_private *priv; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; int max_crtc_count; @@ -842,8 +842,6 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_rm_destroy(&dpu_kms->rm); dpu_kms->rm_init = false; - if (dpu_kms->catalog) - dpu_hw_catalog_deinit(dpu_kms->catalog); dpu_kms->catalog = NULL; if (dpu_kms->vbif[VBIF_NRT]) @@ -905,7 +903,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k { int i; struct dpu_kms *dpu_kms; - struct dpu_mdss_cfg *cat; + const struct dpu_mdss_cfg *cat; struct dpu_hw_mdp *top; dpu_kms = to_dpu_kms(kms); @@ -1095,7 +1093,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); - dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); + dpu_kms->catalog = dpu_hw_catalog_init(dev->dev, dpu_kms->core_rev); if (IS_ERR_OR_NULL(dpu_kms->catalog)) { rc = PTR_ERR(dpu_kms->catalog); if (!dpu_kms->catalog) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index 832a0769f2e7..ed80ed6784ee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -69,7 +69,7 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; int core_rev; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX], *reg_dma; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b887f45596f3..7899418c5ca3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -106,7 +106,7 @@ struct dpu_plane { bool is_rt_pipe; bool is_virtual; struct list_head mplane_list; - struct dpu_mdss_cfg *catalog; + const struct dpu_mdss_cfg *catalog; }; static const uint64_t supported_format_modifiers[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 06f03e7081bc..73b3442e7467 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -95,7 +95,7 @@ int dpu_rm_destroy(struct dpu_rm *rm) } int dpu_rm_init(struct dpu_rm *rm, - struct dpu_mdss_cfg *cat, + const struct dpu_mdss_cfg *cat, void __iomem *mmio) { int rc, i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 2f34a31d8d0d..59de72b381f9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -42,7 +42,7 @@ struct dpu_rm { * @Return: 0 on Success otherwise -ERROR */ int dpu_rm_init(struct dpu_rm *rm, - struct dpu_mdss_cfg *cat, + const struct dpu_mdss_cfg *cat, void __iomem *mmio); /** From de7d480f5e8ca6eace02a725abdadb9ea13294ef Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 2 Jun 2022 23:24:47 +0300 Subject: [PATCH 08/46] drm/msm/dpu: make dpu hardware catalog static const Replace superfluous cfg_init functions, which just assign a static config to the struct dpu_mdss_cfg, with static instances of struct dpu_mdss_cfg. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/488166/ Link: https://lore.kernel.org/r/20220602202447.1755115-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 479 ++++++++---------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- 3 files changed, 215 insertions(+), 271 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 535337a9e74f..de4291936cb2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1722,285 +1722,230 @@ static const struct dpu_perf_cfg qcm2290_perf_data = { .bw_inefficiency_factor = 120, }; /************************************************************* - * Hardware catalog init + * Hardware catalog *************************************************************/ -/* - * msm8998_cfg_init(): populate sdm845 dpu sub-blocks reg offsets - * and instance counts. - */ -static void msm8998_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &msm8998_dpu_caps, - .mdp_count = ARRAY_SIZE(msm8998_mdp), - .mdp = msm8998_mdp, - .ctl_count = ARRAY_SIZE(msm8998_ctl), - .ctl = msm8998_ctl, - .sspp_count = ARRAY_SIZE(msm8998_sspp), - .sspp = msm8998_sspp, - .mixer_count = ARRAY_SIZE(msm8998_lm), - .mixer = msm8998_lm, - .dspp_count = ARRAY_SIZE(msm8998_dspp), - .dspp = msm8998_dspp, - .pingpong_count = ARRAY_SIZE(sdm845_pp), - .pingpong = sdm845_pp, - .intf_count = ARRAY_SIZE(msm8998_intf), - .intf = msm8998_intf, - .vbif_count = ARRAY_SIZE(msm8998_vbif), - .vbif = msm8998_vbif, - .reg_dma_count = 0, - .perf = &msm8998_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, - }; -} - -/* - * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets - * and instance counts. - */ -static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sdm845_dpu_caps, - .mdp_count = ARRAY_SIZE(sdm845_mdp), - .mdp = sdm845_mdp, - .ctl_count = ARRAY_SIZE(sdm845_ctl), - .ctl = sdm845_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sdm845_lm), - .mixer = sdm845_lm, - .pingpong_count = ARRAY_SIZE(sdm845_pp), - .pingpong = sdm845_pp, - .dsc_count = ARRAY_SIZE(sdm845_dsc), - .dsc = sdm845_dsc, - .intf_count = ARRAY_SIZE(sdm845_intf), - .intf = sdm845_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sdm845_regdma, - .perf = &sdm845_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, - }; -} - -/* - * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets - * and instance counts. - */ -static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sc7180_dpu_caps, - .mdp_count = ARRAY_SIZE(sc7180_mdp), - .mdp = sc7180_mdp, - .ctl_count = ARRAY_SIZE(sc7180_ctl), - .ctl = sc7180_ctl, - .sspp_count = ARRAY_SIZE(sc7180_sspp), - .sspp = sc7180_sspp, - .mixer_count = ARRAY_SIZE(sc7180_lm), - .mixer = sc7180_lm, - .dspp_count = ARRAY_SIZE(sc7180_dspp), - .dspp = sc7180_dspp, - .pingpong_count = ARRAY_SIZE(sc7180_pp), - .pingpong = sc7180_pp, - .intf_count = ARRAY_SIZE(sc7180_intf), - .intf = sc7180_intf, - .wb_count = ARRAY_SIZE(sm8250_wb), - .wb = sm8250_wb, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sdm845_regdma, - .perf = &sc7180_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, - }; -} - -/* - * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets - * and instance counts. - */ -static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sm8150_dpu_caps, - .mdp_count = ARRAY_SIZE(sdm845_mdp), - .mdp = sdm845_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sm8150_intf), - .intf = sm8150_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8150_regdma, - .perf = &sm8150_perf_data, - .mdss_irqs = IRQ_SDM845_MASK, - }; -} - -/* - * sc8180x_cfg_init(): populate sc8180 dpu sub-blocks reg offsets - * and instance counts. - */ -static void sc8180x_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sc8180x_dpu_caps, - .mdp_count = ARRAY_SIZE(sc8180x_mdp), - .mdp = sc8180x_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sdm845_sspp), - .sspp = sdm845_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sc8180x_intf), - .intf = sc8180x_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sm8150_regdma, - .perf = &sc8180x_perf_data, - .mdss_irqs = IRQ_SC8180X_MASK, - }; -} - -/* - * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets - * and instance counts. - */ -static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sm8250_dpu_caps, - .mdp_count = ARRAY_SIZE(sm8250_mdp), - .mdp = sm8250_mdp, - .ctl_count = ARRAY_SIZE(sm8150_ctl), - .ctl = sm8150_ctl, - .sspp_count = ARRAY_SIZE(sm8250_sspp), - .sspp = sm8250_sspp, - .mixer_count = ARRAY_SIZE(sm8150_lm), - .mixer = sm8150_lm, - .dspp_count = ARRAY_SIZE(sm8150_dspp), - .dspp = sm8150_dspp, - .pingpong_count = ARRAY_SIZE(sm8150_pp), - .pingpong = sm8150_pp, - .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), - .merge_3d = sm8150_merge_3d, - .intf_count = ARRAY_SIZE(sm8150_intf), - .intf = sm8150_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .wb_count = ARRAY_SIZE(sm8250_wb), - .wb = sm8250_wb, - .reg_dma_count = 1, - .dma_cfg = &sm8250_regdma, - .perf = &sm8250_perf_data, - .mdss_irqs = IRQ_SM8250_MASK, - }; -} - -static void sc7280_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &sc7280_dpu_caps, - .mdp_count = ARRAY_SIZE(sc7280_mdp), - .mdp = sc7280_mdp, - .ctl_count = ARRAY_SIZE(sc7280_ctl), - .ctl = sc7280_ctl, - .sspp_count = ARRAY_SIZE(sc7280_sspp), - .sspp = sc7280_sspp, - .mixer_count = ARRAY_SIZE(sc7280_lm), - .mixer = sc7280_lm, - .pingpong_count = ARRAY_SIZE(sc7280_pp), - .pingpong = sc7280_pp, - .intf_count = ARRAY_SIZE(sc7280_intf), - .intf = sc7280_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .perf = &sc7280_perf_data, - .mdss_irqs = IRQ_SC7280_MASK, - }; -} - - -/* - * qcm2290_cfg_init(): populate qcm2290 dpu sub-blocks reg offsets - * and instance counts. - */ -static void qcm2290_cfg_init(struct dpu_mdss_cfg *dpu_cfg) -{ - *dpu_cfg = (struct dpu_mdss_cfg){ - .caps = &qcm2290_dpu_caps, - .mdp_count = ARRAY_SIZE(qcm2290_mdp), - .mdp = qcm2290_mdp, - .ctl_count = ARRAY_SIZE(qcm2290_ctl), - .ctl = qcm2290_ctl, - .sspp_count = ARRAY_SIZE(qcm2290_sspp), - .sspp = qcm2290_sspp, - .mixer_count = ARRAY_SIZE(qcm2290_lm), - .mixer = qcm2290_lm, - .dspp_count = ARRAY_SIZE(qcm2290_dspp), - .dspp = qcm2290_dspp, - .pingpong_count = ARRAY_SIZE(qcm2290_pp), - .pingpong = qcm2290_pp, - .intf_count = ARRAY_SIZE(qcm2290_intf), - .intf = qcm2290_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, - .reg_dma_count = 1, - .dma_cfg = &sdm845_regdma, - .perf = &qcm2290_perf_data, - .mdss_irqs = IRQ_SC7180_MASK, - }; -} - -static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { - { .hw_rev = DPU_HW_VER_300, .cfg_init = msm8998_cfg_init}, - { .hw_rev = DPU_HW_VER_301, .cfg_init = msm8998_cfg_init}, - { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, - { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, - { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, - { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init}, - { .hw_rev = DPU_HW_VER_510, .cfg_init = sc8180x_cfg_init}, - { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init}, - { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, - { .hw_rev = DPU_HW_VER_650, .cfg_init = qcm2290_cfg_init}, - { .hw_rev = DPU_HW_VER_720, .cfg_init = sc7280_cfg_init}, +static const struct dpu_mdss_cfg msm8998_dpu_cfg = { + .caps = &msm8998_dpu_caps, + .mdp_count = ARRAY_SIZE(msm8998_mdp), + .mdp = msm8998_mdp, + .ctl_count = ARRAY_SIZE(msm8998_ctl), + .ctl = msm8998_ctl, + .sspp_count = ARRAY_SIZE(msm8998_sspp), + .sspp = msm8998_sspp, + .mixer_count = ARRAY_SIZE(msm8998_lm), + .mixer = msm8998_lm, + .dspp_count = ARRAY_SIZE(msm8998_dspp), + .dspp = msm8998_dspp, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .intf_count = ARRAY_SIZE(msm8998_intf), + .intf = msm8998_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .reg_dma_count = 0, + .perf = &msm8998_perf_data, + .mdss_irqs = IRQ_SM8250_MASK, }; -const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev) +static const struct dpu_mdss_cfg sdm845_dpu_cfg = { + .caps = &sdm845_dpu_caps, + .mdp_count = ARRAY_SIZE(sdm845_mdp), + .mdp = sdm845_mdp, + .ctl_count = ARRAY_SIZE(sdm845_ctl), + .ctl = sdm845_ctl, + .sspp_count = ARRAY_SIZE(sdm845_sspp), + .sspp = sdm845_sspp, + .mixer_count = ARRAY_SIZE(sdm845_lm), + .mixer = sdm845_lm, + .pingpong_count = ARRAY_SIZE(sdm845_pp), + .pingpong = sdm845_pp, + .dsc_count = ARRAY_SIZE(sdm845_dsc), + .dsc = sdm845_dsc, + .intf_count = ARRAY_SIZE(sdm845_intf), + .intf = sdm845_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sdm845_regdma, + .perf = &sdm845_perf_data, + .mdss_irqs = IRQ_SDM845_MASK, +}; + +static const struct dpu_mdss_cfg sc7180_dpu_cfg = { + .caps = &sc7180_dpu_caps, + .mdp_count = ARRAY_SIZE(sc7180_mdp), + .mdp = sc7180_mdp, + .ctl_count = ARRAY_SIZE(sc7180_ctl), + .ctl = sc7180_ctl, + .sspp_count = ARRAY_SIZE(sc7180_sspp), + .sspp = sc7180_sspp, + .mixer_count = ARRAY_SIZE(sc7180_lm), + .mixer = sc7180_lm, + .dspp_count = ARRAY_SIZE(sc7180_dspp), + .dspp = sc7180_dspp, + .pingpong_count = ARRAY_SIZE(sc7180_pp), + .pingpong = sc7180_pp, + .intf_count = ARRAY_SIZE(sc7180_intf), + .intf = sc7180_intf, + .wb_count = ARRAY_SIZE(sm8250_wb), + .wb = sm8250_wb, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sdm845_regdma, + .perf = &sc7180_perf_data, + .mdss_irqs = IRQ_SC7180_MASK, +}; + +static const struct dpu_mdss_cfg sm8150_dpu_cfg = { + .caps = &sm8150_dpu_caps, + .mdp_count = ARRAY_SIZE(sdm845_mdp), + .mdp = sdm845_mdp, + .ctl_count = ARRAY_SIZE(sm8150_ctl), + .ctl = sm8150_ctl, + .sspp_count = ARRAY_SIZE(sdm845_sspp), + .sspp = sdm845_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .pingpong_count = ARRAY_SIZE(sm8150_pp), + .pingpong = sm8150_pp, + .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), + .merge_3d = sm8150_merge_3d, + .intf_count = ARRAY_SIZE(sm8150_intf), + .intf = sm8150_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8150_regdma, + .perf = &sm8150_perf_data, + .mdss_irqs = IRQ_SDM845_MASK, +}; + +static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { + .caps = &sc8180x_dpu_caps, + .mdp_count = ARRAY_SIZE(sc8180x_mdp), + .mdp = sc8180x_mdp, + .ctl_count = ARRAY_SIZE(sm8150_ctl), + .ctl = sm8150_ctl, + .sspp_count = ARRAY_SIZE(sdm845_sspp), + .sspp = sdm845_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .pingpong_count = ARRAY_SIZE(sm8150_pp), + .pingpong = sm8150_pp, + .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), + .merge_3d = sm8150_merge_3d, + .intf_count = ARRAY_SIZE(sc8180x_intf), + .intf = sc8180x_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sm8150_regdma, + .perf = &sc8180x_perf_data, + .mdss_irqs = IRQ_SC8180X_MASK, +}; + +static const struct dpu_mdss_cfg sm8250_dpu_cfg = { + .caps = &sm8250_dpu_caps, + .mdp_count = ARRAY_SIZE(sm8250_mdp), + .mdp = sm8250_mdp, + .ctl_count = ARRAY_SIZE(sm8150_ctl), + .ctl = sm8150_ctl, + .sspp_count = ARRAY_SIZE(sm8250_sspp), + .sspp = sm8250_sspp, + .mixer_count = ARRAY_SIZE(sm8150_lm), + .mixer = sm8150_lm, + .dspp_count = ARRAY_SIZE(sm8150_dspp), + .dspp = sm8150_dspp, + .pingpong_count = ARRAY_SIZE(sm8150_pp), + .pingpong = sm8150_pp, + .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), + .merge_3d = sm8150_merge_3d, + .intf_count = ARRAY_SIZE(sm8150_intf), + .intf = sm8150_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .wb_count = ARRAY_SIZE(sm8250_wb), + .wb = sm8250_wb, + .reg_dma_count = 1, + .dma_cfg = &sm8250_regdma, + .perf = &sm8250_perf_data, + .mdss_irqs = IRQ_SM8250_MASK, +}; + +static const struct dpu_mdss_cfg sc7280_dpu_cfg = { + .caps = &sc7280_dpu_caps, + .mdp_count = ARRAY_SIZE(sc7280_mdp), + .mdp = sc7280_mdp, + .ctl_count = ARRAY_SIZE(sc7280_ctl), + .ctl = sc7280_ctl, + .sspp_count = ARRAY_SIZE(sc7280_sspp), + .sspp = sc7280_sspp, + .mixer_count = ARRAY_SIZE(sc7280_lm), + .mixer = sc7280_lm, + .pingpong_count = ARRAY_SIZE(sc7280_pp), + .pingpong = sc7280_pp, + .intf_count = ARRAY_SIZE(sc7280_intf), + .intf = sc7280_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sc7280_perf_data, + .mdss_irqs = IRQ_SC7280_MASK, +}; + +static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { + .caps = &qcm2290_dpu_caps, + .mdp_count = ARRAY_SIZE(qcm2290_mdp), + .mdp = qcm2290_mdp, + .ctl_count = ARRAY_SIZE(qcm2290_ctl), + .ctl = qcm2290_ctl, + .sspp_count = ARRAY_SIZE(qcm2290_sspp), + .sspp = qcm2290_sspp, + .mixer_count = ARRAY_SIZE(qcm2290_lm), + .mixer = qcm2290_lm, + .dspp_count = ARRAY_SIZE(qcm2290_dspp), + .dspp = qcm2290_dspp, + .pingpong_count = ARRAY_SIZE(qcm2290_pp), + .pingpong = qcm2290_pp, + .intf_count = ARRAY_SIZE(qcm2290_intf), + .intf = qcm2290_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = &sdm845_regdma, + .perf = &qcm2290_perf_data, + .mdss_irqs = IRQ_SC7180_MASK, +}; + +static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { + { .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg}, + { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg}, + { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg}, + { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg}, + { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg}, + { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg}, + { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, + { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, + { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, + { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, + { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, +}; + +const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) { int i; struct dpu_mdss_cfg *dpu_cfg; - dpu_cfg = devm_kzalloc(dev, sizeof(*dpu_cfg), GFP_KERNEL); + dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); if (!dpu_cfg) return ERR_PTR(-ENOMEM); for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { - if (cfg_handler[i].hw_rev == hw_rev) { - cfg_handler[i].cfg_init(dpu_cfg); - return dpu_cfg; - } + if (cfg_handler[i].hw_rev == hw_rev) + return cfg_handler[i].dpu_cfg; } DPU_ERROR("unsupported chipset id:%X\n", hw_rev); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index c317fa27daa0..71fe4c505f5b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -878,17 +878,16 @@ struct dpu_mdss_cfg { struct dpu_mdss_hw_cfg_handler { u32 hw_rev; - void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); + const struct dpu_mdss_cfg *dpu_cfg; }; /** * dpu_hw_catalog_init - dpu hardware catalog init API retrieves * hardcoded target specific catalog information in config structure - * @dev: DPU device * @hw_rev: caller needs provide the hardware revision. * * Return: dpu config structure */ -const struct dpu_mdss_cfg *dpu_hw_catalog_init(struct device *dev, u32 hw_rev); +const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 324f01b92433..1b3781f276d1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1093,7 +1093,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev); - dpu_kms->catalog = dpu_hw_catalog_init(dev->dev, dpu_kms->core_rev); + dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev); if (IS_ERR_OR_NULL(dpu_kms->catalog)) { rc = PTR_ERR(dpu_kms->catalog); if (!dpu_kms->catalog) From b1ed585a16da8ad3ee426309d684a7a4a919ae56 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 7 May 2022 14:59:41 +0300 Subject: [PATCH 09/46] drm/msm/dpu: dont_use IS_ERR_OR_NULL for encoder phys backends The functions dpu_encoder_phys_foo_init() can not return NULL. Replace corresponding IS_ERR_OR_NULL() checks with just IS_ERR(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/485452/ Link: https://lore.kernel.org/r/20220507115942.1705872-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 5e88ddd0f4fe..d14415b58e5b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2142,10 +2142,10 @@ static int dpu_encoder_virt_add_phys_encs( if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) { enc = dpu_encoder_phys_vid_init(params); - if (IS_ERR_OR_NULL(enc)) { + if (IS_ERR(enc)) { DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", PTR_ERR(enc)); - return enc == NULL ? -EINVAL : PTR_ERR(enc); + return PTR_ERR(enc); } dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; @@ -2155,10 +2155,10 @@ static int dpu_encoder_virt_add_phys_encs( if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { enc = dpu_encoder_phys_cmd_init(params); - if (IS_ERR_OR_NULL(enc)) { + if (IS_ERR(enc)) { DPU_ERROR_ENC(dpu_enc, "failed to init cmd enc: %ld\n", PTR_ERR(enc)); - return enc == NULL ? -EINVAL : PTR_ERR(enc); + return PTR_ERR(enc); } dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; @@ -2168,10 +2168,10 @@ static int dpu_encoder_virt_add_phys_encs( if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) { enc = dpu_encoder_phys_wb_init(params); - if (IS_ERR_OR_NULL(enc)) { + if (IS_ERR(enc)) { DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", PTR_ERR(enc)); - return enc == NULL ? -EINVAL : PTR_ERR(enc); + return PTR_ERR(enc); } dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; From b6529e33761f8c2f482d0f7e37e4d7a054cc1d9f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 7 May 2022 14:59:42 +0300 Subject: [PATCH 10/46] drm/msm/dpu: drop enum msm_display_caps After the commit c46f0d69039c ("drm/msm: remove unused hotplug and edid macros from msm_drv.h") the msm_display_caps enum contains two bits describing whether the encoder should work in video or command mode. Drop the enum and replace capabilities field in struct msm_display_info with boolean is_cmd_mode field. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/485454/ Link: https://lore.kernel.org/r/20220507115942.1705872-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 31 +++++++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 5 +--- drivers/gpu/drm/msm/msm_drv.h | 10 ------- 4 files changed, 16 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d14415b58e5b..5ccaf35929a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -634,7 +634,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, } if (hw_mdptop->ops.setup_vsync_source && - disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { + disp_info->is_cmd_mode) { for (i = 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; @@ -718,8 +718,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, } dpu_enc = to_dpu_encoder_virt(drm_enc); priv = drm_enc->dev->dev_private; - is_vid_mode = dpu_enc->disp_info.capabilities & - MSM_DISPLAY_CAP_VID_MODE; + is_vid_mode = !dpu_enc->disp_info.is_cmd_mode; /* * when idle_pc is not supported, process only KICKOFF, STOP and MODESET @@ -1603,7 +1602,7 @@ void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc) /* update only for command mode primary ctl */ if ((phys == dpu_enc->cur_master) && - (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) + disp_info->is_cmd_mode && ctl->ops.trigger_pending) ctl->ops.trigger_pending(ctl); } @@ -2139,20 +2138,19 @@ static int dpu_encoder_virt_add_phys_encs( return -EINVAL; } - if (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE) { - enc = dpu_encoder_phys_vid_init(params); + + if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) { + enc = dpu_encoder_phys_wb_init(params); if (IS_ERR(enc)) { - DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", + DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", PTR_ERR(enc)); return PTR_ERR(enc); } dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; ++dpu_enc->num_phys_encs; - } - - if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) { + } else if (disp_info->is_cmd_mode) { enc = dpu_encoder_phys_cmd_init(params); if (IS_ERR(enc)) { @@ -2163,14 +2161,12 @@ static int dpu_encoder_virt_add_phys_encs( dpu_enc->phys_encs[dpu_enc->num_phys_encs] = enc; ++dpu_enc->num_phys_encs; - } - - if (disp_info->intf_type == DRM_MODE_ENCODER_VIRTUAL) { - enc = dpu_encoder_phys_wb_init(params); + } else { + enc = dpu_encoder_phys_vid_init(params); if (IS_ERR(enc)) { - DPU_ERROR_ENC(dpu_enc, "failed to init wb enc: %ld\n", - PTR_ERR(enc)); + DPU_ERROR_ENC(dpu_enc, "failed to init vid enc: %ld\n", + PTR_ERR(enc)); return PTR_ERR(enc); } @@ -2230,8 +2226,7 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles); - if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) || - (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE)) + if (disp_info->intf_type != DRM_MODE_ENCODER_VIRTUAL) dpu_enc->idle_pc_supported = dpu_kms->catalog->caps->has_idle_pc; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 781d41c91994..861870ac8ae7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -21,19 +21,19 @@ /** * struct msm_display_info - defines display properties * @intf_type: DRM_MODE_ENCODER_ type - * @capabilities: Bitmask of display flags * @num_of_h_tiles: Number of horizontal tiles in case of split interface * @h_tile_instance: Controller instance used per tile. Number of elements is * based on num_of_h_tiles + * @is_cmd_mode Boolean to indicate if the CMD mode is requested * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is * used instead of panel TE in cmd mode panels * @dsc: DSC configuration data for DSC-enabled displays */ struct msm_display_info { int intf_type; - uint32_t capabilities; uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; + bool is_cmd_mode; bool is_te_using_watchdog_timer; struct msm_display_dsc_config *dsc; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1b3781f276d1..a2d71f0c96af 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -582,9 +582,7 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, } info.h_tile_instance[info.num_of_h_tiles++] = i; - info.capabilities = msm_dsi_is_cmd_mode(priv->dsi[i]) ? - MSM_DISPLAY_CAP_CMD_MODE : - MSM_DISPLAY_CAP_VID_MODE; + info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]); @@ -637,7 +635,6 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, info.num_of_h_tiles = 1; info.h_tile_instance[0] = i; - info.capabilities = MSM_DISPLAY_CAP_VID_MODE; info.intf_type = encoder->encoder_type; rc = dpu_encoder_setup(dev, encoder, &info); if (rc) { diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 099a67d10c3a..ae49e56ac026 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -61,16 +61,6 @@ enum msm_dp_controller { #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 -/** - * enum msm_display_caps - features/capabilities supported by displays - * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported - * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported - */ -enum msm_display_caps { - MSM_DISPLAY_CAP_VID_MODE = BIT(0), - MSM_DISPLAY_CAP_CMD_MODE = BIT(1), -}; - /** * enum msm_event_wait - type of HW events to wait for * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW From b4a624acabe99f2ea912e895529b8b37d1fa909d Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 16 Jun 2022 12:01:22 -0700 Subject: [PATCH 11/46] drm/msm/dpu: move intf and wb assignment to dpu_encoder_setup_display() intf and wb resources are not dependent on the rm global state so need not be allocated during dpu_encoder_virt_atomic_mode_set(). Move the allocation of intf and wb resources to dpu_encoder_setup_display() so that we can utilize the hw caps even during atomic_check() phase. Since dpu_encoder_setup_display() already has protection against setting invalid intf_idx and wb_idx, these checks can now be dropped as well. changes in v2: - add phys->hw_intf and phys->hw_wb checks back changes in v3: - correct the Fixes tag Fixes: e02a559a720f ("drm/msm/dpu: make changes to dpu_encoder to support virtual encoder") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489885/ Link: https://lore.kernel.org/r/1655406084-17407-1-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 ++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 5ccaf35929a0..d61874b069c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1047,24 +1047,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, phys->hw_pp = dpu_enc->hw_pp[i]; phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); - if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) - phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx); - - if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX) - phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx); - - if (!phys->hw_intf && !phys->hw_wb) { - DPU_ERROR_ENC(dpu_enc, - "no intf or wb block assigned at idx: %d\n", i); - return; - } - - if (phys->hw_intf && phys->hw_wb) { - DPU_ERROR_ENC(dpu_enc, - "invalid phys both intf and wb block at idx: %d\n", i); - return; - } - phys->cached_mode = crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set) phys->ops.atomic_mode_set(phys, crtc_state, conn_state); @@ -2289,7 +2271,25 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; atomic_set(&phys->vsync_cnt, 0); atomic_set(&phys->underrun_cnt, 0); + + if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX) + phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx); + + if (phys->wb_idx >= WB_0 && phys->wb_idx < WB_MAX) + phys->hw_wb = dpu_rm_get_wb(&dpu_kms->rm, phys->wb_idx); + + if (!phys->hw_intf && !phys->hw_wb) { + DPU_ERROR_ENC(dpu_enc, "no intf or wb block assigned at idx: %d\n", i); + ret = -EINVAL; + } + + if (phys->hw_intf && phys->hw_wb) { + DPU_ERROR_ENC(dpu_enc, + "invalid phys both intf and wb block at idx: %d\n", i); + ret = -EINVAL; + } } + mutex_unlock(&dpu_enc->enc_lock); return ret; From a370cc392e075de5a4b7f3fb27cdeec0d70b5893 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 16 Jun 2022 12:01:23 -0700 Subject: [PATCH 12/46] drm/msm/dpu: fix maxlinewidth for writeback block Writeback block for sm8250 was using the default maxlinewidth of 2048. But this is not right as it supports upto 4096. This should have no effect on most resolutions as we are still limiting upto maxlinewidth of SSPP for adding the modes. Fix the maxlinewidth for writeback block on sm8250. changes in v3: - correct the Fixes tag Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489887/ Link: https://lore.kernel.org/r/1655406084-17407-2-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index de4291936cb2..c7d46cd8c35e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1288,7 +1288,7 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { * Writeback blocks config *************************************************************/ #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \ - __xin_id, vbif_id, _reg, _wb_done_bit) \ + __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \ { \ .name = _name, .id = _id, \ .base = _base, .len = 0x2c8, \ @@ -1298,13 +1298,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { .clk_ctrl = _clk_ctrl, \ .xin_id = __xin_id, \ .vbif_idx = vbif_id, \ - .maxlinewidth = DEFAULT_DPU_LINE_WIDTH, \ + .maxlinewidth = _max_linewidth, \ .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ } static const struct dpu_wb_cfg sm8250_wb[] = { WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, - VBIF_RT, MDP_SSPP_TOP0_INTR, 4), + VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), }; /************************************************************* From 4edea8d305873336a626c5f4ce17cb8751059054 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 16 Jun 2022 12:01:24 -0700 Subject: [PATCH 13/46] drm/msm/dpu: remove hard-coded linewidth limit for writeback Remove the hard-coded limit for writeback and lets start using the one from catalog instead. changes in v3: - correct the Fixes tag Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489888/ Link: https://lore.kernel.org/r/1655406084-17407-3-git-send-email-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 2ba9e64445b4..d301070cd4a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -20,8 +20,6 @@ #include "dpu_crtc.h" #include "disp/msm_disp_snapshot.h" -#define DEFAULT_MAX_WRITEBACK_WIDTH 2048 - #define to_dpu_encoder_phys_wb(x) \ container_of(x, struct dpu_encoder_phys_wb, base) @@ -278,9 +276,9 @@ static int dpu_encoder_phys_wb_atomic_check( DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height, mode->vdisplay); return -EINVAL; - } else if (fb->width > DEFAULT_MAX_WRITEBACK_WIDTH) { + } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) { DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n", - fb->width, DEFAULT_MAX_WRITEBACK_WIDTH); + fb->width, phys_enc->hw_wb->caps->maxlinewidth); return -EINVAL; } From 58fc5d186db44cc33bbd9622eff18a15a995a08b Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Wed, 22 Jun 2022 10:18:32 -0700 Subject: [PATCH 14/46] drm/msm/dpu: Move LM CRC code into separate method Move layer mixer-specific section of dpu_crtc_get_crc() into a separate helper method. This way, we can make it easier to get CRCs from other HW blocks by adding other get_crc helper methods. Changes since V1: - Move common bitmasks to dpu_hw_util.h - Move common CRC methods to dpu_hw_util.c - Update copyrights - Change crcs array to a dynamically allocated array and added it as a member of crtc_state Changes since V2: - Put changes for hw_util into a separate commit - Revert crcs array to a static array - Add else case for set_crc_source to return EINVAL if no valid source is selected - Add DPU_CRTC_MAX_CRC_ENTRIES macro Changes since V3: - Move crcs array into dpu_crtc_get_lm_crc - Remove comment about crcs array in dpu_crtc_state struct - Revert `lm` rename - Remove DPU_CRTC_MAX_CRC_ENTRIES macro - Return EINVAL in dpu_crtc_get_crc if no valid CRC source is set Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/490735/ Link: https://lore.kernel.org/r/20220622171835.7558-2-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 65 +++++++++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + 2 files changed, 43 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b56f777dbd0e..b57140c3671a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -99,17 +100,32 @@ static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, return 0; } +static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) +{ + struct dpu_crtc_mixer *m; + int i; + + for (i = 0; i < crtc_state->num_mixers; ++i) { + m = &crtc_state->mixers[i]; + + if (!m->hw_lm || !m->hw_lm->ops.setup_misr) + continue; + + /* Calculate MISR over 1 frame */ + m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); + } +} + static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) { enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); enum dpu_crtc_crc_source current_source; struct dpu_crtc_state *crtc_state; struct drm_device *drm_dev = crtc->dev; - struct dpu_crtc_mixer *m; bool was_enabled; bool enable = false; - int i, ret = 0; + int ret = 0; if (source < 0) { DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index); @@ -146,16 +162,10 @@ static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) crtc_state->crc_frame_skip_count = 0; - for (i = 0; i < crtc_state->num_mixers; ++i) { - m = &crtc_state->mixers[i]; - - if (!m->hw_lm || !m->hw_lm->ops.setup_misr) - continue; - - /* Calculate MISR over 1 frame */ - m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); - } - + if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) + dpu_crtc_setup_lm_misr(crtc_state); + else + ret = -EINVAL; cleanup: drm_modeset_unlock(&crtc->mutex); @@ -174,26 +184,17 @@ static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc) return dpu_encoder_get_vsync_count(encoder); } - -static int dpu_crtc_get_crc(struct drm_crtc *crtc) +static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, + struct dpu_crtc_state *crtc_state) { - struct dpu_crtc_state *crtc_state; struct dpu_crtc_mixer *m; u32 crcs[CRTC_DUAL_MIXERS]; - int i = 0; int rc = 0; - - crtc_state = to_dpu_crtc_state(crtc->state); + int i; BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers)); - /* Skip first 2 frames in case of "uncooked" CRCs */ - if (crtc_state->crc_frame_skip_count < 2) { - crtc_state->crc_frame_skip_count++; - return 0; - } - for (i = 0; i < crtc_state->num_mixers; ++i) { m = &crtc_state->mixers[i]; @@ -214,6 +215,22 @@ static int dpu_crtc_get_crc(struct drm_crtc *crtc) drm_crtc_accurate_vblank_count(crtc), crcs); } +static int dpu_crtc_get_crc(struct drm_crtc *crtc) +{ + struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); + + /* Skip first 2 frames in case of "uncooked" CRCs */ + if (crtc_state->crc_frame_skip_count < 2) { + crtc_state->crc_frame_skip_count++; + return 0; + } + + if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) + return dpu_crtc_get_lm_crc(crtc, crtc_state); + + return -EINVAL; +} + static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, bool in_vblank_irq, int *vpos, int *hpos, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index b8785c394fcc..20df23fe74ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -201,6 +201,8 @@ struct dpu_crtc { * @mixers : List of active mixers * @num_ctls : Number of ctl paths in use * @hw_ctls : List of active ctl paths + * @crc_source : CRC source + * @crc_frame_skip_count: Number of frames skipped before getting CRC */ struct dpu_crtc_state { struct drm_crtc_state base; From d9e0f7a6631baf8b5abb2e7364101f05a5b4e7cb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 08:55:26 +0300 Subject: [PATCH 15/46] drm/msm/dp: "inline" dp_ctrl_set_clock_rate("ctrl_link") "ctrl_link" is the clock from DP_CTRL_PM module. The result of setting the rate for it would be a call to dev_pm_opp_set_rate(). Instead of saving the rate inside struct dss_module_power, call the devm_pm_opp_set_rate() directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/474712/ Link: https://lore.kernel.org/r/20220217055529.499829-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 7 +++++-- drivers/gpu/drm/msm/dp/dp_power.c | 33 +------------------------------ 2 files changed, 6 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 703249384e7c..4a9e4f0e9972 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1349,12 +1349,11 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) opts_dp->lanes = ctrl->link->link_params.num_lanes; opts_dp->link_rate = ctrl->link->link_params.rate / 100; opts_dp->ssc = drm_dp_max_downspread(dpcd); - dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link", - ctrl->link->link_params.rate * 1000); phy_configure(phy, &dp_io->phy_opts); phy_power_on(phy); + dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); @@ -1462,6 +1461,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) * link clock might have been adjusted as part of the * link maintenance. */ + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); @@ -1493,6 +1493,7 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_reset(ctrl->catalog); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1929,6 +1930,7 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) } } + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); @@ -1997,6 +1999,7 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl) if (ret) DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); + dev_pm_opp_set_rate(ctrl->dev, 0); ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); if (ret) { DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index d9e011775ad8..ccb7c42c862c 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -151,44 +151,13 @@ static int dp_power_clk_deinit(struct dp_power_private *power) return 0; } -static int dp_power_clk_set_link_rate(struct dp_power_private *power, - struct dss_clk *clk_arry, int num_clk, int enable) -{ - u32 rate; - int i, rc = 0; - - for (i = 0; i < num_clk; i++) { - if (clk_arry[i].clk) { - if (clk_arry[i].type == DSS_CLK_PCLK) { - if (enable) - rate = clk_arry[i].rate; - else - rate = 0; - - rc = dev_pm_opp_set_rate(power->dev, rate); - if (rc) - break; - } - - } - } - return rc; -} - static int dp_power_clk_set_rate(struct dp_power_private *power, enum dp_pm_type module, bool enable) { int rc = 0; struct dss_module_power *mp = &power->parser->mp[module]; - if (module == DP_CTRL_PM) { - rc = dp_power_clk_set_link_rate(power, mp->clk_config, mp->num_clk, enable); - if (rc) { - DRM_ERROR("failed to set link clks rate\n"); - return rc; - } - } else { - + if (module != DP_CTRL_PM) { if (enable) { rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); if (rc) { From 26345e0117234c89e9d581c63aa25f10e6b50517 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 08:55:27 +0300 Subject: [PATCH 16/46] drm/msm/dp: set stream_pixel rate directly The only clock for which we set the rate is the "stream_pixel". Rather than storing the rate and then setting it by looping over all the clocks, set the clock rate directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/474714/ Link: https://lore.kernel.org/r/20220217055529.499829-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_clk_util.c | 33 ---------------------------- drivers/gpu/drm/msm/dp/dp_clk_util.h | 9 -------- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +- drivers/gpu/drm/msm/dp/dp_parser.c | 7 ------ drivers/gpu/drm/msm/dp/dp_power.c | 10 --------- 5 files changed, 1 insertion(+), 60 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.c b/drivers/gpu/drm/msm/dp/dp_clk_util.c index 44a4fc59ff31..85abed31c68b 100644 --- a/drivers/gpu/drm/msm/dp/dp_clk_util.c +++ b/drivers/gpu/drm/msm/dp/dp_clk_util.c @@ -51,39 +51,6 @@ error: return rc; } -int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk) -{ - int i, rc = 0; - - for (i = 0; i < num_clk; i++) { - if (clk_arry[i].clk) { - if (clk_arry[i].type != DSS_CLK_AHB) { - DEV_DBG("%pS->%s: '%s' rate %ld\n", - __builtin_return_address(0), __func__, - clk_arry[i].clk_name, - clk_arry[i].rate); - rc = clk_set_rate(clk_arry[i].clk, - clk_arry[i].rate); - if (rc) { - DEV_ERR("%pS->%s: %s failed. rc=%d\n", - __builtin_return_address(0), - __func__, - clk_arry[i].clk_name, rc); - break; - } - } - } else { - DEV_ERR("%pS->%s: '%s' is not available\n", - __builtin_return_address(0), __func__, - clk_arry[i].clk_name); - rc = -EPERM; - break; - } - } - - return rc; -} - int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) { int i, rc = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.h b/drivers/gpu/drm/msm/dp/dp_clk_util.h index 067bf87f3d97..c3d59b5017a9 100644 --- a/drivers/gpu/drm/msm/dp/dp_clk_util.h +++ b/drivers/gpu/drm/msm/dp/dp_clk_util.h @@ -13,17 +13,9 @@ #define DEV_WARN(fmt, args...) pr_warn(fmt, ##args) #define DEV_ERR(fmt, args...) pr_err(fmt, ##args) -enum dss_clk_type { - DSS_CLK_AHB, /* no set rate. rate controlled through rpm */ - DSS_CLK_PCLK, -}; - struct dss_clk { struct clk *clk; /* clk handle */ char clk_name[32]; - enum dss_clk_type type; - unsigned long rate; - unsigned long max_rate; }; struct dss_module_power { @@ -33,6 +25,5 @@ struct dss_module_power { int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk); void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); -int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk); int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); #endif /* __DP_CLK_UTIL_H__ */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 4a9e4f0e9972..748339617ad4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1332,7 +1332,7 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, rate, name); if (num) - cfg->rate = rate; + clk_set_rate(cfg->clk, rate); else DRM_ERROR("%s clock doesn't exit to set rate %lu\n", name, rate); diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 8f9fed9fdafc..fc3d88c05f94 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -237,14 +237,12 @@ static int dp_parser_clock(struct dp_parser *parser) struct dss_clk *clk = &core_power->clk_config[core_clk_index]; strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); - clk->type = DSS_CLK_AHB; core_clk_index++; } else if (dp_parser_check_prefix("stream", clk_name) && stream_clk_index < stream_clk_count) { struct dss_clk *clk = &stream_power->clk_config[stream_clk_index]; strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); - clk->type = DSS_CLK_PCLK; stream_clk_index++; } else if (dp_parser_check_prefix("ctrl", clk_name) && ctrl_clk_index < ctrl_clk_count) { @@ -252,11 +250,6 @@ static int dp_parser_clock(struct dp_parser *parser) &ctrl_power->clk_config[ctrl_clk_index]; strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); ctrl_clk_index++; - if (dp_parser_check_prefix("ctrl_link", clk_name) || - dp_parser_check_prefix("stream_pixel", clk_name)) - clk->type = DSS_CLK_PCLK; - else - clk->type = DSS_CLK_AHB; } } diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index ccb7c42c862c..ffb84edb0f98 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -157,16 +157,6 @@ static int dp_power_clk_set_rate(struct dp_power_private *power, int rc = 0; struct dss_module_power *mp = &power->parser->mp[module]; - if (module != DP_CTRL_PM) { - if (enable) { - rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); - if (rc) { - DRM_ERROR("failed to set clks rate\n"); - return rc; - } - } - } - rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); if (rc) { DRM_ERROR("failed to %d clks, err: %d\n", enable, rc); From 7b37523fb1d1b2afe64d5fbd16a1ea72596e3663 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Wed, 22 Jun 2022 10:18:33 -0700 Subject: [PATCH 17/46] drm/msm/dpu: Move MISR methods to dpu_hw_util Move layer mixer specific MISR methods to generalized helper methods. This will make it easier to add CRC support for other blocks in the future. Changes since V2: - Reordered parameters so that offsets are after hw_blk_reg_map - Fixed mismatched whitespace in bitmask definitions Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/490732/ Link: https://lore.kernel.org/r/20220622171835.7558-3-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 42 ++---------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 49 ++++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 16 +++++++ 3 files changed, 67 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c index b41993269d09..f1d237057ed9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -27,11 +28,6 @@ #define LM_MISR_CTRL 0x310 #define LM_MISR_SIGNATURE 0x314 -#define LM_MISR_FRAME_COUNT_MASK 0xFF -#define LM_MISR_CTRL_ENABLE BIT(8) -#define LM_MISR_CTRL_STATUS BIT(9) -#define LM_MISR_CTRL_STATUS_CLEAR BIT(10) -#define LM_MISR_CTRL_FREE_RUN_MASK BIT(31) static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer, @@ -107,44 +103,12 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count) { - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 config = 0; - - DPU_REG_WRITE(c, LM_MISR_CTRL, LM_MISR_CTRL_STATUS_CLEAR); - - /* Clear old MISR value (in case it's read before a new value is calculated)*/ - wmb(); - - if (enable) { - config = (frame_count & LM_MISR_FRAME_COUNT_MASK) | - LM_MISR_CTRL_ENABLE | LM_MISR_CTRL_FREE_RUN_MASK; - - DPU_REG_WRITE(c, LM_MISR_CTRL, config); - } else { - DPU_REG_WRITE(c, LM_MISR_CTRL, 0); - } - + dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count); } static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value) { - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 ctrl = 0; - - if (!misr_value) - return -EINVAL; - - ctrl = DPU_REG_READ(c, LM_MISR_CTRL); - - if (!(ctrl & LM_MISR_CTRL_ENABLE)) - return -ENODATA; - - if (!(ctrl & LM_MISR_CTRL_STATUS)) - return -EINVAL; - - *misr_value = DPU_REG_READ(c, LM_MISR_SIGNATURE); - - return 0; + return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value); } static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index 512316f25a51..a679757159e9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ @@ -447,3 +449,48 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, return 0; } + +void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + bool enable, u32 frame_count) +{ + u32 config = 0; + + DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR); + + /* Clear old MISR value (in case it's read before a new value is calculated)*/ + wmb(); + + if (enable) { + config = (frame_count & MISR_FRAME_COUNT_MASK) | + MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK; + + DPU_REG_WRITE(c, misr_ctrl_offset, config); + } else { + DPU_REG_WRITE(c, misr_ctrl_offset, 0); + } + +} + +int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + u32 misr_signature_offset, + u32 *misr_value) +{ + u32 ctrl = 0; + + if (!misr_value) + return -EINVAL; + + ctrl = DPU_REG_READ(c, misr_ctrl_offset); + + if (!(ctrl & MISR_CTRL_ENABLE)) + return -ENODATA; + + if (!(ctrl & MISR_CTRL_STATUS)) + return -EINVAL; + + *misr_value = DPU_REG_READ(c, misr_signature_offset); + + return 0; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 550b2e2b3e34..ca74474d546b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ @@ -12,6 +13,11 @@ #include "dpu_hw_catalog.h" #define REG_MASK(n) ((BIT(n)) - 1) +#define MISR_FRAME_COUNT_MASK 0xFF +#define MISR_CTRL_ENABLE BIT(8) +#define MISR_CTRL_STATUS BIT(9) +#define MISR_CTRL_STATUS_CLEAR BIT(10) +#define MISR_CTRL_FREE_RUN_MASK BIT(31) /* * This is the common struct maintained by each sub block @@ -341,4 +347,14 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, u32 total_fl); +void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + bool enable, + u32 frame_count); + +int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, + u32 misr_ctrl_offset, + u32 misr_signature_offset, + u32 *misr_value); + #endif /* _DPU_HW_UTIL_H */ From fc18ea9818cdf2767f007d108d07a5b47083d67f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 08:55:28 +0300 Subject: [PATCH 18/46] drm/msm/dp: inline dp_power_clk_set_rate() Inline the dp_power_clk_set_rate() function, replacing it with the call to msm_dss_enable_clk(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/474719/ Link: https://lore.kernel.org/r/20220217055529.499829-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_power.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index ffb84edb0f98..9dadcb6793dd 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -151,21 +151,6 @@ static int dp_power_clk_deinit(struct dp_power_private *power) return 0; } -static int dp_power_clk_set_rate(struct dp_power_private *power, - enum dp_pm_type module, bool enable) -{ - int rc = 0; - struct dss_module_power *mp = &power->parser->mp[module]; - - rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); - if (rc) { - DRM_ERROR("failed to %d clks, err: %d\n", enable, rc); - return rc; - } - - return 0; -} - int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type) { struct dp_power_private *power; @@ -193,6 +178,7 @@ int dp_power_clk_enable(struct dp_power *dp_power, { int rc = 0; struct dp_power_private *power; + struct dss_module_power *mp; power = container_of(dp_power, struct dp_power_private, dp_power); @@ -225,8 +211,9 @@ int dp_power_clk_enable(struct dp_power *dp_power, if ((pm_type == DP_CTRL_PM) && (!dp_power->core_clks_on)) { drm_dbg_dp(power->drm_dev, "Enable core clks before link clks\n"); + mp = &power->parser->mp[DP_CORE_PM]; - rc = dp_power_clk_set_rate(power, DP_CORE_PM, enable); + rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); if (rc) { DRM_ERROR("fail to enable clks: %s. err=%d\n", dp_parser_pm_name(DP_CORE_PM), rc); @@ -236,7 +223,8 @@ int dp_power_clk_enable(struct dp_power *dp_power, } } - rc = dp_power_clk_set_rate(power, pm_type, enable); + mp = &power->parser->mp[pm_type]; + rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); if (rc) { DRM_ERROR("failed to '%s' clks for: %s. err=%d\n", enable ? "enable" : "disable", From 91143873a05db2ae606128c9e246745a721c60b9 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Wed, 22 Jun 2022 10:18:34 -0700 Subject: [PATCH 19/46] drm/msm/dpu: Add MISR register support for interface Add support for setting MISR registers within the interface Changes since V1: - Replaced dpu_hw_intf collect_misr and setup_misr implementations with calls to dpu_hw_utils helper methods Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/490730/ Link: https://lore.kernel.org/r/20220622171835.7558-4-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 19 ++++++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 8 +++++++- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index b2ca8d19fdd7..90613f797ff5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #include "dpu_hwio.h" @@ -67,6 +69,9 @@ #define INTF_CFG2_DATABUS_WIDEN BIT(0) #define INTF_CFG2_DATA_HCTL_EN BIT(4) +#define INTF_MISR_CTRL 0x180 +#define INTF_MISR_SIGNATURE 0x184 + static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, const struct dpu_mdss_cfg *m, void __iomem *addr, @@ -318,6 +323,16 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) return DPU_REG_READ(c, INTF_LINE_COUNT); } +static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count) +{ + dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count); +} + +static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value) +{ + return dpu_hw_collect_misr(&intf->hw, INTF_MISR_CTRL, INTF_MISR_SIGNATURE, misr_value); +} + static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, unsigned long cap) { @@ -328,6 +343,8 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->get_line_count = dpu_hw_intf_get_line_count; if (cap & BIT(DPU_INTF_INPUT_CTRL)) ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; + ops->setup_misr = dpu_hw_intf_setup_misr; + ops->collect_misr = dpu_hw_intf_collect_misr; } struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 7b2d96ac61e8..8d0e7b509260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ #ifndef _DPU_HW_INTF_H @@ -57,6 +59,8 @@ struct intf_status { * @ get_line_count: reads current vertical line counter * @bind_pingpong_blk: enable/disable the connection with pingpong which will * feed pixels to this interface + * @setup_misr: enable/disable MISR + * @collect_misr: read MISR signature */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, @@ -77,6 +81,8 @@ struct dpu_hw_intf_ops { void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, bool enable, const enum dpu_pingpong pp); + void (*setup_misr)(struct dpu_hw_intf *intf, bool enable, u32 frame_count); + int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); }; struct dpu_hw_intf { From 50b1131e067496b1cdd6e52d48f1aea94eccecaf Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Feb 2022 08:55:29 +0300 Subject: [PATCH 20/46] drm/msm/dp: rewrite dss_module_power to use bulk clock functions In order to simplify DP code, drop hand-coded loops over clock arrays, replacing them with clk_bulk_* functions. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/474717/ Link: https://lore.kernel.org/r/20220217055529.499829-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/dp/dp_clk_util.c | 87 ---------------------------- drivers/gpu/drm/msm/dp/dp_clk_util.h | 29 ---------- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 +- drivers/gpu/drm/msm/dp/dp_parser.c | 36 +++++------- drivers/gpu/drm/msm/dp/dp_parser.h | 6 +- drivers/gpu/drm/msm/dp/dp_power.c | 45 ++++---------- 7 files changed, 34 insertions(+), 174 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.c delete mode 100644 drivers/gpu/drm/msm/dp/dp_clk_util.h diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 66395ee0862a..7274c41228ed 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -119,7 +119,6 @@ msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ dp/dp_catalog.o \ - dp/dp_clk_util.o \ dp/dp_ctrl.o \ dp/dp_display.o \ dp/dp_drm.o \ diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.c b/drivers/gpu/drm/msm/dp/dp_clk_util.c deleted file mode 100644 index 85abed31c68b..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_clk_util.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2015, 2017-2018, The Linux Foundation. - * All rights reserved. - */ - -#include -#include -#include -#include -#include - -#include - -#include "dp_clk_util.h" - -void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk) -{ - int i; - - for (i = num_clk - 1; i >= 0; i--) { - if (clk_arry[i].clk) - clk_put(clk_arry[i].clk); - clk_arry[i].clk = NULL; - } -} - -int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk) -{ - int i, rc = 0; - - for (i = 0; i < num_clk; i++) { - clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); - rc = PTR_ERR_OR_ZERO(clk_arry[i].clk); - if (rc) { - DEV_ERR("%pS->%s: '%s' get failed. rc=%d\n", - __builtin_return_address(0), __func__, - clk_arry[i].clk_name, rc); - goto error; - } - } - - return rc; - -error: - for (i--; i >= 0; i--) { - if (clk_arry[i].clk) - clk_put(clk_arry[i].clk); - clk_arry[i].clk = NULL; - } - - return rc; -} - -int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable) -{ - int i, rc = 0; - - if (enable) { - for (i = 0; i < num_clk; i++) { - DEV_DBG("%pS->%s: enable '%s'\n", - __builtin_return_address(0), __func__, - clk_arry[i].clk_name); - rc = clk_prepare_enable(clk_arry[i].clk); - if (rc) - DEV_ERR("%pS->%s: %s en fail. rc=%d\n", - __builtin_return_address(0), - __func__, - clk_arry[i].clk_name, rc); - - if (rc && i) { - msm_dss_enable_clk(&clk_arry[i - 1], - i - 1, false); - break; - } - } - } else { - for (i = num_clk - 1; i >= 0; i--) { - DEV_DBG("%pS->%s: disable '%s'\n", - __builtin_return_address(0), __func__, - clk_arry[i].clk_name); - - clk_disable_unprepare(clk_arry[i].clk); - } - } - - return rc; -} diff --git a/drivers/gpu/drm/msm/dp/dp_clk_util.h b/drivers/gpu/drm/msm/dp/dp_clk_util.h deleted file mode 100644 index c3d59b5017a9..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_clk_util.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2012, 2017-2018, The Linux Foundation. All rights reserved. - */ - -#ifndef __DP_CLK_UTIL_H__ -#define __DP_CLK_UTIL_H__ - -#include -#include - -#define DEV_DBG(fmt, args...) pr_debug(fmt, ##args) -#define DEV_INFO(fmt, args...) pr_info(fmt, ##args) -#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args) -#define DEV_ERR(fmt, args...) pr_err(fmt, ##args) - -struct dss_clk { - struct clk *clk; /* clk handle */ - char clk_name[32]; -}; - -struct dss_module_power { - unsigned int num_clk; - struct dss_clk *clk_config; -}; - -int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk); -void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk); -int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable); -#endif /* __DP_CLK_UTIL_H__ */ diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 748339617ad4..ab6aa13b1639 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1321,9 +1321,9 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, enum dp_pm_type module, char *name, unsigned long rate) { u32 num = ctrl->parser->mp[module].num_clk; - struct dss_clk *cfg = ctrl->parser->mp[module].clk_config; + struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks; - while (num && strcmp(cfg->clk_name, name)) { + while (num && strcmp(cfg->id, name)) { num--; cfg++; } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index fc3d88c05f94..29107f108a78 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -162,11 +162,11 @@ static int dp_parser_init_clk_data(struct dp_parser *parser) } core_power->num_clk = core_clk_count; - core_power->clk_config = devm_kzalloc(dev, - sizeof(struct dss_clk) * core_power->num_clk, + core_power->clocks = devm_kcalloc(dev, + core_power->num_clk, sizeof(struct clk_bulk_data), GFP_KERNEL); - if (!core_power->clk_config) - return -EINVAL; + if (!core_power->clocks) + return -ENOMEM; /* Initialize the CTRL power module */ if (ctrl_clk_count == 0) { @@ -175,12 +175,12 @@ static int dp_parser_init_clk_data(struct dp_parser *parser) } ctrl_power->num_clk = ctrl_clk_count; - ctrl_power->clk_config = devm_kzalloc(dev, - sizeof(struct dss_clk) * ctrl_power->num_clk, + ctrl_power->clocks = devm_kcalloc(dev, + ctrl_power->num_clk, sizeof(struct clk_bulk_data), GFP_KERNEL); - if (!ctrl_power->clk_config) { + if (!ctrl_power->clocks) { ctrl_power->num_clk = 0; - return -EINVAL; + return -ENOMEM; } /* Initialize the STREAM power module */ @@ -190,12 +190,12 @@ static int dp_parser_init_clk_data(struct dp_parser *parser) } stream_power->num_clk = stream_clk_count; - stream_power->clk_config = devm_kzalloc(dev, - sizeof(struct dss_clk) * stream_power->num_clk, + stream_power->clocks = devm_kcalloc(dev, + stream_power->num_clk, sizeof(struct clk_bulk_data), GFP_KERNEL); - if (!stream_power->clk_config) { + if (!stream_power->clocks) { stream_power->num_clk = 0; - return -EINVAL; + return -ENOMEM; } return 0; @@ -234,21 +234,15 @@ static int dp_parser_clock(struct dp_parser *parser) } if (dp_parser_check_prefix("core", clk_name) && core_clk_index < core_clk_count) { - struct dss_clk *clk = - &core_power->clk_config[core_clk_index]; - strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); + core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); core_clk_index++; } else if (dp_parser_check_prefix("stream", clk_name) && stream_clk_index < stream_clk_count) { - struct dss_clk *clk = - &stream_power->clk_config[stream_clk_index]; - strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); + stream_power->clocks[stream_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); stream_clk_index++; } else if (dp_parser_check_prefix("ctrl", clk_name) && ctrl_clk_index < ctrl_clk_count) { - struct dss_clk *clk = - &ctrl_power->clk_config[ctrl_clk_index]; - strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name)); + ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); ctrl_clk_index++; } } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 3a4d7972c069..9abddc6d50c0 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -10,7 +10,6 @@ #include #include -#include "dp_clk_util.h" #include "msm_drv.h" #define DP_LABEL "MDSS DP DISPLAY" @@ -106,6 +105,11 @@ struct dp_regulator_cfg { struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX]; }; +struct dss_module_power { + unsigned int num_clk; + struct clk_bulk_data *clocks; +}; + /** * struct dp_parser - DP parser's data exposed to clients * diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index 9dadcb6793dd..b415b35c2b8c 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -106,51 +106,30 @@ static int dp_power_clk_init(struct dp_power_private *power) ctrl = &power->parser->mp[DP_CTRL_PM]; stream = &power->parser->mp[DP_STREAM_PM]; - rc = msm_dss_get_clk(dev, core->clk_config, core->num_clk); + rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks); if (rc) { DRM_ERROR("failed to get %s clk. err=%d\n", dp_parser_pm_name(DP_CORE_PM), rc); return rc; } - rc = msm_dss_get_clk(dev, ctrl->clk_config, ctrl->num_clk); + rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks); if (rc) { DRM_ERROR("failed to get %s clk. err=%d\n", dp_parser_pm_name(DP_CTRL_PM), rc); - msm_dss_put_clk(core->clk_config, core->num_clk); return -ENODEV; } - rc = msm_dss_get_clk(dev, stream->clk_config, stream->num_clk); + rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks); if (rc) { DRM_ERROR("failed to get %s clk. err=%d\n", dp_parser_pm_name(DP_CTRL_PM), rc); - msm_dss_put_clk(core->clk_config, core->num_clk); return -ENODEV; } return 0; } -static int dp_power_clk_deinit(struct dp_power_private *power) -{ - struct dss_module_power *core, *ctrl, *stream; - - core = &power->parser->mp[DP_CORE_PM]; - ctrl = &power->parser->mp[DP_CTRL_PM]; - stream = &power->parser->mp[DP_STREAM_PM]; - - if (!core || !ctrl || !stream) { - DRM_ERROR("invalid power_data\n"); - return -EINVAL; - } - - msm_dss_put_clk(ctrl->clk_config, ctrl->num_clk); - msm_dss_put_clk(core->clk_config, core->num_clk); - msm_dss_put_clk(stream->clk_config, stream->num_clk); - return 0; -} - int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type) { struct dp_power_private *power; @@ -213,7 +192,7 @@ int dp_power_clk_enable(struct dp_power *dp_power, "Enable core clks before link clks\n"); mp = &power->parser->mp[DP_CORE_PM]; - rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); + rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); if (rc) { DRM_ERROR("fail to enable clks: %s. err=%d\n", dp_parser_pm_name(DP_CORE_PM), rc); @@ -224,12 +203,14 @@ int dp_power_clk_enable(struct dp_power *dp_power, } mp = &power->parser->mp[pm_type]; - rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); - if (rc) { - DRM_ERROR("failed to '%s' clks for: %s. err=%d\n", - enable ? "enable" : "disable", - dp_parser_pm_name(pm_type), rc); - return rc; + if (enable) { + rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); + if (rc) { + DRM_ERROR("failed to enable clks, err: %d\n", rc); + return rc; + } + } else { + clk_bulk_disable_unprepare(mp->num_clk, mp->clocks); } if (pm_type == DP_CORE_PM) @@ -294,9 +275,7 @@ void dp_power_client_deinit(struct dp_power *dp_power) power = container_of(dp_power, struct dp_power_private, dp_power); - dp_power_clk_deinit(power); pm_runtime_disable(&power->pdev->dev); - } int dp_power_init(struct dp_power *dp_power, bool flip) From b16650478635f06600bd6bc3cc04f09a5c3888af Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Wed, 22 Jun 2022 10:18:35 -0700 Subject: [PATCH 21/46] drm/msm/dpu: Add interface support for CRC debugfs Add support for writing CRC values for the interface block to the debugfs by calling the necessary MISR setup/collect methods. Changes since V1: - Set values_cnt to only include phys with backing hw_intf - Loop over all drm_encs connected to crtc Changes since V2: - Remove vblank.h inclusion - Change `pos + i` to `pos + entries` - Initialize values_cnt to 0 for encoder - Change DPU_CRTC_CRC_SOURCE_INTF to DPU_CRTC_CRC_SOURCE_ENCODER (and "intf" to "enc") - Change dpu_encoder_get_num_phys to dpu_encoder_get_num_hw_intfs - Add checks for setup_misr and collect_misr in dpu_encoder_get_num_hw_intfs Changes since V3: - Remove extra whitespace - Change "enc" to "encoder" - Move crcs array to dpu_crtc_get_encoder_crc - Rename dpu_encoder_get_num_hw_intfs to dpu_encoder_get_crc_values_cnt Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/490736/ Link: https://lore.kernel.org/r/20220622171835.7558-5-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 46 ++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 64 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 22 +++++++ 4 files changed, 134 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b57140c3671a..4dd0ce09ca74 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -79,6 +79,8 @@ static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name) if (!strcmp(src_name, "auto") || !strcmp(src_name, "lm")) return DPU_CRTC_CRC_SOURCE_LAYER_MIXER; + if (!strcmp(src_name, "encoder")) + return DPU_CRTC_CRC_SOURCE_ENCODER; return DPU_CRTC_CRC_SOURCE_INVALID; } @@ -94,8 +96,16 @@ static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, return -EINVAL; } - if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) + if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) { *values_cnt = crtc_state->num_mixers; + } else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) { + struct drm_encoder *drm_enc; + + *values_cnt = 0; + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) + *values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc); + } return 0; } @@ -116,6 +126,14 @@ static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) } } +static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc) +{ + struct drm_encoder *drm_enc; + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) + dpu_encoder_setup_misr(drm_enc); +} + static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) { enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); @@ -164,6 +182,8 @@ static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) dpu_crtc_setup_lm_misr(crtc_state); + else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) + dpu_crtc_setup_encoder_misr(crtc); else ret = -EINVAL; @@ -215,6 +235,28 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, drm_crtc_accurate_vblank_count(crtc), crcs); } +static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc) +{ + struct drm_encoder *drm_enc; + int rc, pos = 0; + u32 crcs[INTF_MAX]; + + drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) { + rc = dpu_encoder_get_crc(drm_enc, crcs, pos); + if (rc < 0) { + if (rc != -ENODATA) + DRM_DEBUG_DRIVER("MISR read failed\n"); + + return rc; + } + + pos += rc; + } + + return drm_crtc_add_crc_entry(crtc, true, + drm_crtc_accurate_vblank_count(crtc), crcs); +} + static int dpu_crtc_get_crc(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); @@ -227,6 +269,8 @@ static int dpu_crtc_get_crc(struct drm_crtc *crtc) if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) return dpu_crtc_get_lm_crc(crtc, crtc_state); + else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER) + return dpu_crtc_get_encoder_crc(crtc); return -EINVAL; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 20df23fe74ed..af03277a3e5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -73,11 +74,13 @@ struct dpu_crtc_smmu_state_data { * enum dpu_crtc_crc_source: CRC source * @DPU_CRTC_CRC_SOURCE_NONE: no source set * @DPU_CRTC_CRC_SOURCE_LAYER_MIXER: CRC in layer mixer + * @DPU_CRTC_CRC_SOURCE_ENCODER: CRC in encoder * @DPU_CRTC_CRC_SOURCE_INVALID: Invalid source */ enum dpu_crtc_crc_source { DPU_CRTC_CRC_SOURCE_NONE = 0, DPU_CRTC_CRC_SOURCE_LAYER_MIXER, + DPU_CRTC_CRC_SOURCE_ENCODER, DPU_CRTC_CRC_SOURCE_MAX, DPU_CRTC_CRC_SOURCE_INVALID = -1 }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d61874b069c3..f435baa500f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -225,6 +225,70 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) return dpu_enc->wide_bus_en; } +int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + int i, num_intf = 0; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + + if (phys->hw_intf && phys->hw_intf->ops.setup_misr + && phys->hw_intf->ops.collect_misr) + num_intf++; + } + + return num_intf; +} + +void dpu_encoder_setup_misr(const struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + + int i; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + + if (!phys->hw_intf || !phys->hw_intf->ops.setup_misr) + continue; + + phys->hw_intf->ops.setup_misr(phys->hw_intf, true, 1); + } +} + +int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos) +{ + struct dpu_encoder_virt *dpu_enc; + + int i, rc = 0, entries_added = 0; + + if (!drm_enc->crtc) { + DRM_ERROR("no crtc found for encoder %d\n", drm_enc->index); + return -EINVAL; + } + + dpu_enc = to_dpu_encoder_virt(drm_enc); + + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + + if (!phys->hw_intf || !phys->hw_intf->ops.collect_misr) + continue; + + rc = phys->hw_intf->ops.collect_misr(phys->hw_intf, &crcs[pos + entries_added]); + if (rc) + return rc; + entries_added++; + } + + return entries_added; +} + static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc) { struct dpu_hw_dither_cfg dither_cfg = { 0 }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 861870ac8ae7..d4d1ecd416e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark @@ -174,6 +175,27 @@ int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc); bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc); +/** + * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained + * in virtual encoder that can collect CRC values + * @drm_enc: Pointer to previously created drm encoder structure + * Returns: Number of physical encoders for given drm encoder + */ +int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc); + +/** + * dpu_encoder_setup_misr - enable misr calculations + * @drm_enc: Pointer to previously created drm encoder structure + */ +void dpu_encoder_setup_misr(const struct drm_encoder *drm_encoder); + +/** + * dpu_encoder_get_crc - get the crc value from interface blocks + * @drm_enc: Pointer to previously created drm encoder structure + * Returns: 0 on success, error otherwise + */ +int dpu_encoder_get_crc(const struct drm_encoder *drm_enc, u32 *crcs, int pos); + /** * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology. * @drm_enc: Pointer to previously created drm encoder structure From ce557eaf52ab03c376bb1a29b17e9abd04f9be26 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 25 Apr 2022 14:06:42 -0700 Subject: [PATCH 22/46] dt-bindings: msm/dp: List supplies in the bindings We're supposed to list the supplies in the dt bindings but there are none in the DP controller bindings. Looking at the Linux driver and existing device trees, we can see that two supplies are expected: - vdda-0p9-supply - vdda-1p2-supply Let's list them both in the bindings. Note that the datasheet for sc7280 doesn't describe these supplies very verbosely. For the 0p9 supply, for instance, it says "Power for eDP 0.9 V circuits". This this is obvious from the property name, we don't bother cluttering the bindings with a description. Signed-off-by: Douglas Anderson Reviewed-by: Sankeerth Billakanti Patchwork: https://patchwork.freedesktop.org/patch/483373/ Link: https://lore.kernel.org/r/20220425140619.1.Ibfde5a26a7182c4b478d570c23d2649823ac2cce@changeid Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dp-controller.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index cd05cfd76536..dba31108db51 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -76,6 +76,9 @@ properties: "#sound-dai-cells": const: 0 + vdda-0p9-supply: true + vdda-1p2-supply: true + ports: $ref: /schemas/graph.yaml#/properties/ports properties: @@ -137,6 +140,9 @@ examples: power-domains = <&rpmhpd SC7180_CX>; + vdda-0p9-supply = <&vdda_usb_ss_dp_core>; + vdda-1p2-supply = <&vdda_usb_ss_dp_1p2>; + ports { #address-cells = <1>; #size-cells = <0>; From 2709935b4a9e5b2b97288b391da9fe5aab24c280 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 25 Jun 2022 03:30:28 +0300 Subject: [PATCH 23/46] drm/msm/dpu: simplify and unify dpu_encoder_get_intf and dpu_encoder_get_wb Remove extra nestting level from the dpu_encoder_get_intf(), replacing it with the explicit return in case the INTF_WB was passed to the function. While we are at it, also change dpu_encoder_get_wb() to also use explicit return rather than the goto. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/491189/ Link: https://lore.kernel.org/r/20220625003028.383259-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f435baa500f8..c682d4e02d1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1255,12 +1255,13 @@ static enum dpu_intf dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog, { int i = 0; - if (type != INTF_WB) { - for (i = 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type == type - && catalog->intf[i].controller_id == controller_id) { - return catalog->intf[i].id; - } + if (type == INTF_WB) + return INTF_MAX; + + for (i = 0; i < catalog->intf_count; i++) { + if (catalog->intf[i].type == type + && catalog->intf[i].controller_id == controller_id) { + return catalog->intf[i].id; } } @@ -1273,14 +1274,13 @@ static enum dpu_wb dpu_encoder_get_wb(const struct dpu_mdss_cfg *catalog, int i = 0; if (type != INTF_WB) - goto end; + return WB_MAX; for (i = 0; i < catalog->wb_count; i++) { if (catalog->wb[i].id == controller_id) return catalog->wb[i].id; } -end: return WB_MAX; } From 01161a5c0ea6d21da8f59001ffeb95aed4e35526 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Fri, 3 Jun 2022 13:09:39 -0700 Subject: [PATCH 24/46] dt-bindings: msm: update maintainers list with proper id Use quic id instead of codeaurora id in maintainers list for display devicetree bindings. Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488296/ Link: https://lore.kernel.org/r/1654286979-11072-1-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dp-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index dba31108db51..94bc6e1b6451 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: MSM Display Port Controller maintainers: - - Kuogee Hsieh + - Kuogee Hsieh description: | Device tree bindings for DisplayPort host controller for MSM targets From 3bcecf2b6d06f71ce3392cc5f5a2d8cd52bd72a1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 15 Jun 2022 14:59:20 +0300 Subject: [PATCH 25/46] drm/msm/dp: make dp_bridge_mode_valid() more precise Make dp_connector_mode_valid() return precise MODE_CLOCK_HIGH rather than generic MODE_BAD in case the mode clock is higher than DP_MAX_PIXEL_CLK_KHZ (675 MHz). Reviewed-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489554/ Link: https://lore.kernel.org/r/20220615115920.6768-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 239c8e3f2fbd..c234295ce94b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -992,7 +992,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, return MODE_OK; if (mode->clock > DP_MAX_PIXEL_CLK_KHZ) - return MODE_BAD; + return MODE_CLOCK_HIGH; dp_display = container_of(dp, struct dp_display_private, dp_display); link_info = &dp_display->panel->link_info; From efc7617086bf3ce5a782fcc926947d73788316c5 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 24 Jun 2022 17:28:11 -0700 Subject: [PATCH 26/46] drm/msm/dp: Remove encoder pointer from struct msm_dp We don't need to stash the encoder here. Instead we can simply pass it around as an argument. Cc: Kuogee Hsieh Signed-off-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/491187/ Link: https://lore.kernel.org/r/20220625002811.3225344-1-swboyd@chromium.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 4 +--- drivers/gpu/drm/msm/dp/dp_display.h | 1 - drivers/gpu/drm/msm/dp/dp_drm.c | 8 ++++---- drivers/gpu/drm/msm/dp/dp_drm.h | 2 +- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c234295ce94b..859353fec26d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1624,8 +1624,6 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, return ret; } - dp_display->encoder = encoder; - ret = dp_display_get_next_bridge(dp_display); if (ret) return ret; @@ -1641,7 +1639,7 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, priv->bridges[priv->num_bridges++] = dp_display->bridge; - dp_display->connector = dp_drm_connector_init(dp_display); + dp_display->connector = dp_drm_connector_init(dp_display, encoder); if (IS_ERR(dp_display->connector)) { ret = PTR_ERR(dp_display->connector); DRM_DEV_ERROR(dev->dev, diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 4f9fe4d7610b..dcedf021f7fe 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -15,7 +15,6 @@ struct msm_dp { struct device *codec_dev; struct drm_bridge *bridge; struct drm_connector *connector; - struct drm_encoder *encoder; struct drm_bridge *next_bridge; bool is_connected; bool audio_enabled; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 62d58b9c4647..6df25f7662e7 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -116,7 +116,7 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device * } if (dp_display->next_bridge) { - rc = drm_bridge_attach(dp_display->encoder, + rc = drm_bridge_attach(encoder, dp_display->next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (rc < 0) { @@ -130,15 +130,15 @@ struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device * } /* connector initialization */ -struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display) +struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder) { struct drm_connector *connector = NULL; - connector = drm_bridge_connector_init(dp_display->drm_dev, dp_display->encoder); + connector = drm_bridge_connector_init(dp_display->drm_dev, encoder); if (IS_ERR(connector)) return connector; - drm_connector_attach_encoder(connector, dp_display->encoder); + drm_connector_attach_encoder(connector, encoder); return connector; } diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index f4b1ed1e24f7..82035dbb0578 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -19,7 +19,7 @@ struct msm_dp_bridge { #define to_dp_bridge(x) container_of((x), struct msm_dp_bridge, bridge) -struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display); +struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder); struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder); From a18a44e9262d5c7f7fbccbc9458df64d69185d41 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 14:31:48 +0300 Subject: [PATCH 27/46] drm/msm/hdmi: fill the pwr_regs bulk regulators Conversion to use bulk regulator API omitted filling the pwr_regs with proper regulator IDs. This was left unnoticed, since none of my testing platforms has used the pwr_regs. Fix this by propagating regulator ids properly. Fixes: 31b3b1f5e352 ("drm/msm/hdmi: use bulk regulator API") Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/488847/ Link: https://lore.kernel.org/r/20220609113148.3149194-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index cf24e68864ba..73070ec1a936 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -180,6 +180,9 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) goto fail; } + for (i = 0; i < config->pwr_reg_cnt; i++) + hdmi->pwr_regs[i].supply = config->pwr_reg_names[i]; + ret = devm_regulator_bulk_get(&pdev->dev, config->pwr_reg_cnt, hdmi->pwr_regs); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to get pwr regulator: %d\n", ret); From 4f0718bfa47266de90f9e5eec8545ba20939c872 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sat, 11 Jun 2022 00:02:57 +0200 Subject: [PATCH 28/46] drm/msm/dsi: Use single function for reset There is currently two function for performing reset: dsi_sw_reset and dsi_sw_reset_restore. Only difference between those is that latter one assumes that DSI controller is enabled. In contrary former one assumes that controller is disabled and executed during power-on. However this assumtion is not true mobile devices which have boot splash set up by boot-loader. This patch removes dsi_sw_reset_restore and makes dsi_sw_reset disable DSI controller during reset sequence if it's enabled. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489152/ Link: https://lore.kernel.org/r/20220610220259.220622-1-luca@z3ntu.xyz [DB: fixed the typo in the commit message] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 48 +++++++++++++----------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index a95d5df52653..bab2634ebd11 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1080,12 +1080,32 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) static void dsi_sw_reset(struct msm_dsi_host *msm_host) { + u32 ctrl; + + ctrl = dsi_read(msm_host, REG_DSI_CTRL); + + if (ctrl & DSI_CTRL_ENABLE) { + dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); + /* + * dsi controller need to be disabled before + * clocks turned on + */ + wmb(); + } + dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); wmb(); /* clocks need to be enabled before reset */ + /* dsi controller can only be reset while clocks are running */ dsi_write(msm_host, REG_DSI_RESET, 1); msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ dsi_write(msm_host, REG_DSI_RESET, 0); + wmb(); /* controller out of reset */ + + if (ctrl & DSI_CTRL_ENABLE) { + dsi_write(msm_host, REG_DSI_CTRL, ctrl); + wmb(); /* make sure dsi controller enabled again */ + } } static void dsi_op_mode_config(struct msm_dsi_host *msm_host, @@ -1478,32 +1498,6 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, return len; } -static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) -{ - u32 data0, data1; - - data0 = dsi_read(msm_host, REG_DSI_CTRL); - data1 = data0; - data1 &= ~DSI_CTRL_ENABLE; - dsi_write(msm_host, REG_DSI_CTRL, data1); - /* - * dsi controller need to be disabled before - * clocks turned on - */ - wmb(); - - dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); - wmb(); /* make sure clocks enabled */ - - /* dsi controller can only be reset while clocks are running */ - dsi_write(msm_host, REG_DSI_RESET, 1); - msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ - dsi_write(msm_host, REG_DSI_RESET, 0); - wmb(); /* controller out of reset */ - dsi_write(msm_host, REG_DSI_CTRL, data0); - wmb(); /* make sure dsi controller enabled again */ -} - static void dsi_hpd_worker(struct work_struct *work) { struct msm_dsi_host *msm_host = @@ -1520,7 +1514,7 @@ static void dsi_err_worker(struct work_struct *work) pr_err_ratelimited("%s: status=%x\n", __func__, status); if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) - dsi_sw_reset_restore(msm_host); + dsi_sw_reset(msm_host); /* It is safe to clear here because error irq is disabled. */ msm_host->err_work_state = 0; From 94a9e05228c8624fbb08f4d8b2775dd0dc588f76 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 27 Jun 2022 19:54:13 +0300 Subject: [PATCH 29/46] drm/msm/dp: use ARRAY_SIZE for calculating num_descs If for some reason the msm_dp_config::descs array starts from non-zero index or contains the hole, setting the msm_dp_config::num_descs might be not that obvious and error-prone. Use ARRAY_SIZE to set this field rather than encoding the value manually. Reported-by: Kuogee Hsieh Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Reviewed-by: Kuogee Hsieh Patchwork: https://patchwork.freedesktop.org/patch/491399/ Link: https://lore.kernel.org/r/20220627165413.657142-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 46 +++++++++++++++++------------ 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 859353fec26d..b36f8b69a244 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -131,35 +131,43 @@ struct msm_dp_config { size_t num_descs; }; +static const struct msm_dp_desc sc7180_dp_descs[] = { + [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, +}; + static const struct msm_dp_config sc7180_dp_cfg = { - .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - }, - .num_descs = 1, + .descs = sc7180_dp_descs, + .num_descs = ARRAY_SIZE(sc7180_dp_descs), +}; + +static const struct msm_dp_desc sc7280_dp_descs[] = { + [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, + [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, }; static const struct msm_dp_config sc7280_dp_cfg = { - .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea0000, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, - }, - .num_descs = 2, + .descs = sc7280_dp_descs, + .num_descs = ARRAY_SIZE(sc7280_dp_descs), +}; + +static const struct msm_dp_desc sc8180x_dp_descs[] = { + [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, + [MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, + [MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP }, }; static const struct msm_dp_config sc8180x_dp_cfg = { - .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - [MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - [MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type = DRM_MODE_CONNECTOR_eDP }, - }, - .num_descs = 3, + .descs = sc8180x_dp_descs, + .num_descs = ARRAY_SIZE(sc8180x_dp_descs), +}; + +static const struct msm_dp_desc sm8350_dp_descs[] = { + [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, }; static const struct msm_dp_config sm8350_dp_cfg = { - .descs = (const struct msm_dp_desc[]) { - [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae90000, .connector_type = DRM_MODE_CONNECTOR_DisplayPort }, - }, - .num_descs = 1, + .descs = sm8350_dp_descs, + .num_descs = ARRAY_SIZE(sm8350_dp_descs), }; static const struct of_device_id dp_dt_match[] = { From 2f14bc38d88a47e79fc2d8bf5d4ced752db7e1fb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:37 +0300 Subject: [PATCH 30/46] dt-bindings: display/msm: hdmi: split and convert to yaml Convert Qualcomm HDMI binding into HDMI TX and PHY yaml bindings. Changes to schema: HDMI: - fixed reg-names numbering to match 0..3 instead 0,1,3,4 - dropped qcom,tx-ddc-* from example, they were not documented - make phy-names deprecated, drop it from the examples PHY: - moved into phy/ directory - split into QMP and non-QMP PHY schemas Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/488850/ Link: https://lore.kernel.org/r/20220609122350.3157529-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/hdmi.txt | 99 -------- .../devicetree/bindings/display/msm/hdmi.yaml | 228 ++++++++++++++++++ .../bindings/phy/qcom,hdmi-phy-other.yaml | 104 ++++++++ .../bindings/phy/qcom,hdmi-phy-qmp.yaml | 85 +++++++ 4 files changed, 417 insertions(+), 99 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.txt create mode 100644 Documentation/devicetree/bindings/display/msm/hdmi.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml create mode 100644 Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt deleted file mode 100644 index 5f90a40da51b..000000000000 --- a/Documentation/devicetree/bindings/display/msm/hdmi.txt +++ /dev/null @@ -1,99 +0,0 @@ -Qualcomm adreno/snapdragon hdmi output - -Required properties: -- compatible: one of the following - * "qcom,hdmi-tx-8996" - * "qcom,hdmi-tx-8994" - * "qcom,hdmi-tx-8084" - * "qcom,hdmi-tx-8974" - * "qcom,hdmi-tx-8660" - * "qcom,hdmi-tx-8960" -- reg: Physical base address and length of the controller's registers -- reg-names: "core_physical" -- interrupts: The interrupt signal from the hdmi block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See ../clocks/clock-bindings.txt for details. -- core-vdda-supply: phandle to supply regulator -- hdmi-mux-supply: phandle to mux regulator -- phys: the phandle for the HDMI PHY device -- phy-names: the name of the corresponding PHY device - -Optional properties: -- hpd-gpios: hpd pin -- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin -- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin -- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin -- power-domains: reference to the power domain(s), if available. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-1: the "sleep" pinctrl state - -HDMI PHY: -Required properties: -- compatible: Could be the following - * "qcom,hdmi-phy-8660" - * "qcom,hdmi-phy-8960" - * "qcom,hdmi-phy-8974" - * "qcom,hdmi-phy-8084" - * "qcom,hdmi-phy-8996" -- #phy-cells: Number of cells in a PHY specifier; Should be 0. -- reg: Physical base address and length of the registers of the PHY sub blocks. -- reg-names: The names of register regions. The following regions are required: - * "hdmi_phy" - * "hdmi_pll" - For HDMI PHY on msm8996, these additional register regions are required: - * "hdmi_tx_l0" - * "hdmi_tx_l1" - * "hdmi_tx_l3" - * "hdmi_tx_l4" -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- core-vdda-supply: phandle to vdda regulator device node - -Example: - -/ { - ... - - hdmi: hdmi@4a00000 { - compatible = "qcom,hdmi-tx-8960"; - reg-names = "core_physical"; - reg = <0x04a00000 0x2f0>; - interrupts = ; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "core", - "master_iface", - "slave_iface"; - clocks = - <&mmcc HDMI_APP_CLK>, - <&mmcc HDMI_M_AHB_CLK>, - <&mmcc HDMI_S_AHB_CLK>; - qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>; - qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - hdmi-mux-supply = <&ext_3p3v>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hpd_active &ddc_active &cec_active>; - pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; - - phys = <&hdmi_phy>; - phy-names = "hdmi_phy"; - }; - - hdmi_phy: phy@4a00400 { - compatible = "qcom,hdmi-phy-8960"; - reg-names = "hdmi_phy", - "hdmi_pll"; - reg = <0x4a00400 0x60>, - <0x4a00500 0x100>; - #phy-cells = <0>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = "slave_iface"; - clocks = <&mmcc HDMI_S_AHB_CLK>; - core-vdda-supply = <&pm8921_hdmi_mvs>; - }; -}; diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml new file mode 100644 index 000000000000..861678b2bf94 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/display/msm/hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon HDMI output + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8660 + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + minItems: 1 + items: + - const: core_physical + - const: qfprom_physical + - const: hdcp_physical + + interrupts: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + enum: + - hdmi_phy + - hdmi-phy + deprecated: true + + core-vdda-supply: + description: phandle to VDDA supply regulator + + hdmi-mux-supply: + description: phandle to mux regulator + + core-vcc-supply: + description: phandle to VCC supply regulator + + hpd-gpios: + maxItems: 1 + description: hpd pin + + qcom,hdmi-tx-mux-en-gpios: + maxItems: 1 + description: HDMI mux enable pin + + qcom,hdmi-tx-mux-sel-gpios: + maxItems: 1 + description: HDMI mux select pin + + qcom,hdmi-tx-mux-lpm-gpios: + maxItems: 1 + description: HDMI mux lpm pin + + '#sound-dai-cells': + const: 1 + + ports: + type: object + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Input endpoints of the controller. + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: | + Output endpoints of the controller. + + required: + - port@0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - interrupts + - phys + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8960 + - qcom,hdmi-tx-8660 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: core + - const: master_iface + - const: slave_iface + core-vcc-supplies: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-tx-8974 + - qcom,hdmi-tx-8084 + - qcom,hdmi-tx-8994 + - qcom,hdmi-tx-8996 + then: + properties: + clocks: + minItems: 5 + clock-names: + items: + - const: mdp_core + - const: iface + - const: core + - const: alt_iface + - const: extp + hdmi-mux-supplies: false + +additionalProperties: false + +examples: + - | + #include + #include + #include + hdmi: hdmi@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x2f0>; + interrupts = ; + clock-names = "core", + "master_iface", + "slave_iface"; + clocks = <&clk 61>, + <&clk 72>, + <&clk 98>; + hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hpd_active &ddc_active &cec_active>; + pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>; + + phys = <&hdmi_phy>; + }; + - | + #include + #include + #include + #include + #include + hdmi@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; + reg-names = "core_physical", + "qfprom_physical", + "hdcp_physical"; + + interrupt-parent = <&mdss>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_HDMI_CLK>, + <&mmcc MDSS_HDMI_AHB_CLK>, + <&mmcc MDSS_EXTPCLK_CLK>; + clock-names = "mdp_core", + "iface", + "core", + "alt_iface", + "extp"; + + phys = <&hdmi_phy>; + #sound-dai-cells = <1>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&mdp5_intf3_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml new file mode 100644 index 000000000000..fdb277edebeb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-other.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon HDMI phy + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + - qcom,hdmi-phy-8974 + - qcom,hdmi-phy-8084 + + reg: + maxItems: 2 + + reg-names: + items: + - const: hdmi_phy + - const: hdmi_pll + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + power-domains: + maxItems: 1 + + core-vdda-supply: + description: phandle to VDDA supply regulator + + vddio-supply: + description: phandle to VDD I/O supply regulator + + '#phy-cells': + const: 0 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-phy-8660 + - qcom,hdmi-phy-8960 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: slave_iface + vddio-supply: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,hdmi-phy-8084 + - qcom,hdmi-phy-8974 + then: + properties: + clocks: + maxItems: 2 + clock-names: + items: + - const: iface + - const: alt_iface + +required: + - compatible + - clocks + - reg + - reg-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + hdmi_phy: phy@4a00400 { + compatible = "qcom,hdmi-phy-8960"; + reg-names = "hdmi_phy", + "hdmi_pll"; + reg = <0x4a00400 0x60>, + <0x4a00500 0x100>; + #phy-cells = <0>; + power-domains = <&mmcc 1>; + clock-names = "slave_iface"; + clocks = <&clk 21>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml new file mode 100644 index 000000000000..eea2e02678ed --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,hdmi-phy-qmp.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Adreno/Snapdragon QMP HDMI phy + +maintainers: + - Rob Clark + +properties: + compatible: + enum: + - qcom,hdmi-phy-8996 + + reg: + maxItems: 6 + + reg-names: + items: + - const: hdmi_pll + - const: hdmi_tx_l0 + - const: hdmi_tx_l1 + - const: hdmi_tx_l2 + - const: hdmi_tx_l3 + - const: hdmi_phy + + clocks: + maxItems: 2 + + clock-names: + items: + - const: iface + - const: ref + + power-domains: + maxItems: 1 + + vcca-supply: + description: phandle to VCCA supply regulator + + vddio-supply: + description: phandle to VDD I/O supply regulator + + '#phy-cells': + const: 0 + +required: + - compatible + - clocks + - clock-names + - reg + - reg-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + hdmi-phy@9a0600 { + compatible = "qcom,hdmi-phy-8996"; + reg = <0x009a0600 0x1c4>, + <0x009a0a00 0x124>, + <0x009a0c00 0x124>, + <0x009a0e00 0x124>, + <0x009a1000 0x124>, + <0x009a1200 0x0c8>; + reg-names = "hdmi_pll", + "hdmi_tx_l0", + "hdmi_tx_l1", + "hdmi_tx_l2", + "hdmi_tx_l3", + "hdmi_phy"; + + clocks = <&mmcc 116>, + <&gcc 214>; + clock-names = "iface", + "ref"; + #phy-cells = <0>; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + }; From e3c5ce88e8f93b498e0632add6899afc31d89607 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:38 +0300 Subject: [PATCH 31/46] dt-bindings: display/msm: hdmi: mark old GPIO properties as deprecated Mark obsolete GPIO properties as deprecated. They are not used by existing device trees. While we are at it, also drop them from the schema example. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488852/ Link: https://lore.kernel.org/r/20220609122350.3157529-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/hdmi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index 861678b2bf94..99b07abcd960 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -66,14 +66,17 @@ properties: qcom,hdmi-tx-mux-en-gpios: maxItems: 1 + deprecated: true description: HDMI mux enable pin qcom,hdmi-tx-mux-sel-gpios: maxItems: 1 + deprecated: true description: HDMI mux select pin qcom,hdmi-tx-mux-lpm-gpios: maxItems: 1 + deprecated: true description: HDMI mux lpm pin '#sound-dai-cells': From 6c04d89a6138a3d398e893c6c1f7542b1ff406a3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:39 +0300 Subject: [PATCH 32/46] dt-bindings: display/msm: hdmi: mark hdmi-mux-supply as deprecated hdmi-mux-supply is not used by the SoC's HDMI block, it is thought to power up the external logic. Thus it should not be a part of HDMI bindings, but it should be declared at some other device in the DT (like HDMI mux, bridge, etc). Mark it as deprecated. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488870/ Link: https://lore.kernel.org/r/20220609122350.3157529-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/hdmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.yaml b/Documentation/devicetree/bindings/display/msm/hdmi.yaml index 99b07abcd960..47e97669821c 100644 --- a/Documentation/devicetree/bindings/display/msm/hdmi.yaml +++ b/Documentation/devicetree/bindings/display/msm/hdmi.yaml @@ -56,6 +56,7 @@ properties: hdmi-mux-supply: description: phandle to mux regulator + deprecated: true core-vcc-supply: description: phandle to VCC supply regulator From 7fbf025305e9f9f554ec5f0ac781035c7edd27a6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:41 +0300 Subject: [PATCH 33/46] drm/msm/hdmi: drop the hdmi-mux support With the last (and only) in-kernel user of hdmi-mux regulator, drop it from the HDMI driver. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488855/ Link: https://lore.kernel.org/r/20220609122350.3157529-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 73070ec1a936..7267167d5ef1 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -361,7 +361,7 @@ static const char *hpd_reg_names_none[] = {}; static struct hdmi_platform_config hdmi_tx_8660_config; -static const char *hpd_reg_names_8960[] = {"core-vdda", "hdmi-mux"}; +static const char *hpd_reg_names_8960[] = {"core-vdda"}; static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"}; static struct hdmi_platform_config hdmi_tx_8960_config = { From 68e674b13b17ed41aac2763d12ece6deaae8df58 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:42 +0300 Subject: [PATCH 34/46] drm/msm/hdmi: drop unused GPIO support The HDMI driver has code to configure extra GPIOs, which predates pinctrl support. Nowadays all platforms should use pinctrl instead. Neither of upstreamed Qualcomm platforms uses these properties, so it's safe to drop them. Reported-by: kernel test robot Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/488858/ Link: https://lore.kernel.org/r/20220609122350.3157529-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 66 +++++++---------------------- drivers/gpu/drm/msm/hdmi/hdmi.h | 13 +----- drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 62 ++------------------------- 3 files changed, 21 insertions(+), 120 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 7267167d5ef1..6d79f1b910a5 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -233,6 +233,20 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) hdmi->pwr_clks[i] = clk; } + hdmi->hpd_gpiod = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN); + /* This will catch e.g. -EPROBE_DEFER */ + if (IS_ERR(hdmi->hpd_gpiod)) { + ret = PTR_ERR(hdmi->hpd_gpiod); + DRM_DEV_ERROR(&pdev->dev, "failed to get hpd gpio: (%d)\n", ret); + goto fail; + } + + if (!hdmi->hpd_gpiod) + DBG("failed to get HPD gpio"); + + if (hdmi->hpd_gpiod) + gpiod_set_consumer_name(hdmi->hpd_gpiod, "HDMI_HPD"); + pm_runtime_enable(&pdev->dev); hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); @@ -409,20 +423,6 @@ static struct hdmi_platform_config hdmi_tx_8996_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static const struct { - const char *name; - const bool output; - const int value; - const char *label; -} msm_hdmi_gpio_pdata[] = { - { "qcom,hdmi-tx-ddc-clk", true, 1, "HDMI_DDC_CLK" }, - { "qcom,hdmi-tx-ddc-data", true, 1, "HDMI_DDC_DATA" }, - { "qcom,hdmi-tx-hpd", false, 1, "HDMI_HPD" }, - { "qcom,hdmi-tx-mux-en", true, 1, "HDMI_MUX_EN" }, - { "qcom,hdmi-tx-mux-sel", true, 0, "HDMI_MUX_SEL" }, - { "qcom,hdmi-tx-mux-lpm", true, 1, "HDMI_MUX_LPM" }, -}; - /* * HDMI audio codec callbacks */ @@ -534,7 +534,7 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data) struct hdmi_platform_config *hdmi_cfg; struct hdmi *hdmi; struct device_node *of_node = dev->of_node; - int i, err; + int err; hdmi_cfg = (struct hdmi_platform_config *) of_device_get_match_data(dev); @@ -546,42 +546,6 @@ static int msm_hdmi_bind(struct device *dev, struct device *master, void *data) hdmi_cfg->mmio_name = "core_physical"; hdmi_cfg->qfprom_mmio_name = "qfprom_physical"; - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - const char *name = msm_hdmi_gpio_pdata[i].name; - struct gpio_desc *gpiod; - - /* - * We are fetching the GPIO lines "as is" since the connector - * code is enabling and disabling the lines. Until that point - * the power-on default value will be kept. - */ - gpiod = devm_gpiod_get_optional(dev, name, GPIOD_ASIS); - /* This will catch e.g. -PROBE_DEFER */ - if (IS_ERR(gpiod)) - return PTR_ERR(gpiod); - if (!gpiod) { - /* Try a second time, stripping down the name */ - char name3[32]; - - /* - * Try again after stripping out the "qcom,hdmi-tx" - * prefix. This is mainly to match "hpd-gpios" used - * in the upstream bindings. - */ - if (sscanf(name, "qcom,hdmi-tx-%s", name3)) - gpiod = devm_gpiod_get_optional(dev, name3, GPIOD_ASIS); - if (IS_ERR(gpiod)) - return PTR_ERR(gpiod); - if (!gpiod) - DBG("failed to get gpio: %s", name); - } - hdmi_cfg->gpios[i].gpiod = gpiod; - if (gpiod) - gpiod_set_consumer_name(gpiod, msm_hdmi_gpio_pdata[i].label); - hdmi_cfg->gpios[i].output = msm_hdmi_gpio_pdata[i].output; - hdmi_cfg->gpios[i].value = msm_hdmi_gpio_pdata[i].value; - } - dev->platform_data = hdmi_cfg; hdmi = msm_hdmi_init(to_platform_device(dev)); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h index 736f348befb3..a6c88d157bc3 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -19,17 +19,9 @@ #include "msm_drv.h" #include "hdmi.xml.h" -#define HDMI_MAX_NUM_GPIO 6 - struct hdmi_phy; struct hdmi_platform_config; -struct hdmi_gpio_data { - struct gpio_desc *gpiod; - bool output; - int value; -}; - struct hdmi_audio { bool enabled; struct hdmi_audio_infoframe infoframe; @@ -61,6 +53,8 @@ struct hdmi { struct clk **hpd_clks; struct clk **pwr_clks; + struct gpio_desc *hpd_gpiod; + struct hdmi_phy *phy; struct device *phy_dev; @@ -109,9 +103,6 @@ struct hdmi_platform_config { /* clks that need to be on for screen pwr (ie pixel clk): */ const char **pwr_clk_names; int pwr_clk_cnt; - - /* gpio's: */ - struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO]; }; struct hdmi_bridge { diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c index 75605ddac7c4..bfa827b47989 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c @@ -60,48 +60,6 @@ static void msm_hdmi_phy_reset(struct hdmi *hdmi) } } -static int gpio_config(struct hdmi *hdmi, bool on) -{ - const struct hdmi_platform_config *config = hdmi->config; - int i; - - if (on) { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (gpio.gpiod) { - if (gpio.output) { - gpiod_direction_output(gpio.gpiod, - gpio.value); - } else { - gpiod_direction_input(gpio.gpiod); - gpiod_set_value_cansleep(gpio.gpiod, - gpio.value); - } - } - } - - DBG("gpio on"); - } else { - for (i = 0; i < HDMI_MAX_NUM_GPIO; i++) { - struct hdmi_gpio_data gpio = config->gpios[i]; - - if (!gpio.gpiod) - continue; - - if (gpio.output) { - int value = gpio.value ? 0 : 1; - - gpiod_set_value_cansleep(gpio.gpiod, value); - } - } - - DBG("gpio off"); - } - - return 0; -} - static void enable_hpd_clocks(struct hdmi *hdmi, bool enable) { const struct hdmi_platform_config *config = hdmi->config; @@ -154,11 +112,8 @@ int msm_hdmi_hpd_enable(struct drm_bridge *bridge) goto fail; } - ret = gpio_config(hdmi, true); - if (ret) { - DRM_DEV_ERROR(dev, "failed to configure GPIOs: %d\n", ret); - goto fail; - } + if (hdmi->hpd_gpiod) + gpiod_set_value_cansleep(hdmi->hpd_gpiod, 1); pm_runtime_get_sync(dev); enable_hpd_clocks(hdmi, true); @@ -207,10 +162,6 @@ void msm_hdmi_hpd_disable(struct hdmi_bridge *hdmi_bridge) enable_hpd_clocks(hdmi, false); pm_runtime_put(dev); - ret = gpio_config(hdmi, false); - if (ret) - dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); - ret = pinctrl_pm_select_sleep_state(dev); if (ret) dev_warn(dev, "pinctrl state chg failed: %d\n", ret); @@ -269,10 +220,7 @@ static enum drm_connector_status detect_reg(struct hdmi *hdmi) #define HPD_GPIO_INDEX 2 static enum drm_connector_status detect_gpio(struct hdmi *hdmi) { - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; - - return gpiod_get_value(hpd_gpio.gpiod) ? + return gpiod_get_value(hdmi->hpd_gpiod) ? connector_status_connected : connector_status_disconnected; } @@ -282,8 +230,6 @@ enum drm_connector_status msm_hdmi_bridge_detect( { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; - const struct hdmi_platform_config *config = hdmi->config; - struct hdmi_gpio_data hpd_gpio = config->gpios[HPD_GPIO_INDEX]; enum drm_connector_status stat_gpio, stat_reg; int retry = 20; @@ -291,7 +237,7 @@ enum drm_connector_status msm_hdmi_bridge_detect( * some platforms may not have hpd gpio. Rely only on the status * provided by REG_HDMI_HPD_INT_STATUS in this case. */ - if (!hpd_gpio.gpiod) + if (!hdmi->hpd_gpiod) return detect_reg(hdmi); do { From 1f88301794595ff4c28a1f1befe690e8dbac72a2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:43 +0300 Subject: [PATCH 35/46] drm/msm/hdmi: enable core-vcc/core-vdda-supply for 8996 platform DB820c makes use of core-vcc-supply and core-vdda-supply, however the driver code doesn't support these regulators. Enable them for HDMI on 8996 platform. Fixes: 0afbe59edd3f ("drm/msm/hdmi: Add basic HDMI support for msm8996") Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/488857/ Link: https://lore.kernel.org/r/20220609122350.3157529-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 6d79f1b910a5..4ec55616a2e5 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -416,7 +416,7 @@ static struct hdmi_platform_config hdmi_tx_8994_config = { }; static struct hdmi_platform_config hdmi_tx_8996_config = { - HDMI_CFG(pwr_reg, none), + HDMI_CFG(pwr_reg, 8x74), HDMI_CFG(hpd_reg, none), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), From 53d9118f7d39f9ae8dc0555d7ae2186b4cf783e3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:44 +0300 Subject: [PATCH 36/46] drm/msm/hdmi: drop empty 'none' regulator lists Several platform configs use empty 'none' regulator arrays. They are not necessary, as the code will use corresponding _cnt field and skip the array completely. Drop them now. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488861/ Link: https://lore.kernel.org/r/20220609122350.3157529-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 4ec55616a2e5..8f0fd2795748 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -370,9 +370,6 @@ fail: .item ## _names = item ##_names_ ## entry, \ .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry) -static const char *pwr_reg_names_none[] = {}; -static const char *hpd_reg_names_none[] = {}; - static struct hdmi_platform_config hdmi_tx_8660_config; static const char *hpd_reg_names_8960[] = {"core-vdda"}; @@ -409,7 +406,6 @@ static struct hdmi_platform_config hdmi_tx_8084_config = { static struct hdmi_platform_config hdmi_tx_8994_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, none), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, @@ -417,7 +413,6 @@ static struct hdmi_platform_config hdmi_tx_8994_config = { static struct hdmi_platform_config hdmi_tx_8996_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, none), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, From b45aff9688e7d0e2dc478b43125d6901849a16b6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:45 +0300 Subject: [PATCH 37/46] drm/msm/hdmi: drop hpd_regs usage on 8x74/8084 The MSM HDMI driver has support for hpd_regs on 8x74/8084: supply regulators that are to be enabled for HPD to work. Currently these regulators contain the hpd_gdsc, which was replaced by the power-domains support and hpd-5v/hpd-5v-en, which are not used by the chip itself. They power up the ESD bridge. However it is a separate device which should be represented separately in the device tree. None of upstreamed devices support these properties. Thus drop support for them from the HDMI driver. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488860/ Link: https://lore.kernel.org/r/20220609122350.3157529-10-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 8f0fd2795748..48cd6b9a7565 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -381,24 +381,19 @@ static struct hdmi_platform_config hdmi_tx_8960_config = { }; static const char *pwr_reg_names_8x74[] = {"core-vdda", "core-vcc"}; -static const char *hpd_reg_names_8x74[] = {"hpd-gdsc", "hpd-5v"}; static const char *pwr_clk_names_8x74[] = {"extp", "alt_iface"}; static const char *hpd_clk_names_8x74[] = {"iface", "core", "mdp_core"}; static unsigned long hpd_clk_freq_8x74[] = {0, 19200000, 0}; static struct hdmi_platform_config hdmi_tx_8974_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, 8x74), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, }; -static const char *hpd_reg_names_8084[] = {"hpd-gdsc", "hpd-5v", "hpd-5v-en"}; - static struct hdmi_platform_config hdmi_tx_8084_config = { HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, 8084), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, From 9edaba8751ca4e218d06bfeb002ef27c34057e18 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:46 +0300 Subject: [PATCH 38/46] drm/msm/hdmi: merge platform config for 8974/8084/8994/8996 Since there is no more difference between the HDMI platform data between MSM8974/APQ8084/MSM8994/MSM8996, merge these configs into a single entry. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488868/ Link: https://lore.kernel.org/r/20220609122350.3157529-11-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 48cd6b9a7565..0f1c63f68569 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -392,27 +392,6 @@ static struct hdmi_platform_config hdmi_tx_8974_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static struct hdmi_platform_config hdmi_tx_8084_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - -static struct hdmi_platform_config hdmi_tx_8994_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - -static struct hdmi_platform_config hdmi_tx_8996_config = { - HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(pwr_clk, 8x74), - HDMI_CFG(hpd_clk, 8x74), - .hpd_freq = hpd_clk_freq_8x74, -}; - /* * HDMI audio codec callbacks */ @@ -583,9 +562,9 @@ static int msm_hdmi_dev_remove(struct platform_device *pdev) } static const struct of_device_id msm_hdmi_dt_match[] = { - { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config }, - { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, - { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, + { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8974_config }, + { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8974_config }, + { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config }, { .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config }, From ac1c2787bb297ccc0ae4d6071b3b21103145fe98 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:47 +0300 Subject: [PATCH 39/46] drm/msm/hdmi: reuse MSM8960's config for MSM8660 MSM8660 requires the same set of clocks and regulators as MSM8960. Reuse MSM8960's config for the MSM8660 (8x60). Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488864/ Link: https://lore.kernel.org/r/20220609122350.3157529-12-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 0f1c63f68569..6acc17e0efc1 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -370,8 +370,6 @@ fail: .item ## _names = item ##_names_ ## entry, \ .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry) -static struct hdmi_platform_config hdmi_tx_8660_config; - static const char *hpd_reg_names_8960[] = {"core-vdda"}; static const char *hpd_clk_names_8960[] = {"core", "master_iface", "slave_iface"}; @@ -567,7 +565,7 @@ static const struct of_device_id msm_hdmi_dt_match[] = { { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, { .compatible = "qcom,hdmi-tx-8960", .data = &hdmi_tx_8960_config }, - { .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8660_config }, + { .compatible = "qcom,hdmi-tx-8660", .data = &hdmi_tx_8960_config }, {} }; From 0f390c8ca0e18149ec77967cedf12aac8284b48d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:48 +0300 Subject: [PATCH 40/46] drm/msm/hdmi-phy: populate 8x60 HDMI PHY requirements Declare that 8x60 HDMI PHY uses the core-vdda regulator and slave_iface clock (this is the same config as is used by the 8960). Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/488863/ Link: https://lore.kernel.org/r/20220609122350.3157529-13-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c index 95f2928cb2cb..1d97640d8c24 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8x60.c @@ -122,8 +122,20 @@ static void hdmi_phy_8x60_powerdown(struct hdmi_phy *phy) HDMI_8x60_PHY_REG2_PD_DESER); } +static const char * const hdmi_phy_8x60_reg_names[] = { + "core-vdda", +}; + +static const char * const hdmi_phy_8x60_clk_names[] = { + "slave_iface", +}; + const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg = { .type = MSM_HDMI_PHY_8x60, .powerup = hdmi_phy_8x60_powerup, .powerdown = hdmi_phy_8x60_powerdown, + .reg_names = hdmi_phy_8x60_reg_names, + .num_regs = ARRAY_SIZE(hdmi_phy_8x60_reg_names), + .clk_names = hdmi_phy_8x60_clk_names, + .num_clks = ARRAY_SIZE(hdmi_phy_8x60_clk_names), }; From 089008b698f8c4a42e5e73b0a5628509b608b8da Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Jun 2022 11:50:54 +0300 Subject: [PATCH 41/46] drm/msm/hdmi: drop empty bridge callbacks Drop empty callbacks msm_hdmi_bridge_enable() and msm_hdmi_bridge_disable(). Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/489707/ Link: https://lore.kernel.org/r/20220616085054.432317-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index 97c24010c4d1..d569f0c6cab7 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -159,14 +159,6 @@ static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge) msm_hdmi_hdcp_on(hdmi->hdcp_ctrl); } -static void msm_hdmi_bridge_enable(struct drm_bridge *bridge) -{ -} - -static void msm_hdmi_bridge_disable(struct drm_bridge *bridge) -{ -} - static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge) { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); @@ -306,8 +298,6 @@ static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { .pre_enable = msm_hdmi_bridge_pre_enable, - .enable = msm_hdmi_bridge_enable, - .disable = msm_hdmi_bridge_disable, .post_disable = msm_hdmi_bridge_post_disable, .mode_set = msm_hdmi_bridge_mode_set, .mode_valid = msm_hdmi_bridge_mode_valid, From a7977d5cd9dbf4c9e8706d9e254655ed422859f0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Jun 2022 11:50:57 +0300 Subject: [PATCH 42/46] drm/msm/hdmi: support attaching the "next" bridge There might be a chain of bridges attached to the HDMI node (including but not limited to the display-connector bridge). Add support for attaching them right to the HDMI bridge chain. Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/489709/ Link: https://lore.kernel.org/r/20220616085057.432353-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.c | 14 ++++++++++++++ drivers/gpu/drm/msm/hdmi/hdmi.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 6acc17e0efc1..93fe61b86967 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -9,6 +9,7 @@ #include #include +#include #include #include "hdmi.h" @@ -133,6 +134,10 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) hdmi->config = config; spin_lock_init(&hdmi->reg_lock); + ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, 1, 0, NULL, &hdmi->next_bridge); + if (ret && ret != -ENODEV) + goto fail; + hdmi->mmio = msm_ioremap(pdev, config->mmio_name); if (IS_ERR(hdmi->mmio)) { ret = PTR_ERR(hdmi->mmio); @@ -308,6 +313,15 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi, goto fail; } + if (hdmi->next_bridge) { + ret = drm_bridge_attach(hdmi->encoder, hdmi->next_bridge, hdmi->bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) { + DRM_DEV_ERROR(dev->dev, "failed to attach next HDMI bridge: %d\n", ret); + goto fail; + } + } + hdmi->connector = drm_bridge_connector_init(hdmi->dev, encoder); if (IS_ERR(hdmi->connector)) { ret = PTR_ERR(hdmi->connector); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h index a6c88d157bc3..04a74381aaf7 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -62,6 +62,8 @@ struct hdmi { struct drm_connector *connector; struct drm_bridge *bridge; + struct drm_bridge *next_bridge; + /* the encoder we are hooked to (outside of hdmi block) */ struct drm_encoder *encoder; From a143890fefa5c519772cace8be27ca1bd1792e95 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 5 May 2022 16:50:07 +0300 Subject: [PATCH 43/46] drm/msm/mdp4: move iommu_domain_alloc() call close to its usage Move iommu_domain_alloc() in front of adress space/IOMMU initialization. This allows us to drop it from struct mdp4_cfg_platform which remained from the pre-DT days. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/485049/ Link: https://lore.kernel.org/r/20220505135008.1351533-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 8 ++++---- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 17cb1fc78379..b55b4a4067be 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -390,6 +390,7 @@ static int mdp4_kms_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct mdp4_kms *mdp4_kms; struct msm_kms *kms = NULL; + struct iommu_domain *iommu; struct msm_gem_address_space *aspace; int irq, ret; u32 major, minor; @@ -497,9 +498,9 @@ static int mdp4_kms_init(struct drm_device *dev) mdp4_disable(mdp4_kms); mdelay(16); - if (config->iommu) { - struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, - config->iommu); + iommu = iommu_domain_alloc(pdev->dev.bus); + if (iommu) { + struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu); aspace = msm_gem_address_space_create(mmu, "mdp4", 0x1000, 0x100000000 - 0x1000); @@ -559,7 +560,6 @@ static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ config.max_clk = 266667000; - config.iommu = iommu_domain_alloc(&platform_bus_type); return &config; } diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h index e8ee92ab7956..7cc549b6a82b 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h @@ -44,7 +44,6 @@ struct mdp4_kms { /* platform config data (ie. from DT, or pdata) */ struct mdp4_platform_config { - struct iommu_domain *iommu; uint32_t max_clk; }; From 97b10e15df73249a6e5dfe36d07322110748cf67 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 5 May 2022 16:50:08 +0300 Subject: [PATCH 44/46] drm/msm/mdp4: get rid of struct mdp4_platform_config Struct mdp4_platform_config is a relict from the DT-conversion time. Move the max_clk field to the mdp4_kms_init(), the place where it is used and drop the struct mdp4_platform_config and the mdp4_get_config() function. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/485050/ Link: https://lore.kernel.org/r/20220505135008.1351533-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 21 ++++++--------------- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 5 ----- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index b55b4a4067be..964573d26d26 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -13,8 +13,6 @@ #include "msm_mmu.h" #include "mdp4_kms.h" -static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev); - static int mdp4_hw_init(struct msm_kms *kms) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); @@ -386,7 +384,6 @@ static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms, static int mdp4_kms_init(struct drm_device *dev) { struct platform_device *pdev = to_platform_device(dev->dev); - struct mdp4_platform_config *config = mdp4_get_config(pdev); struct msm_drm_private *priv = dev->dev_private; struct mdp4_kms *mdp4_kms; struct msm_kms *kms = NULL; @@ -394,6 +391,10 @@ static int mdp4_kms_init(struct drm_device *dev) struct msm_gem_address_space *aspace; int irq, ret; u32 major, minor; + unsigned long max_clk; + + /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ + max_clk = 266667000; mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); if (!mdp4_kms) { @@ -461,7 +462,7 @@ static int mdp4_kms_init(struct drm_device *dev) goto fail; } - clk_set_rate(mdp4_kms->clk, config->max_clk); + clk_set_rate(mdp4_kms->clk, max_clk); read_mdp_hw_revision(mdp4_kms, &major, &minor); @@ -481,7 +482,7 @@ static int mdp4_kms_init(struct drm_device *dev) ret = PTR_ERR(mdp4_kms->lut_clk); goto fail; } - clk_set_rate(mdp4_kms->lut_clk, config->max_clk); + clk_set_rate(mdp4_kms->lut_clk, max_clk); } pm_runtime_enable(dev->dev); @@ -554,16 +555,6 @@ fail: return ret; } -static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) -{ - static struct mdp4_platform_config config = {}; - - /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ - config.max_clk = 266667000; - - return &config; -} - static const struct dev_pm_ops mdp4_pm_ops = { .prepare = msm_pm_prepare, .complete = msm_pm_complete, diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h index 7cc549b6a82b..01179e764a29 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h @@ -42,11 +42,6 @@ struct mdp4_kms { }; #define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base) -/* platform config data (ie. from DT, or pdata) */ -struct mdp4_platform_config { - uint32_t max_clk; -}; - static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data) { msm_writel(data, mdp4_kms->mmio + reg); From eeda2bc4fcd9f544b668efc6489ab165dc0d607e Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sat, 11 Jun 2022 00:53:02 +0200 Subject: [PATCH 45/46] drm/msm/mdp5: Add perf data for MDP v1.16 Add the perf data for the mdp found in msm8953. Signed-off-by: Vladimir Lypak Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/489153/ Link: https://lore.kernel.org/r/20220610225304.267508-1-luca@z3ntu.xyz Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 1bf9ff5dbabc..b17f868ffca8 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -837,6 +837,11 @@ static const struct mdp5_cfg_hw msm8x53_config = { [2] = INTF_DSI, }, }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 105 + }, .max_clk = 400000000, }; From fca5ad26b7d8390f474d886a0778d4f9266c6662 Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Tue, 21 Jun 2022 02:06:26 -0700 Subject: [PATCH 46/46] drm/msm/disp/dpu1: add dspp support for sc7280 Add destination side post processing hw block support in sc7280. This hwblock enablement is necessary to support color features like CT Matix (Ex: Night Light feature) Signed-off-by: Kalyan Thota Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/490382/ Link: https://lore.kernel.org/r/1655802387-15275-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index c7d46cd8c35e..0239a811d5ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -1015,7 +1015,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = { static const struct dpu_lm_cfg sc7280_lm[] = { LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, - &sc7180_lm_sblk, PINGPONG_0, 0, 0), + &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK, &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK, @@ -1884,6 +1884,8 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = { .ctl = sc7280_ctl, .sspp_count = ARRAY_SIZE(sc7280_sspp), .sspp = sc7280_sspp, + .dspp_count = ARRAY_SIZE(sc7180_dspp), + .dspp = sc7180_dspp, .mixer_count = ARRAY_SIZE(sc7280_lm), .mixer = sc7280_lm, .pingpong_count = ARRAY_SIZE(sc7280_pp),