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media: ccs-pll: Correct the upper limit of maximum op_pre_pll_clk_div

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commit f639494db450770fa30d6845d9c84b9cb009758f upstream.

The PLL calculator does a search of the PLL configuration space for all
valid OP pre-PLL clock dividers. The maximum did not take into account the
CCS PLL flag CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER in which case also odd PLL
dividers (other than 1) are valid. Do that now.

Fixes: 4e1e8d240d ("media: ccs-pll: Add support for extended input PLL clock divider")
Cc: stable@vger.kernel.org
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sakari Ailus
2025-02-19 15:06:11 +02:00
committed by Greg Kroah-Hartman
parent b9e314231f
commit 1e4b3f1667
1 changed files with 1 additions and 1 deletions
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2
drivers/media/i2c/ccs-pll.c
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@@ -794,7 +794,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div); op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
max_op_pre_pll_clk_div = max_op_pre_pll_clk_div =
min_t(u16, op_lim_fr->max_pre_pll_clk_div, min_t(u16, op_lim_fr->max_pre_pll_clk_div,
clk_div_even(pll->ext_clk_freq_hz / DIV_ROUND_UP(pll->ext_clk_freq_hz,
op_lim_fr->min_pll_ip_clk_freq_hz)); op_lim_fr->min_pll_ip_clk_freq_hz));
min_op_pre_pll_clk_div = min_op_pre_pll_clk_div =
max_t(u16, op_lim_fr->min_pre_pll_clk_div, max_t(u16, op_lim_fr->min_pre_pll_clk_div,