Merge tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc
Pull MMC updates from Ulf Hansson: "MMC core: - Add new API to set VCCQ voltage - mmc_regulator_set_vqmmc() - Add new ioctl to allow userspace to send multi commands - Wait for card busy signalling before starting SDIO requests - Remove MMC_CLKGATE - Enable tuning for DDR50 mode - Some code clean-up/improvements to mmc pwrseq - Use highest priority for eMMC restart handler - Add DT bindings for eMMC hardware reset support - Extend the mmc_send_tuning() API - Improve ios show for debugfs - A couple of code optimizations MMC host: - Some generic OF improvements - Various code clean-ups - sirf: Add support for DDR50 - sunxi: Add support for card busy detection - mediatek: Use MMC_CAP_RUNTIME_RESUME - mediatek: Add support for eMMC HW-reset - mediatek: Add support for HS400 - dw_mmc: Convert to use the new mmc_regulator_set_vqmmc() API - dw_mmc: Add external DMA interface support - dw_mmc: Some various improvements - dw_mmc-rockchip: MMC tuning with the clock phase framework - sdhci: Properly clear IRQs during resume - sdhci: Enable tuning for DDR50 mode - sdhci-of-esdhc: Use IRQ mode for card detection - sdhci-of-esdhc: Support both BE and LE host controller - sdhci-pci: Build o2micro support in the same module - sdhci-pci: Support for new Intel host controllers - sdhci-acpi: Support for new Intel host controllers" * tag 'mmc-v4.4' of git://git.linaro.org/people/ulf.hansson/mmc: (73 commits) mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register mmc: dw_mmc: NULL dereference in error message mmc: pwrseq: Use highest priority for eMMC restart handler mmc: mediatek: add HS400 support mmc: mmc: extend the mmc_send_tuning() mmc: mediatek: add implement of ops->hw_reset() mmc: mediatek: fix got GPD checksum error interrupt when data transfer mmc: mediatek: change the argument "ddr" to "timing" mmc: mediatek: make cmd_ints_mask to const mmc: dt-bindings: update Mediatek MMC bindings mmc: core: Add DT bindings for eMMC hardware reset support mmc: omap_hsmmc: Enable omap_hsmmc for Keystone 2 mmc: sdhci-acpi: Add more ACPI HIDs for Intel controllers mmc: sdhci-pci: Add more PCI IDs for Intel controllers arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC ...
This commit is contained in:
Linus Torvalds
@@ -22,6 +22,8 @@ Optional properties:
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- voltage-ranges : two cells are required, first cell specifies minimum
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slot voltage (mV), second cell specifies maximum slot voltage (mV).
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Several ranges could be specified.
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- little-endian : If the host controller is little-endian mode, specify
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this property. The default endian mode is big-endian.
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Example:
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@@ -37,6 +37,7 @@ Optional properties:
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- sd-uhs-sdr104: SD UHS SDR104 speed is supported
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- sd-uhs-ddr50: SD UHS DDR50 speed is supported
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- cap-power-off-card: powering off the card is safe
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- cap-mmc-hw-reset: eMMC hardware reset is supported
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- cap-sdio-irq: enable SDIO IRQ signalling on this interface
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- full-pwr-cycle: full power cycle of the card is supported
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- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
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@@ -17,6 +17,11 @@ Required properties:
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- vmmc-supply: power to the Core
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- vqmmc-supply: power to the IO
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Optional properties:
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- assigned-clocks: PLL of the source clock
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- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
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- hs400-ds-delay: HS400 DS delay setting
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Examples:
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
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@@ -24,9 +29,13 @@ mmc0: mmc@11230000 {
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
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vmmc-supply = <&mt6397_vemc_3v3_reg>;
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vqmmc-supply = <&mt6397_vio18_reg>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clocks = <&pericfg CLK_PERI_MSDC30_0>,
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<&topckgen CLK_TOP_MSDC50_0_H_SEL>;
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clock-names = "source", "hclk";
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
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hs400-ds-delay = <0x14015>;
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};
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@@ -6,11 +6,12 @@ and the properties used by the MMCIF device.
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Required properties:
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- compatible: must contain one of the following
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- compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
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fallback. Examples with <soctype> are:
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- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
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- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
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- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
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- "renesas,sh-mmcif" for the generic MMCIF
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- "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs
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- clocks: reference to the functional clock
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@@ -14,6 +14,19 @@ Required Properties:
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before RK3288
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- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
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Optional Properties:
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* clocks: from common clock binding: if ciu_drive and ciu_sample are
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specified in clock-names, should contain handles to these clocks.
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* clock-names: Apart from the clock-names described in synopsys-dw-mshc.txt
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two more clocks "ciu-drive" and "ciu-sample" are supported. They are used
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to control the clock phases, "ciu-sample" is required for tuning high-
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speed modes.
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* rockchip,default-sample-phase: The default phase to set ciu_sample at
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probing, low speeds or in case where all phases work at tuning time.
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If not specified 0 deg will be used.
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Example:
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rkdwmmc0@12200000 {
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@@ -75,6 +75,12 @@ Optional properties:
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* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
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specified we'll defer probe until we can find this regulator.
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* dmas: List of DMA specifiers with the controller specific format as described
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in the generic DMA client binding. Refer to dma.txt for details.
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* dma-names: request names for generic DMA client binding. Must be "rx-tx".
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Refer to dma.txt for details.
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Aliases:
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- All the MSHC controller nodes should be represented in the aliases node using
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@@ -95,6 +101,8 @@ board specific portions as listed below.
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#size-cells = <0>;
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};
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[board specific internal DMA resources]
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dwmmc0@12200000 {
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clock-frequency = <400000000>;
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clock-freq-min-max = <400000 200000000>;
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@@ -107,3 +115,20 @@ board specific portions as listed below.
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cap-mmc-highspeed;
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cap-sd-highspeed;
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};
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[board specific generic DMA request binding]
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dwmmc0@12200000 {
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clock-frequency = <400000000>;
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clock-freq-min-max = <400000 200000000>;
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num-slots = <1>;
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broken-cd;
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fifo-depth = <0x80>;
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card-detect-delay = <200>;
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vmmc-supply = <&buck8>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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dmas = <&pdma 12>;
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dma-names = "rx-tx";
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};
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@@ -72,13 +72,3 @@ Note on raw_rpmb_size_mult:
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"raw_rpmb_size_mult" is a mutliple of 128kB block.
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RPMB size in byte is calculated by using the following equation:
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RPMB partition size = 128kB x raw_rpmb_size_mult
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SD/MMC/SDIO Clock Gating Attribute
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==================================
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Read and write access is provided to following attribute.
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This attribute appears only if CONFIG_MMC_CLKGATE is enabled.
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clkgate_delay Tune the clock gating delay with desired value in milliseconds.
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echo <desired delay> > /sys/class/mmc_host/mmcX/clkgate_delay
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