samsung_sm8750/android_kernel_samsung_sm8750
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm64: zynqmp: add clock-output-names property in clock nodes

Browse Source 
[ Upstream commit 385a59e7f7fb3438466a0712cc14672c708bbd57 ]

Add clock-output-names property to clock nodes, so that the resulting
clock name do not change when clock node name is changed.
Also, replace underscores with hyphens in the clock node names as per
dt-schema rule.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Link: https://lore.kernel.org/r/20241122095712.1166883-1-naman.trivedimanojbhai@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Naman Trivedi
2024-11-22 01:57:12 -08:00
committed by Greg Kroah-Hartman
parent 23b0b86ad1
commit 123ac614e5
1 changed files with 10 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
View File

@@ -10,39 +10,44 @@
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
pss_ref_clk: pss_ref_clk {
pss_ref_clk: pss-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
clock-output-names = "pss_ref_clk";
};
video_clk: video_clk {
video_clk: video-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "video_clk";
};
pss_alt_ref_clk: pss_alt_ref_clk {
pss_alt_ref_clk: pss-alt-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "pss_alt_ref_clk";
};
gt_crx_ref_clk: gt_crx_ref_clk {
gt_crx_ref_clk: gt-crx-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
clock-output-names = "gt_crx_ref_clk";
};
aux_ref_clk: aux_ref_clk {
aux_ref_clk: aux-ref-clk {
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "aux_ref_clk";
};
};