MIPS: Netlogic: Move code common with XLP to common/
- Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Jayachandran C
committed by
Ralf Baechle
Ralf Baechle
parent
99fb2f7984
commit
0c9654072a
188
arch/mips/netlogic/common/smp.c
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188
arch/mips/netlogic/common/smp.c
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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void nlm_send_ipi_single(int logical_cpu, unsigned int action)
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{
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int cpu = cpu_logical_map(logical_cpu);
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if (action & SMP_CALL_FUNCTION)
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nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
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if (action & SMP_RESCHEDULE_YOURSELF)
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nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
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}
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void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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int cpu;
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for_each_cpu(cpu, mask) {
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nlm_send_ipi_single(cpu, action);
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}
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}
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/* IRQ_IPI_SMP_FUNCTION Handler */
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
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{
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smp_call_function_interrupt();
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write_c0_eirr(1ull << irq);
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}
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/* IRQ_IPI_SMP_RESCHEDULE handler */
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
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{
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scheduler_ipi();
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write_c0_eirr(1ull << irq);
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}
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/*
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* Called before going into mips code, early cpu init
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*/
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void nlm_early_init_secondary(int cpu)
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{
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write_c0_ebase((uint32_t)nlm_common_ebase);
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#ifdef NLM_XLP
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if (cpu % 4 == 0)
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xlp_mmu_init();
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#endif
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}
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/*
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* Code to run on secondary just after probing the CPU
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*/
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static void __cpuinit nlm_init_secondary(void)
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{
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nlm_smp_irq_init();
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}
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void nlm_smp_finish(void)
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{
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#ifdef notyet
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nlm_common_msgring_cpu_init();
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#endif
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local_irq_enable();
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}
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void nlm_cpus_done(void)
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{
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}
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/*
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* Boot all other cpus in the system, initialize them, and bring them into
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* the boot function
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*/
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int nlm_cpu_unblock[NR_CPUS];
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int nlm_cpu_ready[NR_CPUS];
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unsigned long nlm_next_gp;
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unsigned long nlm_next_sp;
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cpumask_t phys_cpu_present_map;
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void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
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{
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unsigned long gp = (unsigned long)task_thread_info(idle);
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unsigned long sp = (unsigned long)__KSTK_TOS(idle);
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int cpu = cpu_logical_map(logical_cpu);
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nlm_next_sp = sp;
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nlm_next_gp = gp;
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/* barrier */
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__sync();
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nlm_cpu_unblock[cpu] = 1;
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}
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void __init nlm_smp_setup(void)
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{
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unsigned int boot_cpu;
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int num_cpus, i;
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boot_cpu = hard_smp_processor_id();
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cpus_clear(phys_cpu_present_map);
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cpu_set(boot_cpu, phys_cpu_present_map);
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__cpu_number_map[boot_cpu] = 0;
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__cpu_logical_map[0] = boot_cpu;
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cpu_set(0, cpu_possible_map);
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num_cpus = 1;
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for (i = 0; i < NR_CPUS; i++) {
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/*
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* nlm_cpu_ready array is not set for the boot_cpu,
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* it is only set for ASPs (see smpboot.S)
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*/
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if (nlm_cpu_ready[i]) {
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cpu_set(i, phys_cpu_present_map);
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__cpu_number_map[i] = num_cpus;
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__cpu_logical_map[num_cpus] = i;
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cpu_set(num_cpus, cpu_possible_map);
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++num_cpus;
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}
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}
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pr_info("Phys CPU present map: %lx, possible map %lx\n",
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(unsigned long)phys_cpu_present_map.bits[0],
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(unsigned long)cpu_possible_map.bits[0]);
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pr_info("Detected %i Slave CPU(s)\n", num_cpus);
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}
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void nlm_prepare_cpus(unsigned int max_cpus)
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{
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}
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struct plat_smp_ops nlm_smp_ops = {
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.send_ipi_single = nlm_send_ipi_single,
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.send_ipi_mask = nlm_send_ipi_mask,
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.init_secondary = nlm_init_secondary,
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.smp_finish = nlm_smp_finish,
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.cpus_done = nlm_cpus_done,
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.boot_secondary = nlm_boot_secondary,
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.smp_setup = nlm_smp_setup,
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.prepare_cpus = nlm_prepare_cpus,
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};
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