1485 lines
39 KiB
Plaintext
Executable File
1485 lines
39 KiB
Plaintext
Executable File
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/msm/msm-camera.h>
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&soc {
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qcom,cam-req-mgr {
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compatible = "qcom,cam-req-mgr";
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status = "ok";
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};
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cam_csiphy0: qcom,csiphy0 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
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reg = <0x0ac65000 0x1000>;
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reg-names = "csiphy";
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reg-cam-base = <0x65000>;
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interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 880000 1200000>;
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rgltr-max-voltage = <0 0 880000 1200000>;
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rgltr-load-current = <0 0 80000 80000>;
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clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&camcc CAM_CC_CSIPHY0_CLK>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI0PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy0_clk",
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"csi0phytimer_clk_src",
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"csi0phytimer_clk";
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src-clock-name = "csi0phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs", "svs_l1";
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clock-rates =
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<300000000 0 300000000 0>,
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<384000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok";
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};
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cam_csiphy1: qcom,csiphy1 {
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cell-index = <1>;
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compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
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reg = <0xac66000 0x1000>;
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reg-names = "csiphy";
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reg-cam-base = <0x66000>;
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interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 880000 1200000>;
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rgltr-max-voltage = <0 0 880000 1200000>;
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rgltr-load-current = <0 0 80000 80000>;
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clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&camcc CAM_CC_CSIPHY1_CLK>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI1PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy1_clk",
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"csi1phytimer_clk_src",
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"csi1phytimer_clk";
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src-clock-name = "csi1phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs", "svs_l1";
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clock-rates =
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<300000000 0 300000000 0>,
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<384000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok";
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};
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cam_csiphy2: qcom,csiphy2 {
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cell-index = <2>;
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compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
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reg = <0xac67000 0x1000>;
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reg-names = "csiphy";
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reg-cam-base = <0x67000>;
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interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 880000 1200000>;
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rgltr-max-voltage = <0 0 880000 1200000>;
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rgltr-load-current = <0 0 80000 80000>;
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clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&camcc CAM_CC_CSIPHY2_CLK>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI2PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy2_clk",
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"csi2phytimer_clk_src",
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"csi2phytimer_clk";
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src-clock-name = "csi2phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs", "svs_l1";
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clock-rates =
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<300000000 0 300000000 0>,
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<384000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok";
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};
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cam_csiphy3: qcom,csiphy3 {
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cell-index = <3>;
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compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
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reg = <0xac68000 0x1000>;
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reg-names = "csiphy";
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reg-cam-base = <0x68000>;
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interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "csiphy";
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regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
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"mipi-csi-vdd2";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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refgen-supply = <&refgen>;
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mipi-csi-vdd1-supply = <&L18A>;
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mipi-csi-vdd2-supply = <&L22A>;
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rgltr-cntrl-support;
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rgltr-min-voltage = <0 0 880000 1200000>;
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rgltr-max-voltage = <0 0 880000 1200000>;
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rgltr-load-current = <0 0 80000 80000>;
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clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
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<&camcc CAM_CC_CSIPHY3_CLK>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
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<&camcc CAM_CC_CSI3PHYTIMER_CLK>;
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clock-names = "cphy_rx_clk_src",
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"csiphy3_clk",
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"csi3phytimer_clk_src",
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"csi3phytimer_clk";
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src-clock-name = "csi3phytimer_clk_src";
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clock-cntl-level = "lowsvs", "svs", "svs_l1";
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clock-rates =
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<300000000 0 300000000 0>,
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<384000000 0 300000000 0>,
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<400000000 0 300000000 0>;
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status = "ok";
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};
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cam_cci0: qcom,cci0 {
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cell-index = <0>;
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compatible = "qcom,cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xac4a000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x4a000>;
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interrupt-names = "cci";
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interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
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status = "ok";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&camcc CAM_CC_CCI_0_CLK>,
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<&camcc CAM_CC_CCI_0_CLK_SRC>;
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clock-names = "cci_0_clk",
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"cci_0_clk_src";
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src-clock-name = "cci_0_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci0_active &cci1_active>;
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pinctrl-1 = <&cci0_suspend &cci1_suspend>;
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gpios = <&tlmm 39 0>,
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<&tlmm 40 0>,
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<&tlmm 41 0>,
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<&tlmm 42 0>;
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gpio-req-tbl-num = <0 1 2 3>;
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gpio-req-tbl-flags = <1 1 1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA0",
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"CCI_I2C_CLK0",
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"CCI_I2C_DATA1",
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"CCI_I2C_CLK1";
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i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_custom_cci0: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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};
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cam_cci1: qcom,cci1 {
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cell-index = <1>;
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compatible = "qcom,cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xac4b000 0x1000>;
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reg-names = "cci";
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reg-cam-base = <0x4b000>;
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interrupt-names = "cci";
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interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
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status = "ok";
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gdscr-supply = <&cam_cc_titan_top_gdsc>;
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regulator-names = "gdscr";
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clocks = <&camcc CAM_CC_CCI_1_CLK>,
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<&camcc CAM_CC_CCI_1_CLK_SRC>;
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clock-names = "cci_clk",
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"cci_1_clk_src";
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src-clock-name = "cci_1_clk_src";
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clock-cntl-level = "lowsvs";
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clock-rates = <0 37500000>;
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pinctrl-names = "cam_default", "cam_suspend";
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pinctrl-0 = <&cci2_active>;
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pinctrl-1 = <&cci2_suspend>;
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gpios = <&tlmm 43 0>,
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<&tlmm 44 0>;
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gpio-req-tbl-num = <0 1>;
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gpio-req-tbl-flags = <1 1>;
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gpio-req-tbl-label = "CCI_I2C_DATA2",
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"CCI_I2C_CLK2";
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i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
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hw-thigh = <201>;
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hw-tlow = <174>;
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hw-tsu-sto = <204>;
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hw-tsu-sta = <231>;
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hw-thd-dat = <22>;
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hw-thd-sta = <162>;
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hw-tbuf = <227>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_custom_cci1: qcom,i2c_custom_mode {
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hw-thigh = <38>;
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hw-tlow = <56>;
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hw-tsu-sto = <40>;
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hw-tsu-sta = <40>;
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hw-thd-dat = <22>;
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hw-thd-sta = <35>;
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hw-tbuf = <62>;
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hw-scl-stretch-en = <1>;
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hw-trdhld = <6>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
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hw-thigh = <16>;
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hw-tlow = <22>;
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hw-tsu-sto = <17>;
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hw-tsu-sta = <18>;
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hw-thd-dat = <16>;
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hw-thd-sta = <15>;
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hw-tbuf = <24>;
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hw-scl-stretch-en = <0>;
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hw-trdhld = <3>;
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hw-tsp = <3>;
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cci-clk-src = <37500000>;
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status = "ok";
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};
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};
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qcom,cam_smmu {
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compatible = "qcom,msm-cam-smmu";
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status = "ok";
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non-fatal-fault-disabled;
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msm_cam_smmu_lrme {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0xD40 0x20>,
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<&apps_smmu 0xD60 0x20>;
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cam-smmu-label = "lrme";
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lrme_iova_mem_map: iova-mem-map {
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iova-mem-region-shared {
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/* Shared region is 100MB long */
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iova-region-name = "shared";
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iova-region-start = <0x7400000>;
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iova-region-len = <0x6400000>;
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iova-region-id = <0x1>;
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status = "ok";
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};
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/* IO region is approximately 3.3 GB */
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iova-mem-region-io {
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iova-region-name = "io";
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iova-region-start = <0xd800000>;
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iova-region-len = <0xd2800000>;
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iova-region-id = <0x3>;
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status = "ok";
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};
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};
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};
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msm_cam_smmu_ife {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0x820 0xc0>,
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<&apps_smmu 0x840 0x0>,
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<&apps_smmu 0x860 0xc0>,
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<&apps_smmu 0x880 0x0>;
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cam-smmu-label = "ife";
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ife_iova_mem_map: iova-mem-map {
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/* IO region is approximately 3.4 GB */
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iova-mem-region-io {
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iova-region-name = "io";
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iova-region-start = <0x7400000>;
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iova-region-len = <0xd8c00000>;
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iova-region-id = <0x3>;
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status = "ok";
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};
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};
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};
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msm_cam_smmu_jpeg {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0xD00 0x20>,
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<&apps_smmu 0xD20 0x20>;
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cam-smmu-label = "jpeg";
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jpeg_iova_mem_map: iova-mem-map {
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/* IO region is approximately 3.4 GB */
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iova-mem-region-io {
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iova-region-name = "io";
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iova-region-start = <0x7400000>;
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iova-region-len = <0xd8c00000>;
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iova-region-id = <0x3>;
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status = "ok";
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};
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};
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};
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msm_cam_icp_fw {
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compatible = "qcom,msm-cam-smmu-fw-dev";
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label="icp";
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memory-region = <&pil_camera_mem>;
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};
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msm_cam_smmu_icp {
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compatible = "qcom,msm-cam-smmu-cb";
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iommus = <&apps_smmu 0xCA2 0x0>,
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<&apps_smmu 0xCC0 0x20>,
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<&apps_smmu 0xCE0 0x20>;
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cam-smmu-label = "icp";
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icp_iova_mem_map: iova-mem-map {
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iova-mem-region-firmware {
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/* Firmware region is 5MB */
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iova-region-name = "firmware";
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iova-region-start = <0x0>;
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iova-region-len = <0x500000>;
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iova-region-id = <0x0>;
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status = "ok";
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};
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iova-mem-region-shared {
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/* Shared region is 150MB long */
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iova-region-name = "shared";
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iova-region-start = <0x7400000>;
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iova-region-len = <0x9600000>;
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iova-region-id = <0x1>;
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iova-granularity = <0x15>;
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status = "ok";
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};
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iova-mem-region-secondary-heap {
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/* Secondary heap region is 1MB long */
|
|
iova-region-name = "secheap";
|
|
iova-region-start = <0x10A00000>;
|
|
iova-region-len = <0x100000>;
|
|
iova-region-id = <0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-region-io {
|
|
/* IO region is approximately 3 GB */
|
|
iova-region-name = "io";
|
|
iova-region-start = <0x10C00000>;
|
|
iova-region-len = <0xCF300000>;
|
|
iova-region-id = <0x3>;
|
|
status = "ok";
|
|
};
|
|
|
|
iova-mem-qdss-region {
|
|
/* qdss region is approximately 1MB */
|
|
iova-region-name = "qdss";
|
|
iova-region-start = <0x10B00000>;
|
|
iova-region-len = <0x100000>;
|
|
iova-region-id = <0x5>;
|
|
qdss-phy-addr = <0x16790000>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_cpas_cdm {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
iommus = <&apps_smmu 0xC80 0x0>;
|
|
cam-smmu-label = "cpas-cdm0";
|
|
cpas_cdm_iova_mem_map: iova-mem-map {
|
|
iova-mem-region-io {
|
|
/* IO region is approximately 3.4 GB */
|
|
iova-region-name = "io";
|
|
iova-region-start = <0x7400000>;
|
|
iova-region-len = <0xd8c00000>;
|
|
iova-region-id = <0x3>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_secure {
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
cam-smmu-label = "cam-secure";
|
|
qcom,secure-cb;
|
|
};
|
|
|
|
};
|
|
|
|
qcom,cam-cdm-intf {
|
|
compatible = "qcom,cam-cdm-intf";
|
|
cell-index = <0>;
|
|
label = "cam-cdm-intf";
|
|
num-hw-cdm = <1>;
|
|
cdm-client-names = "vfe",
|
|
"jpegdma",
|
|
"jpegenc",
|
|
"lrmecdm";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cpas-cdm0@ac48000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam170-cpas-cdm0";
|
|
label = "cpas-cdm";
|
|
reg = <0xac48000 0x1000>;
|
|
reg-names = "cpas-cdm";
|
|
reg-cam-base = <0x48000>;
|
|
interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "cpas-cdm";
|
|
regulator-names = "camss";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"cam_cc_soc_ahb_clk",
|
|
"cam_cc_cpas_ahb_clk",
|
|
"cam_cc_camnoc_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_SOC_AHB_CLK>,
|
|
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
|
<&camcc CAM_CC_CAMNOC_AXI_CLK>;
|
|
clock-rates = <0 0 0>;
|
|
clock-cntl-level = "svs";
|
|
cdm-client-names = "ife";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-isp {
|
|
compatible = "qcom,cam-isp";
|
|
arch-compat = "ife";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_csid0: qcom,csid0@acb3000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,csid170_200";
|
|
reg-names = "csid";
|
|
reg = <0xacb3000 0x1000>;
|
|
reg-cam-base = <0xb3000>;
|
|
interrupt-names = "csid0";
|
|
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife0";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife0-supply = <&cam_cc_ife_0_gdsc>;
|
|
clock-names =
|
|
"ife_csid_clk_src",
|
|
"ife_csid_clk",
|
|
"cphy_rx_clk_src",
|
|
"ife_cphy_rx_clk",
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_0_CSID_CLK>,
|
|
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
|
|
<&camcc CAM_CC_IFE_0_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_0_CLK>,
|
|
<&camcc CAM_CC_IFE_0_AXI_CLK>;
|
|
clock-rates =
|
|
<300000000 0 0 0 320000000 0 0>,
|
|
<384000000 0 0 0 404000000 0 0>,
|
|
<400000000 0 0 0 480000000 0 0>,
|
|
<400000000 0 0 0 600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_vfe0: qcom,vfe0@acaf000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,vfe170_150";
|
|
reg-names = "ife";
|
|
reg = <0xacaf000 0x4000>;
|
|
reg-cam-base = <0xaf000>;
|
|
interrupt-names = "ife0";
|
|
interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife0";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife0-supply = <&cam_cc_ife_0_gdsc>;
|
|
clock-names =
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_0_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_0_CLK>,
|
|
<&camcc CAM_CC_IFE_0_AXI_CLK>;
|
|
clock-rates =
|
|
<320000000 0 0>,
|
|
<404000000 0 0>,
|
|
<480000000 0 0>,
|
|
<600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-names-option = "ife_dsp_clk";
|
|
clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
|
|
clock-rates-option = <600000000>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_csid1: qcom,csid1@acba000 {
|
|
cell-index = <1>;
|
|
compatible = "qcom,csid170_200";
|
|
reg-names = "csid";
|
|
reg = <0xacba000 0x1000>;
|
|
reg-cam-base = <0xba000>;
|
|
interrupt-names = "csid1";
|
|
interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife1";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife1-supply = <&cam_cc_ife_1_gdsc>;
|
|
clock-names =
|
|
"ife_csid_clk_src",
|
|
"ife_csid_clk",
|
|
"cphy_rx_clk_src",
|
|
"ife_cphy_rx_clk",
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_1_CSID_CLK>,
|
|
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
|
|
<&camcc CAM_CC_IFE_1_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_1_CLK>,
|
|
<&camcc CAM_CC_IFE_1_AXI_CLK>;
|
|
clock-rates =
|
|
<300000000 0 0 0 320000000 0 0>,
|
|
<384000000 0 0 0 404000000 0 0>,
|
|
<400000000 0 0 0 480000000 0 0>,
|
|
<400000000 0 0 0 600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_vfe1: qcom,vfe1@acb6000 {
|
|
cell-index = <1>;
|
|
compatible = "qcom,vfe170_150";
|
|
reg-names = "ife";
|
|
reg = <0xacb6000 0x4000>;
|
|
reg-cam-base = <0xb6000>;
|
|
interrupt-names = "ife1";
|
|
interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife1";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife1-supply = <&cam_cc_ife_1_gdsc>;
|
|
clock-names =
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_1_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_1_CLK>,
|
|
<&camcc CAM_CC_IFE_1_AXI_CLK>;
|
|
clock-rates =
|
|
<320000000 0 0>,
|
|
<404000000 0 0>,
|
|
<480000000 0 0>,
|
|
<600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-names-option = "ife_dsp_clk";
|
|
clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
|
|
clock-rates-option = <600000000>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_csid2: qcom,csid2@acc1000 {
|
|
cell-index = <2>;
|
|
compatible = "qcom,csid170_200";
|
|
reg-names = "csid2";
|
|
reg = <0xacc1000 0x1000>;
|
|
reg-cam-base = <0xc1000>;
|
|
interrupt-names = "csid";
|
|
interrupts = <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife2";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife2-supply = <&cam_cc_ife_2_gdsc>;
|
|
clock-names =
|
|
"ife_csid_clk_src",
|
|
"ife_csid_clk",
|
|
"cphy_rx_clk_src",
|
|
"ife_cphy_rx_clk",
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_2_CSID_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_2_CSID_CLK>,
|
|
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
|
|
<&camcc CAM_CC_IFE_2_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_2_CLK>,
|
|
<&camcc CAM_CC_IFE_2_AXI_CLK>;
|
|
clock-rates =
|
|
<300000000 0 0 0 320000000 0 0>,
|
|
<384000000 0 0 0 404000000 0 0>,
|
|
<400000000 0 0 0 480000000 0 0>,
|
|
<400000000 0 0 0 600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_vfe2: qcom,vfe2@acbd000 {
|
|
cell-index = <2>;
|
|
compatible = "qcom,vfe170_150";
|
|
reg-names = "ife2";
|
|
reg = <0xacbd000 0x4000>;
|
|
reg-cam-base = <0xbd000>;
|
|
interrupt-names = "ife";
|
|
interrupts = <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss", "ife2";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
ife2-supply = <&cam_cc_ife_2_gdsc>;
|
|
clock-names =
|
|
"ife_clk_src",
|
|
"ife_clk",
|
|
"ife_axi_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_2_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_2_CLK>,
|
|
<&camcc CAM_CC_IFE_2_AXI_CLK>;
|
|
clock-rates =
|
|
<320000000 0 0>,
|
|
<404000000 0 0>,
|
|
<480000000 0 0>,
|
|
<600000000 0 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
clock-names-option = "ife_dsp_clk";
|
|
clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>;
|
|
clock-rates-option = <600000000>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_csid_lite: qcom,csid-lite@acc8000 {
|
|
cell-index = <3>;
|
|
compatible = "qcom,csid-lite170";
|
|
reg-names = "csid-lite";
|
|
reg = <0xacc8000 0x1000>;
|
|
reg-cam-base = <0xc8000>;
|
|
interrupt-names = "csid-lite";
|
|
interrupts = <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"ife_csid_clk_src",
|
|
"ife_csid_clk",
|
|
"cphy_rx_clk_src",
|
|
"ife_cphy_rx_clk",
|
|
"ife_clk_src",
|
|
"ife_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
|
|
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
|
|
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_LITE_CLK>;
|
|
clock-rates =
|
|
<300000000 0 0 0 320000000 0>,
|
|
<384000000 0 0 0 400000000 0>,
|
|
<400000000 0 0 0 480000000 0>,
|
|
<400000000 0 0 0 600000000 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_csid_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_vfe_lite: qcom,vfe-lite@acc4000 {
|
|
cell-index = <3>;
|
|
compatible = "qcom,vfe-lite170";
|
|
reg-names = "ife-lite";
|
|
reg = <0xacc4000 0x4000>;
|
|
reg-cam-base = <0xc4000>;
|
|
interrupt-names = "ife-lite";
|
|
interrupts = <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"ife_clk_src",
|
|
"ife_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
|
|
<&camcc CAM_CC_IFE_LITE_CLK>;
|
|
clock-rates =
|
|
<320000000 0>,
|
|
<400000000 0>,
|
|
<480000000 0>,
|
|
<600000000 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
|
|
src-clock-name = "ife_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-icp {
|
|
compatible = "qcom,cam-icp";
|
|
compat-hw-name = "qcom,icp",
|
|
"qcom,ipe0",
|
|
"qcom,bps";
|
|
num-icp = <1>;
|
|
num-ipe = <1>;
|
|
num-bps = <1>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_icp: qcom,icp@ac00000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam-icp_v1";
|
|
icp-version = <0x0100>;
|
|
reg = <0xac00000 0x6000>,
|
|
<0xac10000 0x8000>,
|
|
<0xac18000 0x3000>;
|
|
reg-names = "icp_qgic", "icp_sierra", "icp_csr";
|
|
reg-cam-base = <0x00000 0x10000 0x18000>;
|
|
interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "icp";
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"soc_fast_ahb",
|
|
"soc_ahb_clk",
|
|
"icp_clk",
|
|
"icp_clk_src";
|
|
src-clock-name = "icp_clk_src";
|
|
clocks =
|
|
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
|
|
<&camcc CAM_CC_SOC_AHB_CLK>,
|
|
<&camcc CAM_CC_ICP_CLK>,
|
|
<&camcc CAM_CC_ICP_CLK_SRC>;
|
|
|
|
clock-rates =
|
|
<100000000 0 0 384000000>,
|
|
<200000000 0 0 404000000>,
|
|
<300000000 0 0 600000000>,
|
|
<404000000 0 0 600000000>,
|
|
<404000000 0 0 600000000>;
|
|
clock-cntl-level = "lowsvs", "svs",
|
|
"svs_l1", "nominal", "turbo";
|
|
fw_name = "CAMERA_ICP.elf";
|
|
ubwc-cfg = <0x73 0x1CF>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_ipe0: qcom,ipe0 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam-ipe";
|
|
reg = <0xac87000 0xa000>;
|
|
reg-names = "ipe0_top";
|
|
reg-cam-base = <0x87000>;
|
|
regulator-names = "ipe0-vdd";
|
|
ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
|
|
clock-names =
|
|
"ipe_0_ahb_clk",
|
|
"ipe_0_areg_clk",
|
|
"ipe_0_axi_clk",
|
|
"ipe_0_clk",
|
|
"ipe_0_clk_src";
|
|
src-clock-name = "ipe_0_clk_src";
|
|
clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>,
|
|
<&camcc CAM_CC_IPE_0_AREG_CLK>,
|
|
<&camcc CAM_CC_IPE_0_AXI_CLK>,
|
|
<&camcc CAM_CC_IPE_0_CLK>,
|
|
<&camcc CAM_CC_IPE_0_CLK_SRC>;
|
|
|
|
clock-rates =
|
|
<0 0 0 0 240000000>,
|
|
<0 0 0 0 320000000>,
|
|
<0 0 0 0 404000000>,
|
|
<0 0 0 0 538666666>,
|
|
<0 0 0 0 600000000>;
|
|
clock-cntl-level = "lowsvs", "svs",
|
|
"svs_l1", "nominal", "turbo";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_bps: qcom,bps {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam-bps";
|
|
reg = <0xac6f000 0x8000>;
|
|
reg-names = "bps_top";
|
|
reg-cam-base = <0x6f000>;
|
|
regulator-names = "bps-vdd";
|
|
bps-vdd-supply = <&cam_cc_bps_gdsc>;
|
|
clock-names = "bps_ahb_clk",
|
|
"bps_areg_clk",
|
|
"bps_axi_clk",
|
|
"bps_clk",
|
|
"bps_clk_src";
|
|
src-clock-name = "bps_clk_src";
|
|
clocks =
|
|
<&camcc CAM_CC_BPS_AHB_CLK>,
|
|
<&camcc CAM_CC_BPS_AREG_CLK>,
|
|
<&camcc CAM_CC_BPS_AXI_CLK>,
|
|
<&camcc CAM_CC_BPS_CLK>,
|
|
<&camcc CAM_CC_BPS_CLK_SRC>;
|
|
|
|
clock-rates =
|
|
<0 0 0 0 200000000>,
|
|
<0 0 0 0 404000000>,
|
|
<0 0 0 0 480000000>,
|
|
<0 0 0 0 600000000>,
|
|
<0 0 0 0 600000000>;
|
|
clock-cntl-level = "lowsvs", "svs",
|
|
"svs_l1", "nominal", "turbo";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-jpeg {
|
|
compatible = "qcom,cam-jpeg";
|
|
compat-hw-name = "qcom,jpegenc",
|
|
"qcom,jpegdma";
|
|
num-jpeg-enc = <1>;
|
|
num-jpeg-dma = <1>;
|
|
status = "ok";
|
|
};
|
|
|
|
cam_jpeg_enc: qcom,jpegenc@ac4e000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam_jpeg_enc";
|
|
reg-names = "jpege_hw";
|
|
reg = <0xac4e000 0x4000>;
|
|
reg-cam-base = <0x4e000>;
|
|
interrupt-names = "jpeg";
|
|
interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"jpegenc_clk_src",
|
|
"jpegenc_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_JPEG_CLK_SRC>,
|
|
<&camcc CAM_CC_JPEG_CLK>;
|
|
|
|
clock-rates =
|
|
<600000000 0>;
|
|
src-clock-name = "jpegenc_clk_src";
|
|
clock-cntl-level = "nominal";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_jpeg_dma: qcom,jpegdma@0xac52000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam_jpeg_dma";
|
|
reg-names = "jpegdma_hw";
|
|
reg = <0xac52000 0x4000>;
|
|
reg-cam-base = <0x52000>;
|
|
interrupt-names = "jpegdma";
|
|
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"jpegdma_clk_src",
|
|
"jpegdma_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_JPEG_CLK_SRC>,
|
|
<&camcc CAM_CC_JPEG_CLK>;
|
|
|
|
clock-rates =
|
|
<600000000 0>;
|
|
src-clock-name = "jpegdma_clk_src";
|
|
clock-cntl-level = "nominal";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-lrme {
|
|
compatible = "qcom,cam-lrme";
|
|
arch-compat = "lrme";
|
|
status = "ok";
|
|
};
|
|
|
|
cam_lrme: qcom,lrme@ac6b000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,lrme";
|
|
reg-names = "lrme";
|
|
reg = <0xac6b000 0xa00>;
|
|
reg-cam-base = <0x6b000>;
|
|
interrupt-names = "lrme";
|
|
interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
|
|
regulator-names = "camss";
|
|
camss-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"lrme_clk_src",
|
|
"lrme_clk";
|
|
clocks =
|
|
<&camcc CAM_CC_LRME_CLK_SRC>,
|
|
<&camcc CAM_CC_LRME_CLK>;
|
|
clock-rates =
|
|
<200000000 0>,
|
|
<269333333 0>,
|
|
<323200000 0>,
|
|
<404000000 0>,
|
|
<404000000 0>;
|
|
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
|
|
"turbo";
|
|
src-clock-name = "lrme_clk_src";
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,cam-cpas@ac40000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,cam-cpas";
|
|
label = "cpas";
|
|
arch-compat = "cpas_top";
|
|
status = "ok";
|
|
reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr";
|
|
reg = <0xac40000 0x1000>,
|
|
<0xac42000 0x4600>,
|
|
<0x01fc0000 0x40000>;
|
|
reg-cam-base = <0x40000 0x42000 0x0>;
|
|
interrupt-names = "cpas_camnoc";
|
|
interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,cpas-hw-ver = <0x170200>; /* Titan v170 v2.0.0 */
|
|
camnoc-axi-min-ib-bw = <3000000000>;
|
|
regulator-names = "camss-vdd";
|
|
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
|
|
clock-names =
|
|
"gcc_ahb_clk",
|
|
"gcc_axi_clk",
|
|
"soc_ahb_clk",
|
|
"slow_ahb_clk_src",
|
|
"cpas_ahb_clk",
|
|
"camnoc_axi_clk";
|
|
clocks =
|
|
<&gcc GCC_CAMERA_AHB_CLK>,
|
|
<&gcc GCC_CAMERA_AXI_CLK>,
|
|
<&camcc CAM_CC_SOC_AHB_CLK>,
|
|
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
|
|
<&camcc CAM_CC_CPAS_AHB_CLK>,
|
|
<&camcc CAM_CC_CAMNOC_AXI_CLK>;
|
|
src-clock-name = "slow_ahb_clk_src";
|
|
clock-rates =
|
|
<0 0 0 0 0 0>,
|
|
<0 0 0 80000000 0 0>,
|
|
<0 0 0 80000000 0 0>,
|
|
<0 0 0 80000000 0 0>,
|
|
<0 0 0 80000000 0 0>,
|
|
<0 0 0 80000000 0 0>;
|
|
clock-cntl-level = "suspend", "lowsvs", "svs",
|
|
"svs_l1", "nominal", "turbo";
|
|
qcom,msm-bus,name = "cam_ahb";
|
|
qcom,msm-bus,num-cases = <7>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 120000>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
|
|
<MSM_BUS_MASTER_AMPSS_M0
|
|
MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
|
|
vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
|
|
RPMH_REGULATOR_LEVEL_MIN_SVS
|
|
RPMH_REGULATOR_LEVEL_LOW_SVS
|
|
RPMH_REGULATOR_LEVEL_SVS
|
|
RPMH_REGULATOR_LEVEL_SVS_L1
|
|
RPMH_REGULATOR_LEVEL_NOM
|
|
RPMH_REGULATOR_LEVEL_NOM_L1
|
|
RPMH_REGULATOR_LEVEL_NOM_L2
|
|
RPMH_REGULATOR_LEVEL_TURBO
|
|
RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
vdd-corner-ahb-mapping = "suspend",
|
|
"minsvs", "lowsvs", "svs", "svs_l1",
|
|
"nominal", "nominal", "nominal",
|
|
"turbo", "turbo";
|
|
client-id-based;
|
|
client-names =
|
|
"csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0",
|
|
"cci1", "csid0", "csid1", "csid2", "csid3",
|
|
"ife0", "ife1", "ife2", "ife3", "ipe0",
|
|
"cam-cdm-intf0", "cpas-cdm0", "bps0",
|
|
"icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0";
|
|
|
|
camera-bus-nodes {
|
|
level3-nodes {
|
|
level-index = <3>;
|
|
level3_rt0_wr_sum: level3-rt0-wr-sum {
|
|
cell-index = <0>;
|
|
node-name = "level3-rt0-wr-sum";
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
qcom,axi-port-name = "cam_hf_0";
|
|
ib-bw-voting-needed;
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_hf_0_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_HF
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_HF
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_hf_0_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
|
};
|
|
};
|
|
|
|
level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
|
|
cell-index = <1>;
|
|
node-name = "level3-nrt0-rd-wr-sum";
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
qcom,axi-port-name = "cam_sf_0";
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_sf_0_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_SF
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_SF
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_sf_0_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
|
};
|
|
};
|
|
|
|
level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
|
|
cell-index = <2>;
|
|
node-name = "level3-nrt1-rd-wr-sum";
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
qcom,axi-port-name = "cam_sf_icp";
|
|
qcom,axi-port-mnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_sf_icp_mnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_ICP
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_ICP
|
|
MSM_BUS_SLAVE_EBI_CH0 0 0>;
|
|
};
|
|
|
|
qcom,axi-port-camnoc {
|
|
qcom,msm-bus,name =
|
|
"cam_sf_icp_camnoc";
|
|
qcom,msm-bus-vector-dyn-vote;
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<MSM_BUS_MASTER_CAMNOC_ICP_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
|
|
<MSM_BUS_MASTER_CAMNOC_ICP_UNCOMP
|
|
MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
level2-nodes {
|
|
level-index = <2>;
|
|
level2_rt0_wr: level2-rt0-wr {
|
|
cell-index = <3>;
|
|
node-name = "level2-rt0-wr";
|
|
parent-node = <&level3_rt0_wr_sum>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
|
|
};
|
|
|
|
level2_nrt0_rd_wr: level2-nrt0-rd-wr {
|
|
cell-index = <4>;
|
|
node-name = "level2-nrt0-rd-wr";
|
|
parent-node = <&level3_nrt0_rd_wr_sum>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
};
|
|
|
|
level2_nrt1_rd: level2-nrt1-rd {
|
|
cell-index = <5>;
|
|
node-name = "level2-nrt1-rd";
|
|
parent-node = <&level3_nrt1_rd_wr_sum>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
bus-width-factor = <4>;
|
|
};
|
|
};
|
|
|
|
level1-nodes {
|
|
level-index = <1>;
|
|
level1_rt0_wr: level1-rt0-wr {
|
|
cell-index = <6>;
|
|
node-name = "level1-rt0-wr";
|
|
parent-node = <&level2_rt0_wr>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
};
|
|
|
|
level1_rt1_wr: level1-rt1-wr {
|
|
cell-index = <7>;
|
|
node-name = "level1-rt1-wr";
|
|
parent-node = <&level2_rt0_wr>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
};
|
|
|
|
level1_nrt0_wr: level1-nrt0-wr {
|
|
cell-index = <8>;
|
|
node-name = "level1-nrt0-wr";
|
|
parent-node = <&level2_nrt0_rd_wr>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
};
|
|
|
|
level1_nrt0_rd: level1-nrt0-rd {
|
|
cell-index = <9>;
|
|
node-name = "level1-nrt0-rd";
|
|
parent-node = <&level2_nrt0_rd_wr>;
|
|
traffic-merge-type =
|
|
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
|
|
};
|
|
};
|
|
|
|
level0-nodes {
|
|
level-index = <0>;
|
|
|
|
ife0_rdi_all_wr: ife0-rdi-all-wr {
|
|
cell-index = <10>;
|
|
node-name = "ife0-rdi-all-wr";
|
|
client-name = "ife0";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI0
|
|
CAM_CPAS_PATH_DATA_IFE_RDI1
|
|
CAM_CPAS_PATH_DATA_IFE_RDI2
|
|
CAM_CPAS_PATH_DATA_IFE_RDI3>;
|
|
parent-node = <&level1_rt0_wr>;
|
|
};
|
|
|
|
ife1_rdi_all_wr: ife1-rdi-all-wr {
|
|
cell-index = <11>;
|
|
node-name = "ife1-rdi-all-wr";
|
|
client-name = "ife1";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI0
|
|
CAM_CPAS_PATH_DATA_IFE_RDI1
|
|
CAM_CPAS_PATH_DATA_IFE_RDI2
|
|
CAM_CPAS_PATH_DATA_IFE_RDI3>;
|
|
parent-node = <&level1_rt0_wr>;
|
|
};
|
|
|
|
ife2_rdi_all_wr: ife2-rdi-all-wr {
|
|
cell-index = <12>;
|
|
node-name = "ife2-rdi-all-wr";
|
|
client-name = "ife2";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI0
|
|
CAM_CPAS_PATH_DATA_IFE_RDI1
|
|
CAM_CPAS_PATH_DATA_IFE_RDI2
|
|
CAM_CPAS_PATH_DATA_IFE_RDI3>;
|
|
parent-node = <&level1_rt1_wr>;
|
|
};
|
|
|
|
ife3_rdi_all_wr: ife3-rdi-all-wr {
|
|
cell-index = <13>;
|
|
node-name = "ife3-rdi-all-wr";
|
|
client-name = "ife3";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_RDI0
|
|
CAM_CPAS_PATH_DATA_IFE_RDI1
|
|
CAM_CPAS_PATH_DATA_IFE_RDI2
|
|
CAM_CPAS_PATH_DATA_IFE_RDI3>;
|
|
parent-node = <&level1_rt1_wr>;
|
|
};
|
|
|
|
ife0_pixelall_wr: ife0-pixelall-wr {
|
|
cell-index = <14>;
|
|
node-name = "ife0-pixelall-wr";
|
|
client-name = "ife0";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_LINEAR
|
|
CAM_CPAS_PATH_DATA_IFE_PDAF
|
|
CAM_CPAS_PATH_DATA_IFE_VID
|
|
CAM_CPAS_PATH_DATA_IFE_DISP
|
|
CAM_CPAS_PATH_DATA_IFE_STATS
|
|
CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
|
|
parent-node = <&level1_rt0_wr>;
|
|
};
|
|
|
|
ife1_pixelall_wr: ife1-pixelall-wr {
|
|
cell-index = <15>;
|
|
node-name = "ife1-pixelall-wr";
|
|
client-name = "ife1";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_LINEAR
|
|
CAM_CPAS_PATH_DATA_IFE_PDAF
|
|
CAM_CPAS_PATH_DATA_IFE_VID
|
|
CAM_CPAS_PATH_DATA_IFE_DISP
|
|
CAM_CPAS_PATH_DATA_IFE_STATS
|
|
CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
|
|
parent-node = <&level1_rt0_wr>;
|
|
};
|
|
|
|
ife2_pixelall_wr: ife2-pixelall-wr {
|
|
cell-index = <16>;
|
|
node-name = "ife2-pixelall-wr";
|
|
client-name = "ife2";
|
|
traffic-data =
|
|
<CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IFE_LINEAR
|
|
CAM_CPAS_PATH_DATA_IFE_PDAF
|
|
CAM_CPAS_PATH_DATA_IFE_VID
|
|
CAM_CPAS_PATH_DATA_IFE_DISP
|
|
CAM_CPAS_PATH_DATA_IFE_STATS
|
|
CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
|
|
parent-node = <&level1_rt1_wr>;
|
|
};
|
|
|
|
bps0_all_wr: bps0-all-wr {
|
|
cell-index = <17>;
|
|
node-name = "bps0-all-wr";
|
|
client-name = "bps0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
parent-node = <&level1_nrt0_wr>;
|
|
};
|
|
|
|
bps0_all_rd: bps0-all-rd {
|
|
cell-index = <18>;
|
|
node-name = "bps0-all-rd";
|
|
client-name = "bps0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
parent-node = <&level1_nrt0_rd>;
|
|
};
|
|
|
|
ipe0_all_rd: ipe0-all-rd {
|
|
cell-index = <19>;
|
|
node-name = "ipe0-all-rd";
|
|
client-name = "ipe0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IPE_RD_IN
|
|
CAM_CPAS_PATH_DATA_IPE_RD_REF>;
|
|
parent-node = <&level1_nrt0_rd>;
|
|
};
|
|
|
|
ipe0_all_wr: ipe0-all-wr {
|
|
cell-index = <20>;
|
|
node-name = "ipe0-all-wr";
|
|
client-name = "ipe0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
constituent-paths =
|
|
<CAM_CPAS_PATH_DATA_IPE_WR_VID
|
|
CAM_CPAS_PATH_DATA_IPE_WR_DISP
|
|
CAM_CPAS_PATH_DATA_IPE_WR_REF>;
|
|
parent-node = <&level1_nrt0_wr>;
|
|
};
|
|
|
|
lrme0_all_rd: lrme0-all-rd {
|
|
cell-index = <21>;
|
|
node-name = "lrme0-all-rd";
|
|
client-name = "lrmecpas0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
parent-node = <&level1_nrt0_rd>;
|
|
};
|
|
|
|
lrme0_all_wr: lrme0-all-wr {
|
|
cell-index = <22>;
|
|
node-name = "lrme0-all-wr";
|
|
client-name = "lrmecpas0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
parent-node = <&level1_nrt0_wr>;
|
|
};
|
|
|
|
cpas_cdm0_all_rd: cpas-cdm0-all-rd {
|
|
cell-index = <23>;
|
|
node-name = "cpas-cdm0-all-rd";
|
|
client-name = "cpas-cdm0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
parent-node = <&level2_nrt0_rd_wr>;
|
|
};
|
|
|
|
jpeg0_all_wr: jpeg0-all-wr {
|
|
cell-index = <24>;
|
|
node-name = "jpeg0-all-wr";
|
|
client-name = "jpeg-enc0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_WRITE>;
|
|
parent-node = <&level2_nrt0_rd_wr>;
|
|
};
|
|
|
|
jpeg0_all_rd: jpeg0-all-rd {
|
|
cell-index = <25>;
|
|
node-name = "jpeg0-all-rd";
|
|
client-name = "jpeg-enc0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
parent-node = <&level2_nrt0_rd_wr>;
|
|
};
|
|
|
|
icp0_all_rd: icp0-all-rd {
|
|
cell-index = <26>;
|
|
node-name = "icp0-all-rd";
|
|
client-name = "icp0";
|
|
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
|
|
traffic-transaction-type =
|
|
<CAM_CPAS_TRANSACTION_READ>;
|
|
parent-node = <&level2_nrt1_rd>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|