125 lines
3.8 KiB
Python
Executable File
125 lines
3.8 KiB
Python
Executable File
# Copyright (c) 2015, 2017, 2020 The Linux Foundation. All rights reserved.
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# Copyright (c) 2022, 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 and
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# only version 2 as published by the Free Software Foundation.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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import struct
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import os
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from print_out import print_out_str
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from ramparse import VERSION
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dcc_register_list = [
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'DCC_HW_VERSION',
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'DCC_HW_INFO',
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'DCC_CGC_CFG',
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'DCC_LL',
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'DCC_RAM_CFG',
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'DCC_CFG',
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'DCC_SW_CTL',
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'DCC_STATUS',
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'DCC_FETCH_ADDR',
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'DCC_SRAM_ADDR',
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'DCC_INT_ENABLE',
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'DCC_INT_STATUS',
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'DCC_QSB_CFG'
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]
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# DCC regs hash table
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dcc_regs = {}
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class DccRegDump():
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def __init__(self, start, end):
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self.start_addr = start
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self.end_addr = end
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def parse_all_regs(self, ram_dump):
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num_reg = len(dcc_register_list)
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if (self.start_addr + 4 * num_reg) > self.end_addr:
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return False
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for reg in dcc_register_list:
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dcc_regs[reg] = ram_dump.read_u32(self.start_addr, False)
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self.start_addr += 4
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return True
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def dump_all_regs(self, ram_dump):
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outfile = ram_dump.open_file('dcc_regs.txt')
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outfile.write('DCC registers:\n')
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for reg in dcc_register_list:
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outfile.write('{0} : 0x{1:08x}\n'.format(reg, dcc_regs[reg]))
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outfile.close()
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class DccSramDump():
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def __init__(self, start, end, ram_dump):
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self.start_addr = start
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self.end_addr = end
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self.bin_dir = None
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if ram_dump.ram_addr is None:
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self.bin_dir = ram_dump.autodump
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else:
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self.bin_dir = ram_dump.ram_addr
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self.bin_dir="\\".join(self.bin_dir[0][0].split('\\')[:-1])
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self.dcc_bin = os.path.join(self.bin_dir, 'DCC_SRAM.BIN')
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if os.path.isfile(self.dcc_bin):
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self.start_addr = 0x6000
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self.end_addr = 0x8000
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def dump_sram_img(self, ram_dump):
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if self.start_addr >= self.end_addr:
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return False
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rsz = self.end_addr - self.start_addr
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if os.path.isfile(self.dcc_bin):
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return self.dump_sram_img_bin(ram_dump, self.dcc_bin)
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if 'DCC_HW_INFO' not in dcc_regs \
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or dcc_regs['DCC_HW_INFO'] == 0:
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print_out_str('DCC HW Info missing! Skipping sram dump...')
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return False
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if dcc_regs['DCC_CFG'] & 0x1:
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print_out_str('DCC is configured in CRC mode. Skipping sram dump ...')
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return False
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if dcc_regs['DCC_RAM_CFG'] == 0:
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print_out_str('No config found in DCC SRAM. Skipping sram dump ...')
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return False
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file_path = os.path.join(ram_dump.outdir, 'sram.bin')
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sramfile = open(file_path, 'wb')
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if not os.path.isfile(file_path):
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print_out_str("sram.bin file creation failed")
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return FALSE
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for i in range(0, rsz):
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val = ram_dump.read_byte(self.start_addr + i, False)
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sramfile.write(struct.pack('<B', val))
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sramfile.close()
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return True
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def dump_sram_img_bin(self, ram_dump, dcc_bin):
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if self.start_addr >= self.end_addr:
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return False
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f = open(dcc_bin, 'rb')
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f.seek(self.start_addr, 1)
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bin_data=f.read()
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sramfile = ram_dump.open_file('sram.bin')
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sramfile.write(bin_data)
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f.close()
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sramfile.close()
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return True
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