# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hw-fence.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: HW Fence

maintainers:
  - Grace An <quic_gracan@quicinc.com>
  - Kalyan Thota <quic_kalyant@quicinc.com>

description: |
  HW Fence implements Linux APIs to initialize, deinitialize, register-for-signal, and
  overall manage the hw-fences, for hw-to-hw communcation between hw cores.

properties:
  compatible:
    const: qcom,msm-hw-fence

  qcom,ipcc-reg:
    description: Registers ranges for ipcc registers.

  qcom,hw-fence-table-entries:
    description: A u32 indicating number of entries for the hw-fence table
    $ref: /schemas/types.yaml#/definitions/uint32

  qcom,hw-fence-queue-entries:
    description: A u32 indicating default number of entries for the Queues
    $ref: /schemas/types.yaml#/definitions/uint32

  hw_fence@0:
    description: Doorbell configuration to communicate with secondary vm through hypervisor.
    type: object
    properties:
      compatible:
        const: qcom,msm-hw-fence-db
      qcom,master: true
      gunyah-label:
        $ref: /schemas/types.yaml#/definitions/uint32
      peer-name:
        $ref: /schemas/types.yaml#/definitions/uint32

  hw_fence@1:
    description: |
      Carved-out memory-mapping region, to be used for mapping of global tables and
      queues used by the hw-fence driver and fence controller running in secondary vm.
    type: object
    properties:
      compatible:
        const: qcom,msm-hw-fence-mem
      qcom,master: true
      gunyah-label:
        $ref: /schemas/types.yaml#/definitions/uint32
      peer-name:
        $ref: /schemas/types.yaml#/definitions/uint32
      shared-buffer:
        $ref: /schemas/types.yaml#/definitions/phandle

  qcom,hw-fence-ipc-ver:
    description: |
      A u32 indicating ipc version. If not provided in device-tree, this is read from
      the registers.
    $ref: /schemas/types.yaml#/definitions/uint32

  soccp_controller:
    description: phandle for the soccp controller.
    $ref: /schemas/types.yaml#/definitions/phandle

  interrupts:
    description: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP).

  interrupt-controller: true
    description: Mark the device node as an interrupt controller.

  '#interrupt-cells':
    description: Should be one. The first cell is interrupt number.
    const: 1

  iommus:
    description: Specifies the SID's used by this context bank.

patternProperties:
  "qcom,hw\-fence\-client\-type\-+\w":
    description: |
      A list of four u32 describing client properties that
      override default values specified by the driver for some clients.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
    - description: number of clients for given type
    - enum:
      - 1
      - 2
      description: 1 (Tx) or 2 (Rx and Tx)
    - description: number of entries per client queue
    - enum:
      - 0
      - 1
      description: |
        bool indicating whether tx queue wr_idx update is skipped within hw fence
        driver and hfi_header->tx_wm is used instead

  "qcom,hw\-fence\-client\-type\-+\w+\-extra":
    description: |
      A list of four u32 indicating extra client queue properties.Later u32 values do not need to
      be provided to provide values for earlier u32 values.
    minItems: 1
    maxItems: 4
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
    - description: size of padding between queue table header and first queue header in bytes
    - description: size of padding between queue header(s) and first queue payload in bytes
    - description: start_index for TxQ rd_wr_index
    - enum:
      - 0
      - 1
      description: |
        bool indicating whether TxQ rd_wr_idx indexes by payloads instead of
        default dwords

required:
  - compatible
  - qcom,ipcc-reg
  - qcom,hw-fence-table-entries
  - qcom,hw-fence-queue-entries
  - hw_fence@1

if:
  required:
    - soccp-controller
then:
  required:
    - interrupts
    - interrupt-controller
    - '#interrupt-cells'
    - iommus
    properties:
      hw_fence@0: false
else:
  required:
    - hw_fence@0
  properties:
    - interrupts: false
    - interrupt-controller: false
    - '#interrupt-cells': false
    - iommus: false

additionalProperties: false

examples:
  - |
    msm_hw_fence: qcom,hw-fence {
       compatible = "qcom,msm-hw-fence";
       status = "ok";

       qcom,ipcc-reg = <0x400000 0x100000>;
       qcom,hw-fence-table-entries = <8192>;
       qcom,hw-fence-queue-entries = <800>;

       # time register
       qcom,qtime-reg = <0xC221000 0x1000>;

       # ipc version
       qcom,hw-fence-ipc-ver = <0x20003>;

       # client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx
       qcom,hw-fence-client-type-dpu = <4 2 128 0>;
       qcom,hw-fence-client-type-ife2 = <3 1 64 1>;

       # extra client queue properties
       qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;

       # haven doorbell specific
       hw_fence@0 {
         compatible = "qcom,msm-hw-fence-db";
         qcom,master;
         gunyah-label = <6>;
         peer-name = <3>;
       };

       # haven io-mem specific
       hw_fence@1 {
         compatible = "qcom,msm-hw-fence-mem";
         qcom,master;
         gunyah-label = <5>;
         peer-name = <3>;
         shared-buffer = <&hwfence_shbuf>;
       };
    };

  - |
    msm_hw_fence: qcom,hw-fence {
      compatible = "qcom,msm-hw-fence";
      status = "ok";

      # SOCCP properties
      interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-controller;
      #interrupt-cells = <1>;
      iommus = <&apps_smmu 0x562 0x1>;
      soccp_controller = <&soccp_pas>;

      qcom,ipcc-reg = <0x400000 0x100000>;
      qcom,hw-fence-table-entries = <8192>;
      qcom,hw-fence-queue-entries = <800>;

      # time register
      qcom,qtime-reg = <0xC221000 0x1000>;

      # ipc version
      qcom,hw-fence-ipc-ver = <0x20003>;

      # base client queue properties
      qcom,hw-fence-client-type-dpu = <4 2 128 0>;
      qcom,hw-fence-client-type-ife2 = <3 1 64 1>;

      # extra client queue properties
      qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;

      # haven io-mem specific
      hw_fence@1 {
        compatible = "qcom,msm-hw-fence-mem";
        qcom,master;
        shared-buffer = <&hwfence_shbuf>;
      };
    };
...