sm8750: init kernel modules repo

qcom/opensource/audio-kernel/include/bindings/audio-codec-port-types.h

@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */
+/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.*/
+
+#ifndef __AUDIO_CODEC_PORT_TYPES_H
+#define __AUDIO_CODEC_PORT_TYPES_H
+
+#define OFFSET1_VAL0 0
+#define OFFSET1_VAL1 1
+#define OFFSET1_VAL2 2
+#define OFFSET1_VAL3 3
+#define OFFSET1_VAL4 4
+#define OFFSET1_VAL5 5
+#define OFFSET1_VAL6 6
+#define OFFSET1_VAL7 7
+#define OFFSET1_VAL8 8
+#define OFFSET1_VAL9 9
+#define OFFSET1_VAL10 10
+#define OFFSET1_VAL11 11
+#define OFFSET1_VAL12 12
+#define OFFSET1_VAL13 13
+#define OFFSET1_VAL14 14
+#define OFFSET1_VAL15 15
+#define OFFSET1_VAL16 16
+#define OFFSET1_VAL17 17
+#define OFFSET1_VAL18 18
+#define OFFSET1_VAL19 19
+#define OFFSET1_VAL20 20
+#define OFFSET1_VAL21 21
+#define OFFSET1_VAL22 22
+#define OFFSET1_VAL23 23
+#define OFFSET1_VAL24 24
+#define OFFSET1_VAL25 25
+
+#define LANE0 0
+#define LANE1 1
+#define LANE2 2
+
+#define SPKR_L 1
+#define SPKR_L_COMP 2
+#define SPKR_L_BOOST 3
+#define SPKR_R 4
+#define SPKR_R_COMP 5
+#define SPKR_R_BOOST 6
+#define PBR 7
+#define SPKR_HAPT 8
+#define OCPM 9
+#define SPKR_L_VI 10
+#define SPKR_R_VI 11
+#define SPKR_IPCM 12
+#define CPS 13
+#define HPH_L 14
+#define HPH_R 15
+#define COMP_L 16
+#define COMP_R 17
+#define CLSH 18
+#define LO 19
+#define DSD_L 20
+#define DSD_R 21
+#define PCM_OUT1 22
+#define GPPO 23
+#define HAPT 24
+#define HIFI 25
+#define HPTH 26
+#define CMPT 27
+#define IPCM 28
+#define MBHC 29
+#define ADC1 30
+#define ADC2 31
+#define ADC3 32
+#define ADC4 33
+#define DMIC0 34
+#define DMIC1 35
+#define DMIC2 36
+#define DMIC3 37
+#define DMIC4 38
+#define DMIC5 39
+#define DMIC6 40
+#define DMIC7 41
+#define DMIC8 42
+#define DMIC9 43
+#define DMIC10 44
+#define SWRM_TX_PCM_OUT 45
+#define SWRM_TX1_CH1 46
+#define SWRM_TX1_CH2 47
+#define SWRM_TX1_CH3 48
+#define SWRM_TX1_CH4 49
+#define SWRM_TX2_CH1 50
+#define SWRM_TX2_CH2 51
+#define SWRM_TX2_CH3 52
+#define SWRM_TX2_CH4 53
+#define SWRM_TX3_CH1 54
+#define SWRM_TX3_CH2 55
+#define SWRM_TX3_CH3 56
+#define SWRM_TX3_CH4 57
+#define SWRM_TX_PCM_IN 58
+#define HIFI_PCM_L 59
+#define HIFI_PCM_R 60
+
+// BT SWR PORT defines
+#define BT_AUDIO_RX1 101
+#define BT_AUDIO_TX1 102
+#define BT_AUDIO_RX2 103
+#define BT_AUDIO_TX2 104
+#define BT_AUDIO_RX3 105
+#define BT_AUDIO_TX3 106
+#define FM_AUDIO_TX1 107
+
+#endif /* __AUDIO_CODEC_PORT_TYPES_H */

qcom/opensource/audio-kernel/include/bindings/qcom,audio-ext-clk.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
+/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.*/
+
+#ifndef __AUDIO_EXT_CLK_H
+#define __AUDIO_EXT_CLK_H
+
+/* Audio External Clocks */
+#define AUDIO_PMI_CLK                 0
+#define AUDIO_PMIC_LNBB_CLK           1
+#define AUDIO_LPASS_MCLK              2  /* VA CORE CLK */
+#define AUDIO_LPASS_MCLK_2            3  /* WSA1 CORE CLK */
+#define AUDIO_LPASS_MCLK_3            4  /* WSA1 NPL CLK */
+#define AUDIO_LPASS_MCLK_4            5  /* RX CORE CLK */
+#define AUDIO_LPASS_MCLK_5            6  /* RX NPL CLK */
+#define AUDIO_LPASS_MCLK_6            7  /* TX CORE CLK */
+#define AUDIO_LPASS_MCLK_7            8  /* TX NPL CLK */
+#define AUDIO_LPASS_CORE_HW_VOTE      9
+#define AUDIO_LPASS_MCLK_8            10 /* VA NPL CLK */
+#define AUDIO_LPASS_AUDIO_HW_VOTE     11
+#define AUDIO_LPASS_MCLK_9            12 /* WSA2 CORE CLK */
+#define AUDIO_LPASS_MCLK_10           13 /* RX_TX CORE CLK */
+#define AUDIO_LPASS_MCLK_11           14 /* WSA_TX CORE CLK */
+#define AUDIO_LPASS_MCLK_12           15 /* WSA2_TX CORE CLK */
+#define AUDIO_LPASS_MCLK_13           16 /* RX_MCLK2 2X CLK */
+#define AUDIO_LPASS_MCLK_14           17 /* HW SEQUNCER MCLK */
+#define AUDIO_LPASS_MCLK_15           18 /* BT_SWR CLK */
+#define AUDIO_LPASS_MCLK_16           19 /* BT_SWR 2X CLK */
+#endif

qcom/opensource/audio-kernel/include/bindings/qcom,bolero-clk-rsc.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __BOLERO_CODEC_CLK_RSC_H
+#define __BOLERO_CODEC_CLK_RSC_H
+
+/* Bolero clock types */
+#define TX_CORE_CLK	0
+#define RX_CORE_CLK	1
+#define WSA_CORE_CLK	2
+#define VA_CORE_CLK	3
+#define TX_NPL_CLK	4
+#define RX_NPL_CLK	5
+#define WSA_NPL_CLK	6
+#define VA_NPL_CLK	7
+#define MAX_CLK	8
+
+#endif /* __BOLERO_CODEC_CLK_RSC_H */

qcom/opensource/audio-kernel/include/bindings/qcom,gpr.h

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
+#ifndef __DT_BINDINGS_QCOM_GPR_H
+#define __DT_BINDINGS_QCOM_GPR_H
+
+/* Domain IDs */
+#define GPR_DOMAIN_SIM		0x0
+#define GPR_DOMAIN_MODEM	0x1
+#define GPR_DOMAIN_ADSP		0x2
+#define GPR_DOMAIN_APPS		0x3
+#define GPR_DOMAIN_SDSP		0x4
+#define GPR_DOMAIN_CDSP		0x5
+#define GPR_DOMAIN_MAX		0x6
+
+/* ADSP service IDs */
+#define GPR_SVC_ADSP_CORE	0x3
+#define GPR_SVC_AFE		0x4
+#define GPR_SVC_VSM		0x5
+#define GPR_SVC_VPM		0x6
+#define GPR_SVC_ASM		0x7
+#define GPR_SVC_ADM		0x8
+#define GPR_SVC_ADSP_MVM	0x09
+#define GPR_SVC_ADSP_CVS	0x0A
+#define GPR_SVC_ADSP_CVP	0x0B
+#define GPR_SVC_USM		0x0C
+#define GPR_SVC_LSM		0x0D
+#define GPR_SVC_VIDC		0x16
+#define GPR_SVC_MAX		0x17
+
+#endif /* __DT_BINDINGS_QCOM_GPR_H */
+

qcom/opensource/audio-kernel/include/bindings/qcom,lpass-cdc-clk-rsc.h

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __LPASS_CDC_CLK_RSC_H
+#define __LPASS_CDC_CLK_RSC_H
+
+/* LPASS codec clock types */
+#define TX_CORE_CLK      0
+#define RX_CORE_CLK      1
+#define WSA_CORE_CLK     2
+#define VA_CORE_CLK      3
+#define WSA2_CORE_CLK    4
+#define RX_TX_CORE_CLK   5
+#define WSA_TX_CORE_CLK  6
+#define WSA2_TX_CORE_CLK 7
+#define MAX_CLK          8
+
+#endif /* __LPASS_CDC_CLK_RSC_H */