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sm8750: init kernel modules repo

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This commit is contained in:
Sascha Nesterovic
2025-08-11 12:21:01 +02:00
parent 2681143b87
commit facad83b01
8851 changed files with 6894561 additions and 0 deletions
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29
qcom/opensource/audio-kernel/include/asoc/bolero-slave-internal.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* from Slave to bolero events */
enum {
SLV_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
SLV_BOLERO_EVT_IMPED_TRUE, /* for imped true */
SLV_BOLERO_EVT_IMPED_FALSE, /* for imped false */
SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
SLV_BOLERO_EVT_BCS_CLK_OFF,
SLV_BOLERO_EVT_RX_PA_GAIN_UPDATE,
SLV_BOLERO_EVT_HPHL_HD2_ENABLE, /* to enable hd2 config for hphl */
SLV_BOLERO_EVT_HPHR_HD2_ENABLE, /* to enable hd2 config for hphr */
};
/* from bolero to SLV events */
enum {
BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR = 1,
BOLERO_SLV_EVT_PA_OFF_PRE_SSR,
BOLERO_SLV_EVT_SSR_DOWN,
BOLERO_SLV_EVT_SSR_UP,
BOLERO_SLV_EVT_PA_ON_POST_FSCLK,
BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB,
BOLERO_SLV_EVT_CLK_NOTIFY,
BOLERO_SLV_EVT_RX_MACRO_PA_ON,
};

553
qcom/opensource/audio-kernel/include/asoc/core.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_TABLA_CORE_H__
#define __MFD_TABLA_CORE_H__
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include "pdata.h"
#define WCD9XXX_MAX_IRQ_REGS 4
#define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8)
#define WCD9XXX_SLIM_NUM_PORT_REG 3
#define TABLA_VERSION_1_0 0
#define TABLA_VERSION_1_1 1
#define TABLA_VERSION_2_0 2
#define TABLA_IS_1_X(ver) \
(((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0)
#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)
#define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"
#define SITAR_VERSION_1P0 0
#define SITAR_VERSION_1P1 1
#define SITAR_IS_1P0(ver) \
((ver == SITAR_VERSION_1P0) ? 1 : 0)
#define SITAR_IS_1P1(ver) \
((ver == SITAR_VERSION_1P1) ? 1 : 0)
#define TAIKO_VERSION_1_0 1
#define TAIKO_IS_1_0(ver) \
((ver == TAIKO_VERSION_1_0) ? 1 : 0)
#define TAPAN_VERSION_1_0 0
#define TAPAN_IS_1_0(ver) \
((ver == TAPAN_VERSION_1_0) ? 1 : 0)
#define TOMTOM_VERSION_1_0 1
#define TOMTOM_IS_1_0(ver) \
((ver == TOMTOM_VERSION_1_0) ? 1 : 0)
#define TASHA_VERSION_1_0 0
#define TASHA_VERSION_1_1 1
#define TASHA_VERSION_2_0 2
#define TASHA_IS_1_0(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_1_0) ? 1 : 0) : 0)
#define TASHA_IS_1_1(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_1_1) ? 1 : 0) : 0)
#define TASHA_IS_2_0(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_2_0) ? 1 : 0) : 0)
/*
* As fine version info cannot be retrieved before tavil probe.
* Define three coarse versions for possible future use before tavil probe.
*/
#define TAVIL_VERSION_1_0 0
#define TAVIL_VERSION_1_1 1
#define TAVIL_VERSION_WCD9340_1_0 2
#define TAVIL_VERSION_WCD9341_1_0 3
#define TAVIL_VERSION_WCD9340_1_1 4
#define TAVIL_VERSION_WCD9341_1_1 5
#define TAVIL_IS_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_1_0 || \
wcd->version == TAVIL_VERSION_WCD9340_1_0 || \
wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_1_1 || \
wcd->version == TAVIL_VERSION_WCD9340_1_1 || \
wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9340_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9340_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9341_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9340_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9340_1_1) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9341_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
#define IS_CODEC_TYPE(wcd, wcdtype) \
((wcd->type == wcdtype) ? true : false)
#define IS_CODEC_VERSION(wcd, wcdversion) \
((wcd->version == wcdversion) ? true : false)
enum {
CDC_V_1_0,
CDC_V_1_1,
CDC_V_2_0,
};
enum codec_variant {
WCD9XXX,
WCD9330,
WCD9335,
WCD9326,
WCD934X,
};
enum wcd9xxx_slim_slave_addr_type {
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0,
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1,
};
enum wcd9xxx_pm_state {
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE,
WCD9XXX_PM_ASLEEP,
};
enum {
WCD9XXX_INTR_STATUS_BASE = 0,
WCD9XXX_INTR_CLEAR_BASE,
WCD9XXX_INTR_MASK_BASE,
WCD9XXX_INTR_LEVEL_BASE,
WCD9XXX_INTR_CLR_COMMIT,
WCD9XXX_INTR_REG_MAX,
};
enum wcd9xxx_intf_status {
WCD9XXX_INTERFACE_TYPE_PROBING,
WCD9XXX_INTERFACE_TYPE_SLIMBUS,
WCD9XXX_INTERFACE_TYPE_I2C,
};
enum {
/* INTR_REG 0 */
WCD9XXX_IRQ_SLIMBUS = 0,
WCD9XXX_IRQ_MBHC_REMOVAL,
WCD9XXX_IRQ_MBHC_SHORT_TERM,
WCD9XXX_IRQ_MBHC_PRESS,
WCD9XXX_IRQ_MBHC_RELEASE,
WCD9XXX_IRQ_MBHC_POTENTIAL,
WCD9XXX_IRQ_MBHC_INSERTION,
WCD9XXX_IRQ_BG_PRECHARGE,
/* INTR_REG 1 */
WCD9XXX_IRQ_PA1_STARTUP,
WCD9XXX_IRQ_PA2_STARTUP,
WCD9XXX_IRQ_PA3_STARTUP,
WCD9XXX_IRQ_PA4_STARTUP,
WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
WCD9XXX_IRQ_PA5_STARTUP,
WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
/* INTR_REG 2 */
WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_L_PA_STARTUP,
WCD9XXX_IRQ_HPH_R_PA_STARTUP,
WCD9320_IRQ_EAR_PA_STARTUP,
WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_1,
WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS,
WCD9330_IRQ_MBHC_JACK_SWITCH,
/* INTR_REG 3 */
WCD9XXX_IRQ_MAD_AUDIO,
WCD9XXX_IRQ_MAD_ULTRASOUND,
WCD9XXX_IRQ_MAD_BEACON,
WCD9XXX_IRQ_SPEAKER_CLIPPING,
WCD9320_IRQ_MBHC_JACK_SWITCH,
WCD9306_NUM_IRQS,
WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS,
WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
WCD9XXX_NUM_IRQS,
/* WCD9330 INTR1_REG 3*/
WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO,
WCD9330_IRQ_MAD_AUDIO,
WCD9330_IRQ_MAD_ULTRASOUND,
WCD9330_IRQ_MAD_BEACON,
WCD9330_IRQ_SPEAKER1_CLIPPING,
WCD9330_IRQ_SPEAKER2_CLIPPING,
WCD9330_IRQ_VBAT_MONITOR_ATTACK,
WCD9330_IRQ_VBAT_MONITOR_RELEASE,
WCD9330_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS,
};
enum {
TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
TAPAN_NUM_IRQS = WCD9306_NUM_IRQS,
TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS,
};
struct intr_data {
int intr_num;
bool clear_first;
};
struct wcd9xxx_core_resource {
struct mutex irq_lock;
struct mutex nested_irq_lock;
enum wcd9xxx_pm_state pm_state;
struct mutex pm_lock;
/* pm_wq notifies change of pm_state */
wait_queue_head_t pm_wq;
struct pm_qos_request pm_qos_req;
int wlock_holders;
/* holds the table of interrupts per codec */
const struct intr_data *intr_table;
int intr_table_size;
unsigned int irq_base;
unsigned int irq;
u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS];
u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS];
bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
int num_irqs;
int num_irq_regs;
u16 intr_reg[WCD9XXX_INTR_REG_MAX];
struct regmap *wcd_core_regmap;
/* Pointer to parent container data structure */
void *parent;
struct device *dev;
struct irq_domain *domain;
};
/*
* data structure for Slimbus and I2S channel.
* Some of fields are only used in smilbus mode
*/
struct wcd9xxx_ch {
u32 sph; /* share channel handle - slimbus only */
u32 ch_num; /*
* vitrual channel number, such as 128 -144.
* apply for slimbus only
*/
u16 ch_h; /* chanel handle - slimbus only */
u16 port; /*
* tabla port for RX and TX
* such as 0-9 for TX and 10 -16 for RX
* apply for both i2s and slimbus
*/
u16 shift; /*
* shift bit for RX and TX
* apply for both i2s and slimbus
*/
struct list_head list; /*
* channel link list
* apply for both i2s and slimbus
*/
};
struct wcd9xxx_codec_dai_data {
u32 rate; /* sample rate */
u32 bit_width; /* sit width 16,24,32 */
struct list_head wcd9xxx_ch_list; /* channel list */
u16 grph; /* slimbus group handle */
unsigned long ch_mask;
wait_queue_head_t dai_wait;
bool bus_down_in_recovery;
};
#define WCD9XXX_CH(xport, xshift) \
{.port = xport, .shift = xshift}
enum wcd9xxx_chipid_major {
TABLA_MAJOR = cpu_to_le16(0x100),
SITAR_MAJOR = cpu_to_le16(0x101),
TAIKO_MAJOR = cpu_to_le16(0x102),
TAPAN_MAJOR = cpu_to_le16(0x103),
TOMTOM_MAJOR = cpu_to_le16(0x105),
TASHA_MAJOR = cpu_to_le16(0x0),
TASHA2P0_MAJOR = cpu_to_le16(0x107),
TAVIL_MAJOR = cpu_to_le16(0x108),
};
enum codec_power_states {
WCD_REGION_POWER_COLLAPSE_REMOVE,
WCD_REGION_POWER_COLLAPSE_BEGIN,
WCD_REGION_POWER_DOWN,
};
enum wcd_power_regions {
WCD9XXX_DIG_CORE_REGION_1,
WCD9XXX_MAX_PWR_REGIONS,
};
struct wcd9xxx_codec_type {
u16 id_major;
u16 id_minor;
struct mfd_cell *dev;
int size;
int num_irqs;
int version; /* -1 to retrieve version from chip version register */
enum wcd9xxx_slim_slave_addr_type slim_slave_type;
u16 i2c_chip_status;
const struct intr_data *intr_tbl;
int intr_tbl_size;
u16 intr_reg[WCD9XXX_INTR_REG_MAX];
};
struct wcd9xxx_power_region {
enum codec_power_states power_state;
u16 pwr_collapse_reg_min;
u16 pwr_collapse_reg_max;
};
struct wcd9xxx {
struct device *dev;
struct slim_device *slim;
struct slim_device *slim_slave;
struct mutex io_lock;
struct mutex xfer_lock;
struct mutex reset_lock;
u8 version;
int reset_gpio;
struct device_node *wcd_rst_np;
int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *dest, bool interface_reg);
int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src, bool interface_reg);
int (*multi_reg_write)(struct wcd9xxx *wcd9xxx, const void *data,
size_t count);
int (*dev_down)(struct wcd9xxx *wcd9xxx);
int (*post_reset)(struct wcd9xxx *wcd9xxx);
void *ssr_priv;
bool dev_up;
u32 num_of_supplies;
struct regulator_bulk_data *supplies;
struct wcd9xxx_core_resource core_res;
u16 id_minor;
u16 id_major;
/* Slimbus or I2S port */
u32 num_rx_port;
u32 num_tx_port;
struct wcd9xxx_ch *rx_chs;
struct wcd9xxx_ch *tx_chs;
u32 mclk_rate;
enum codec_variant type;
struct regmap *regmap;
struct wcd9xxx_codec_type *codec_type;
bool prev_pg_valid;
u8 prev_pg;
u8 avoid_cdc_rstlow;
struct wcd9xxx_power_region *wcd9xxx_pwr[WCD9XXX_MAX_PWR_REGIONS];
};
struct wcd9xxx_reg_val {
unsigned short reg; /* register address */
u8 *buf; /* buffer to be written to reg. addr */
int bytes; /* number of bytes to be written */
};
#ifdef CONFIG_WCD9XXX_CODEC_CORE
int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val);
int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src);
int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
u32 bw_ops, bool commit);
int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states,
enum wcd_power_regions);
int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
enum wcd_power_regions);
int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg);
int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_reg_val *bulk_reg,
unsigned int size, bool interface);
int wcd9xxx_vote_ondemand_regulator(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_pdata *pdata,
const char *supply_name,
bool enable);
extern int wcd9xxx_core_res_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
int num_irqs, int num_irq_regs, struct regmap *wcd_regmap);
extern void wcd9xxx_core_res_deinit(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_core_res_suspend(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
pm_message_t pmesg);
extern int wcd9xxx_core_res_resume(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_core_irq_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
unsigned int irq,
unsigned int irq_base);
extern enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
extern void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status);
extern enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
enum wcd9xxx_pm_state o,
enum wcd9xxx_pm_state n);
static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
}
int wcd9xxx_init(void);
void wcd9xxx_exit(void);
#else
static inline int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg)
{
return 0;
}
static inline int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val)
{
return 0;
}
static inline int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la)
{
return 0;
}
static inline int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src)
{
return 0;
}
static inline int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
u32 bw_ops, bool commit)
{
return 0;
}
static inline int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states
cdc_power_state, enum wcd_power_regions pwr_region)
{
return 0;
}
static inline int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
enum wcd_power_regions pwr_region)
{
return 0;
}
static inline int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
{
return 0;
}
static inline int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_reg_val *bulk_reg,
unsigned int size, bool interface)
{
return 0;
}
static inline int wcd9xxx_core_res_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
int num_irqs, int num_irq_regs, struct regmap *wcd_regmap)
{
return 0;
}
static inline void wcd9xxx_core_res_deinit(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
}
static inline int wcd9xxx_core_res_suspend(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
pm_message_t pmesg)
{
return 0;
}
static inline int wcd9xxx_core_res_resume(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
return 0;
}
static inline int wcd9xxx_core_irq_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
return 0;
}
static inline int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
unsigned int irq,
unsigned int irq_base)
{
return 0;
}
static inline enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void)
{
return 0;
}
static inline void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status int_state)
{
}
static inline enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
enum wcd9xxx_pm_state o,
enum wcd9xxx_pm_state n)
{
return 0;
}
static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
}
static inline int wcd9xxx_init(void)
{
return 0;
}
static inline void wcd9xxx_exit(void)
{
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __CPE_CORE_H__
#define __CPE_CORE_H__
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/dma-mapping.h>
#include <audio/sound/lsm_params.h>
enum {
CMD_INIT_STATE = 0,
CMD_SENT,
CMD_RESP_RCVD,
};
enum wcd_cpe_event {
WCD_CPE_PRE_ENABLE = 1,
WCD_CPE_POST_ENABLE,
WCD_CPE_PRE_DISABLE,
WCD_CPE_POST_DISABLE,
};
struct wcd_cpe_afe_port_cfg {
u8 port_id;
u16 bit_width;
u16 num_channels;
u32 sample_rate;
};
struct lsm_out_fmt_cfg {
u8 format;
u8 pack_mode;
u8 data_path_events;
u8 transfer_mode;
};
struct lsm_hw_params {
u32 sample_rate;
u16 num_chs;
u16 bit_width;
};
struct cpe_lsm_session {
/* sound model related */
void *snd_model_data;
u8 *conf_levels;
void *cmi_reg_handle;
/* Clients private data */
void *priv_d;
void (*event_cb)(void *priv_data,
u8 detect_status,
u8 size, u8 *payload);
struct completion cmd_comp;
struct wcd_cpe_afe_port_cfg afe_port_cfg;
struct wcd_cpe_afe_port_cfg afe_out_port_cfg;
struct mutex lsm_lock;
u32 snd_model_size;
u32 lsm_mem_handle;
u16 cmd_err_code;
u8 id;
u8 num_confidence_levels;
u16 afe_out_port_id;
struct task_struct *lsm_lab_thread;
bool started;
u32 lab_enable;
struct lsm_out_fmt_cfg out_fmt_cfg;
bool is_topology_used;
};
struct wcd_cpe_afe_ops {
int (*afe_set_params)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg,
bool afe_mad_ctl);
int (*afe_port_start)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_stop)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_suspend)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_resume)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_cmd_cfg)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
};
struct wcd_cpe_lsm_ops {
struct cpe_lsm_session *(*lsm_alloc_session)
(void *core_handle, void *lsm_priv_d,
void (*event_cb)(void *priv_data,
u8 detect_status,
u8 size, u8 *payload));
int (*lsm_dealloc_session)
(void *core_handle, struct cpe_lsm_session *session);
int (*lsm_open_tx)(void *core_handle,
struct cpe_lsm_session *session, u16 app_id,
u16 sample_rate);
int (*lsm_close_tx)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_shmem_alloc)(void *core_handle,
struct cpe_lsm_session *session, u32 size);
int (*lsm_shmem_dealloc)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_register_snd_model)(void *core_handle,
struct cpe_lsm_session *session,
enum lsm_detection_mode,
bool detect_failure);
int (*lsm_deregister_snd_model)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_get_afe_out_port_id)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_start)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_stop)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_lab_control)(void *core_handle,
struct cpe_lsm_session *session,
bool enable);
int (*lab_ch_setup)(void *core_handle,
struct cpe_lsm_session *session,
enum wcd_cpe_event event);
int (*lsm_set_data)(void *core_handle,
struct cpe_lsm_session *session,
enum lsm_detection_mode detect_mode,
bool detect_failure);
int (*lsm_set_fmt_cfg)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_set_one_param)(void *core_handle,
struct cpe_lsm_session *session,
struct lsm_params_info *p_info,
void *data, uint32_t param_type);
void (*lsm_get_snd_model_offset)
(void *core_handle, struct cpe_lsm_session *session,
size_t *offset);
int (*lsm_set_media_fmt_params)(void *core_handle,
struct cpe_lsm_session *session,
struct lsm_hw_params *param);
int (*lsm_set_port)(void *core_handle,
struct cpe_lsm_session *session, void *data);
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD_CPE)
int wcd_cpe_get_lsm_ops(struct wcd_cpe_lsm_ops *lsm_ops);
int wcd_cpe_get_afe_ops(struct wcd_cpe_afe_ops *afe_ops);
void *wcd_cpe_get_core_handle(struct snd_soc_component *component);
#else /* CONFIG_SND_SOC_WCD_CPE */
static inline int wcd_cpe_get_lsm_ops(struct wcd_cpe_lsm_ops *lsm_ops)
{
return 0;
}
static inline int wcd_cpe_get_afe_ops(struct wcd_cpe_afe_ops *afe_ops)
{
return 0;
}
static inline void *wcd_cpe_get_core_handle(struct snd_soc_component *component)
{
return NULL;
}
#endif /* CONFIG_SND_SOC_WCD_CPE */
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_CDC_PINCTRL_H_
#define __MFD_CDC_PINCTRL_H_
#include <linux/types.h>
#include <linux/of.h>
#if IS_ENABLED(CONFIG_MSM_CDC_PINCTRL)
extern int msm_cdc_pinctrl_select_sleep_state(struct device_node *np);
extern int msm_cdc_pinctrl_select_active_state(struct device_node *np);
extern int msm_cdc_pinctrl_select_alt_active_state(struct device_node *np);
extern int msm_cdc_pinctrl_get_state(struct device_node *np);
extern int msm_cdc_get_gpio_state(struct device_node *np);
extern int msm_cdc_pinctrl_set_wakeup_capable(struct device_node *np,
bool enable);
int msm_cdc_pinctrl_drv_init(void);
void msm_cdc_pinctrl_drv_exit(void);
#else
int msm_cdc_pinctrl_select_sleep_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_select_active_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_select_alt_active_state(struct device_node *np)
{
return 0;
}
int msm_cdc_get_gpio_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_drv_init(void)
{
return 0;
}
void msm_cdc_pinctrl_drv_exit(void)
{
}
int msm_cdc_pinctrl_get_state(struct device_node *np)
{
return true;
}
static int msm_cdc_pinctrl_set_wakeup_capable(struct device_node *np,
bool enable)
{
return 0;
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016, 2018-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __CODEC_POWER_SUPPLY_H__
#define __CODEC_POWER_SUPPLY_H__
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
struct cdc_regulator {
const char *name;
int min_uV;
int max_uV;
int optimum_uA;
bool ondemand;
bool lpm_supported;
bool rem_supported;
bool vote;
struct regulator *regulator;
};
struct cdc_wcd_supply {
const char *name;
struct device *dev;
struct snd_soc_component *component;
};
extern int msm_cdc_get_power_supplies(struct device *dev,
struct cdc_regulator **cdc_vreg,
int *total_num_supplies);
extern bool msm_cdc_is_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern bool msm_cdc_supply_supports_retention_mode(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern bool msm_cdc_check_supply_vote(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_disable_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_enable_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_disable_static_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_release_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_enable_static_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_set_supplies_lpm_mode(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies,
bool flag);
extern int msm_cdc_init_supplies(struct device *dev,
struct regulator_bulk_data **supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_init_supplies_v2(struct device *dev,
struct regulator_bulk_data **supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies,
u32 vote_regulator_on_demand);
int msm_cdc_init_wcd_supply(struct device_node *np, const char *name,
struct cdc_wcd_supply *cdc_supply);
int msm_cdc_enable_wcd_supply(struct cdc_wcd_supply *cdc_supply, bool enable);
extern int msm_cdc_set_supply_min_voltage(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name,
int vval_min, bool override_min_vol);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_WCD9XXX_PDATA_H__
#define __MFD_WCD9XXX_PDATA_H__
#if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE)
#include <linux/slimbus/slimbus.h>
#endif
#include "msm-cdc-supply.h"
#define MICBIAS_EXT_BYP_CAP 0x00
#define MICBIAS_NO_EXT_BYP_CAP 0x01
#define SITAR_LDOH_1P95_V 0x0
#define SITAR_LDOH_2P35_V 0x1
#define SITAR_LDOH_2P75_V 0x2
#define SITAR_LDOH_2P85_V 0x3
#define SITAR_CFILT1_SEL 0x0
#define SITAR_CFILT2_SEL 0x1
#define SITAR_CFILT3_SEL 0x2
#define WCD9XXX_LDOH_1P95_V 0x0
#define WCD9XXX_LDOH_2P35_V 0x1
#define WCD9XXX_LDOH_2P75_V 0x2
#define WCD9XXX_LDOH_2P85_V 0x3
#define WCD9XXX_LDOH_3P0_V 0x3
#define TABLA_LDOH_1P95_V 0x0
#define TABLA_LDOH_2P35_V 0x1
#define TABLA_LDOH_2P75_V 0x2
#define TABLA_LDOH_2P85_V 0x3
#define TABLA_CFILT1_SEL 0x0
#define TABLA_CFILT2_SEL 0x1
#define TABLA_CFILT3_SEL 0x2
#define MAX_AMIC_CHANNEL 7
#define TABLA_OCP_300_MA 0x0
#define TABLA_OCP_350_MA 0x2
#define TABLA_OCP_365_MA 0x3
#define TABLA_OCP_150_MA 0x4
#define TABLA_OCP_190_MA 0x6
#define TABLA_OCP_220_MA 0x7
#define TABLA_DCYCLE_255 0x0
#define TABLA_DCYCLE_511 0x1
#define TABLA_DCYCLE_767 0x2
#define TABLA_DCYCLE_1023 0x3
#define TABLA_DCYCLE_1279 0x4
#define TABLA_DCYCLE_1535 0x5
#define TABLA_DCYCLE_1791 0x6
#define TABLA_DCYCLE_2047 0x7
#define TABLA_DCYCLE_2303 0x8
#define TABLA_DCYCLE_2559 0x9
#define TABLA_DCYCLE_2815 0xA
#define TABLA_DCYCLE_3071 0xB
#define TABLA_DCYCLE_3327 0xC
#define TABLA_DCYCLE_3583 0xD
#define TABLA_DCYCLE_3839 0xE
#define TABLA_DCYCLE_4095 0xF
#define WCD9XXX_MCLK_CLK_12P288MHZ 12288000
#define WCD9XXX_MCLK_CLK_9P6HZ 9600000
/* Only valid for 9.6 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_600KHZ 600000
#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
#define WCD9XXX_DMIC_SAMPLE_RATE_3P2MHZ 3200000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
/* Only valid for 12.288 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_768KHZ 768000
#define WCD9XXX_DMIC_SAMPLE_RATE_2P048MHZ 2048000
#define WCD9XXX_DMIC_SAMPLE_RATE_3P072MHZ 3072000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
#define WCD9XXX_DMIC_SAMPLE_RATE_6P144MHZ 6144000
#define WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED 0
#define WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED 0
struct wcd9xxx_amic {
/*legacy mode, txfe_enable and txfe_buff take 7 input
* each bit represent the channel / TXFE number
* and numbered as below
* bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF
* bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF
* ...
* bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF
*/
u8 legacy_mode:MAX_AMIC_CHANNEL;
u8 txfe_enable:MAX_AMIC_CHANNEL;
u8 txfe_buff:MAX_AMIC_CHANNEL;
u8 use_pdata:MAX_AMIC_CHANNEL;
};
/* Each micbias can be assigned to one of three cfilters
* Vbatt_min >= .15V + ldoh_v
* ldoh_v >= .15v + cfiltx_mv
* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
*/
struct wcd9xxx_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv; /* in mv */
u32 cfilt2_mv; /* in mv */
u32 cfilt3_mv; /* in mv */
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb4_mv;
/* Different WCD9xxx series codecs may not
* have 4 mic biases. If a codec has fewer
* mic biases, some of these properties will
* not be used.
*/
u8 bias1_cfilt_sel;
u8 bias2_cfilt_sel;
u8 bias3_cfilt_sel;
u8 bias4_cfilt_sel;
u8 bias1_cap_mode;
u8 bias2_cap_mode;
u8 bias3_cap_mode;
u8 bias4_cap_mode;
bool bias2_is_headset_only;
};
struct wcd9xxx_ocp_setting {
unsigned int use_pdata:1; /* 0 - use sys default as recommended */
unsigned int num_attempts:4; /* up to 15 attempts */
unsigned int run_time:4; /* in duty cycle */
unsigned int wait_time:4; /* in duty cycle */
unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
};
#define WCD9XXX_MAX_REGULATOR 9
/*
* format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX
*
* <POWER_SUPPLY_PIN_NAME> from Tabla objective spec
*/
#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000
#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000
#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000
#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000
#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000
#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000
#define WCD9XXX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
#define WCD9XXX_VDD_SPKDRV2_NAME "cdc-vdd-spkdrv-2"
struct wcd9xxx_regulator {
const char *name;
int min_uV;
int max_uV;
int optimum_uA;
bool ondemand;
struct regulator *regulator;
};
struct wcd9xxx_pdata {
int irq;
int irq_base;
int num_irqs;
int reset_gpio;
bool has_buck_vsel_gpio;
bool has_micb_supply_en_gpio;
struct device_node *buck_vsel_ctl_np;
struct device_node *micb_en_ctl;
struct device_node *wcd_rst_np;
struct wcd9xxx_amic amic_settings;
#if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE)
struct slim_device slimbus_slave_device;
#endif
struct wcd9xxx_micbias_setting micbias;
struct wcd9xxx_ocp_setting ocp;
struct cdc_regulator *regulator;
int num_supplies;
u32 mclk_rate;
u32 dmic_sample_rate;
u32 mad_dmic_sample_rate;
u32 ecpp_dmic_sample_rate;
u32 dmic_clk_drv;
u16 use_pinctrl;
u32 vote_regulator_on_demand;
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2019,, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD_CLSH
#define _WCD_CLSH
#include <linux/stringify.h>
#define WCD_CLSH_STRINGIFY(s) __stringify(s)
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_CLSH_EVENT_PRE_DAC 0x01
#define WCD_CLSH_EVENT_POST_PA 0x02
/*
* Basic states for Class H state machine.
* represented as a bit mask within a u8 data type
* bit 0: EAR mode
* bit 1: HPH Left mode
* bit 2: HPH Right mode
* bit 3: AUX mode
*/
#define WCD_CLSH_STATE_IDLE 0x00
#define WCD_CLSH_STATE_EAR (0x01 << 0)
#define WCD_CLSH_STATE_HPHL (0x01 << 1)
#define WCD_CLSH_STATE_HPHR (0x01 << 2)
#define WCD_CLSH_STATE_AUX (0x01 << 3)
/*
* Though number of CLSH states is 4, max state should be 5
* because state array index starts from 1.
*/
#define WCD_CLSH_STATE_MAX 5
#define NUM_CLSH_STATES (0x01 << WCD_CLSH_STATE_MAX)
/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
#define WCD_CLSH_STATE_HPH_ST (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_HPHR)
#define WCD_CLSH_STATE_HPHL_AUX (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPHR_AUX (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPH_ST_AUX (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_EAR_AUX (WCD_CLSH_STATE_EAR | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPHL_EAR (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPHR_EAR (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPH_ST_EAR (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_EAR)
#define WCD9XXX_BASE_ADDRESS 0x3000
#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
enum {
CLS_H_NORMAL = 0, /* Class-H Default */
CLS_H_HIFI, /* Class-H HiFi */
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB Low HIFI*/
CLS_H_LOHIFI, /* LoHIFI */
CLS_H_ULP, /* Ultra Low power */
CLS_AB_HIFI, /* Class-AB */
CLS_AB_LP, /* Class-AB Low Power */
CLS_AB_LOHIFI, /* Class-AB Low HIFI */
CLS_NONE, /* None of the above modes */
};
/* Class H data that the codec driver will maintain */
struct wcd_clsh_cdc_info {
u8 state;
int flyback_users;
int buck_users;
int interpolator_modes[WCD_CLSH_STATE_MAX];
};
#ifdef CONFIG_SND_SOC_WCD9XXX_V2
extern void wcd_cls_h_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_info *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode);
extern void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh);
extern void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
int mode);
#else
static inline void wcd_cls_h_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_info *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode)
{
}
static inline extern void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh)
{
}
static inline extern void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
int mode)
{
}
#endif /* CONFIG_SND_SOC_WCD9XXX_V2 */
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD_IRQ_H_
#define __WCD_IRQ_H_
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
struct wcd_irq_info {
struct regmap_irq_chip *wcd_regmap_irq_chip;
char *codec_name;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_chip;
struct device *dev;
};
#if (IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE) | \
IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE_V2))
int wcd_irq_init(struct wcd_irq_info *irq_info, struct irq_domain **virq);
int wcd_irq_exit(struct wcd_irq_info *irq_info, struct irq_domain *virq);
int wcd_request_irq(struct wcd_irq_info *irq_info, int irq, const char *name,
irq_handler_t handler, void *data);
void wcd_free_irq(struct wcd_irq_info *irq_info, int irq, void *data);
void wcd_enable_irq(struct wcd_irq_info *irq_info, int irq);
void wcd_disable_irq(struct wcd_irq_info *irq_info, int irq);
#else
static inline int wcd_irq_init(struct wcd_irq_info *irq_info,
struct irq_domain **virq)
{
return 0;
};
static inline int wcd_irq_exit(struct wcd_irq_info *irq_info,
struct irq_domain *virq)
{
return 0;
};
static inline int wcd_request_irq(struct wcd_irq_info *irq_info,
int irq, const char *name,
irq_handler_t handler, void *data)
{
return 0;
};
static inline void wcd_free_irq(struct wcd_irq_info *irq_info, int irq, void *data);
{
};
static inline void wcd_enable_irq(struct wcd_irq_info *irq_info, int irq);
{
};
static inline void wcd_disable_irq(struct wcd_irq_info *irq_info, int irq);
{
};
#endif
#endif /* __WCD_IRQ_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD_MBHC_V2_API_H__
#define __WCD_MBHC_V2_API_H__
#include "wcd-mbhc-v2.h"
#if IS_ENABLED(CONFIG_SND_SOC_WCD_MBHC)
int wcd_mbhc_start(struct wcd_mbhc *mbhc,
struct wcd_mbhc_config *mbhc_cfg);
void wcd_mbhc_stop(struct wcd_mbhc *mbhc);
int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_component *component,
const struct wcd_mbhc_cb *mbhc_cb,
const struct wcd_mbhc_intr *mbhc_cdc_intr_ids,
struct wcd_mbhc_register *wcd_mbhc_regs,
bool impedance_det_en);
int wcd_mbhc_get_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
uint32_t *zr);
void wcd_mbhc_deinit(struct wcd_mbhc *mbhc);
#else
static inline void wcd_mbhc_stop(struct wcd_mbhc *mbhc)
{
}
int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_component *component,
const struct wcd_mbhc_cb *mbhc_cb,
const struct wcd_mbhc_intr *mbhc_cdc_intr_ids,
struct wcd_mbhc_register *wcd_mbhc_regs,
bool impedance_det_en)
{
return 0;
}
static inline int wcd_mbhc_start(struct wcd_mbhc *mbhc,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline int wcd_mbhc_get_impedance(struct wcd_mbhc *mbhc,
uint32_t *zl,
uint32_t *zr)
{
*zl = 0;
*zr = 0;
return -EINVAL;
}
static inline void wcd_mbhc_deinit(struct wcd_mbhc *mbhc)
{
}
#endif
#endif /* __WCD_MBHC_V2_API_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __WCD_MBHC_V2_H__
#define __WCD_MBHC_V2_H__
#include <linux/wait.h>
#include <linux/stringify.h>
#include <linux/power_supply.h>
#include <linux/extcon.h>
#include <linux/extcon-provider.h>
#include "wcdcal-hwdep.h"
#include <sound/jack.h>
#define TOMBAK_MBHC_NC 0
#define TOMBAK_MBHC_NO 1
#define WCD_MBHC_DEF_BUTTONS 8
#define WCD_MBHC_KEYCODE_NUM 8
#define WCD_MBHC_USLEEP_RANGE_MARGIN_US 100
#define WCD_MBHC_THR_HS_MICB_MV 2700
/* z value defined in Ohms */
#define WCD_MONO_HS_MIN_THR 2
#define WCD_MBHC_STRINGIFY(s) __stringify(s)
#define WCD_MBHC_REGISTER(rid, rreg, rmask, rshift, rinvert) \
{ .id = rid, .reg = rreg, .mask = rmask, .offset = rshift, .invert = rinvert }
#define WCD_MBHC_RSC_LOCK(mbhc) \
{ \
pr_debug("%s: Acquiring BCL\n", __func__); \
mutex_lock(&mbhc->codec_resource_lock); \
pr_debug("%s: Acquiring BCL done\n", __func__); \
}
#define WCD_MBHC_RSC_UNLOCK(mbhc) \
{ \
pr_debug("%s: Release BCL\n", __func__); \
mutex_unlock(&mbhc->codec_resource_lock); \
}
#define WCD_MBHC_RSC_ASSERT_LOCKED(mbhc) \
{ \
WARN_ONCE(!mutex_is_locked(&mbhc->codec_resource_lock), \
"%s: BCL should have acquired\n", __func__); \
}
/*
* Macros to update and read mbhc register bits. Check for
* "0" before updating or reading the register, because it
* is possible that one codec wants to write to that bit and
* other codec does not.
*/
#define WCD_MBHC_REG_UPDATE_BITS(function, val) \
do { \
if (mbhc->wcd_mbhc_regs[function].reg) { \
snd_soc_component_update_bits(mbhc->component, \
mbhc->wcd_mbhc_regs[function].reg, \
mbhc->wcd_mbhc_regs[function].mask, \
val << (mbhc->wcd_mbhc_regs[function].offset)); \
} \
} while (0)
#define WCD_MBHC_REG_READ(function, val) \
do { \
if (mbhc->wcd_mbhc_regs[function].reg) { \
val = (((snd_soc_component_read(mbhc->component, \
mbhc->wcd_mbhc_regs[function].reg)) & \
(mbhc->wcd_mbhc_regs[function].mask)) >> \
(mbhc->wcd_mbhc_regs[function].offset)); \
} else { \
val = -EINVAL; \
} \
} while (0)
#define WCD_MBHC_CAL_SIZE(buttons, rload) ( \
sizeof(struct wcd_mbhc_general_cfg) + \
sizeof(struct wcd_mbhc_plug_detect_cfg) + \
((sizeof(s16) + sizeof(s16)) * buttons) + \
sizeof(struct wcd_mbhc_plug_type_cfg) + \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
((sizeof(u16) + sizeof(u16)) * rload) \
)
#define WCD_MBHC_CAL_GENERAL_PTR(cali) ( \
(struct wcd_mbhc_general_cfg *) cali)
#define WCD_MBHC_CAL_PLUG_DET_PTR(cali) ( \
(struct wcd_mbhc_plug_detect_cfg *) \
&(WCD_MBHC_CAL_GENERAL_PTR(cali)[1]))
#define WCD_MBHC_CAL_PLUG_TYPE_PTR(cali) ( \
(struct wcd_mbhc_plug_type_cfg *) \
&(WCD_MBHC_CAL_PLUG_DET_PTR(cali)[1]))
#define WCD_MBHC_CAL_BTN_DET_PTR(cali) ( \
(struct wcd_mbhc_btn_detect_cfg *) \
&(WCD_MBHC_CAL_PLUG_TYPE_PTR(cali)[1]))
#define WCD_MBHC_CAL_IMPED_DET_PTR(cali) ( \
(struct wcd_mbhc_imped_detect_cfg *) \
(((void *)&WCD_MBHC_CAL_BTN_DET_PTR(cali)[1]) + \
(WCD_MBHC_CAL_BTN_DET_PTR(cali)->num_btn * \
(sizeof(WCD_MBHC_CAL_BTN_DET_PTR(cali)->_v_btn_low[0]) + \
sizeof(WCD_MBHC_CAL_BTN_DET_PTR(cali)->_v_btn_high[0])))) \
)
#define WCD_MBHC_CAL_MIN_SIZE ( \
sizeof(struct wcd_mbhc_general_cfg) + \
sizeof(struct wcd_mbhc_plug_detect_cfg) + \
sizeof(struct wcd_mbhc_plug_type_cfg) + \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
(sizeof(u16)*2) \
)
#define WCD_MBHC_CAL_BTN_SZ(cfg_ptr) ( \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
(cfg_ptr->num_btn * (sizeof(cfg_ptr->_v_btn_low[0]) + \
sizeof(cfg_ptr->_v_btn_high[0]))))
#define WCD_MBHC_CAL_IMPED_MIN_SZ ( \
sizeof(struct wcd_mbhc_imped_detect_cfg) + sizeof(u16) * 2)
#define WCD_MBHC_CAL_IMPED_SZ(cfg_ptr) ( \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
(cfg_ptr->_n_rload * \
(sizeof(cfg_ptr->_rload[0]) + sizeof(cfg_ptr->_alpha[0]))))
#if IS_ENABLED(CONFIG_AUDIO_QGKI)
#define WCD_MBHC_JACK_MASK (SND_JACK_HEADSET | SND_JACK_OC_HPHL | \
SND_JACK_OC_HPHR | SND_JACK_LINEOUT | \
SND_JACK_MECHANICAL | \
SND_JACK_UNSUPPORTED)
#else
#define WCD_MBHC_JACK_MASK (SND_JACK_HEADSET | SND_JACK_LINEOUT | \
SND_JACK_MECHANICAL)
#endif /* CONFIG_AUDIO_QGKI */
#define WCD_MBHC_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3 | \
SND_JACK_BTN_4 | SND_JACK_BTN_5)
#define OCP_ATTEMPT 20
#define HS_DETECT_PLUG_TIME_MS (3 * 1000)
#define SPECIAL_HS_DETECT_TIME_MS (2 * 1000)
#define MBHC_BUTTON_PRESS_THRESHOLD_MIN 250
#define GND_MIC_SWAP_THRESHOLD 4
#define GND_MIC_USBC_SWAP_THRESHOLD 2
#define WCD_FAKE_REMOVAL_MIN_PERIOD_MS 100
#define HS_VREF_MIN_VAL 1400
#define FW_READ_ATTEMPTS 15
#define FW_READ_TIMEOUT 4000000
#define FAKE_REM_RETRY_ATTEMPTS 3
#define HPHL_CROSS_CONN_THRESHOLD 100
#define HPHR_CROSS_CONN_THRESHOLD 100
#define WCD_MBHC_BTN_PRESS_COMPL_TIMEOUT_MS 50
#define ANC_DETECT_RETRY_CNT 7
#define WCD_MBHC_SPL_HS_CNT 1
enum wcd_mbhc_detect_logic {
WCD_DETECTION_LEGACY,
WCD_DETECTION_ADC,
};
enum wcd_mbhc_cs_mb_en_flag {
WCD_MBHC_EN_CS = 0,
WCD_MBHC_EN_MB,
WCD_MBHC_EN_PULLUP,
WCD_MBHC_EN_NONE,
};
enum {
WCD_MBHC_ELEC_HS_INS,
WCD_MBHC_ELEC_HS_REM,
};
struct wcd_mbhc;
enum wcd_mbhc_register_function {
WCD_MBHC_L_DET_EN,
WCD_MBHC_GND_DET_EN,
WCD_MBHC_MECH_DETECTION_TYPE,
WCD_MBHC_MIC_CLAMP_CTL,
WCD_MBHC_ELECT_DETECTION_TYPE,
WCD_MBHC_HS_L_DET_PULL_UP_CTRL,
WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL,
WCD_MBHC_HPHL_PLUG_TYPE,
WCD_MBHC_GND_PLUG_TYPE,
WCD_MBHC_SW_HPH_LP_100K_TO_GND,
WCD_MBHC_ELECT_SCHMT_ISRC,
WCD_MBHC_FSM_EN,
WCD_MBHC_INSREM_DBNC,
WCD_MBHC_BTN_DBNC,
WCD_MBHC_HS_VREF,
WCD_MBHC_HS_COMP_RESULT,
WCD_MBHC_IN2P_CLAMP_STATE,
WCD_MBHC_MIC_SCHMT_RESULT,
WCD_MBHC_HPHL_SCHMT_RESULT,
WCD_MBHC_HPHR_SCHMT_RESULT,
WCD_MBHC_OCP_FSM_EN,
WCD_MBHC_BTN_RESULT,
WCD_MBHC_BTN_ISRC_CTL,
WCD_MBHC_ELECT_RESULT,
WCD_MBHC_MICB_CTRL, /* Pull-up and micb control */
WCD_MBHC_HPH_CNP_WG_TIME,
WCD_MBHC_HPHR_PA_EN,
WCD_MBHC_HPHL_PA_EN,
WCD_MBHC_HPH_PA_EN,
WCD_MBHC_SWCH_LEVEL_REMOVE,
WCD_MBHC_PULLDOWN_CTRL,
WCD_MBHC_ANC_DET_EN,
WCD_MBHC_FSM_STATUS,
WCD_MBHC_MUX_CTL,
WCD_MBHC_MOISTURE_STATUS,
WCD_MBHC_HPHR_GND,
WCD_MBHC_HPHL_GND,
WCD_MBHC_HPHL_OCP_DET_EN,
WCD_MBHC_HPHR_OCP_DET_EN,
WCD_MBHC_HPHL_OCP_STATUS,
WCD_MBHC_HPHR_OCP_STATUS,
WCD_MBHC_ADC_EN,
WCD_MBHC_ADC_COMPLETE,
WCD_MBHC_ADC_TIMEOUT,
WCD_MBHC_ADC_RESULT,
WCD_MBHC_MICB2_VOUT,
WCD_MBHC_ADC_MODE,
WCD_MBHC_DETECTION_DONE,
WCD_MBHC_ELECT_ISRC_EN,
WCD_MBHC_REG_FUNC_MAX,
};
enum wcd_mbhc_plug_type {
MBHC_PLUG_TYPE_INVALID = -1,
MBHC_PLUG_TYPE_NONE,
MBHC_PLUG_TYPE_HEADSET,
MBHC_PLUG_TYPE_HEADPHONE,
MBHC_PLUG_TYPE_HIGH_HPH,
MBHC_PLUG_TYPE_GND_MIC_SWAP,
MBHC_PLUG_TYPE_ANC_HEADPHONE,
};
enum pa_dac_ack_flags {
WCD_MBHC_HPHL_PA_OFF_ACK = 0,
WCD_MBHC_HPHR_PA_OFF_ACK,
};
enum anc_ack_flags {
WCD_MBHC_ANC0_OFF_ACK = 0,
WCD_MBHC_ANC1_OFF_ACK,
};
enum wcd_mbhc_btn_det_mem {
WCD_MBHC_BTN_DET_V_BTN_LOW,
WCD_MBHC_BTN_DET_V_BTN_HIGH
};
enum {
MIC_BIAS_1 = 1,
MIC_BIAS_2,
MIC_BIAS_3,
MIC_BIAS_4
};
enum {
MICB_PULLUP_ENABLE,
MICB_PULLUP_DISABLE,
MICB_ENABLE,
MICB_DISABLE,
};
enum {
MBHC_COMMON_MICB_PRECHARGE,
MBHC_COMMON_MICB_SET_VAL,
MBHC_COMMON_MICB_TAIL_CURR,
};
enum wcd_notify_event {
WCD_EVENT_INVALID,
/* events for micbias ON and OFF */
WCD_EVENT_PRE_MICBIAS_2_OFF,
WCD_EVENT_POST_MICBIAS_2_OFF,
WCD_EVENT_PRE_MICBIAS_2_ON,
WCD_EVENT_POST_MICBIAS_2_ON,
WCD_EVENT_PRE_DAPM_MICBIAS_2_OFF,
WCD_EVENT_POST_DAPM_MICBIAS_2_OFF,
WCD_EVENT_PRE_DAPM_MICBIAS_2_ON,
WCD_EVENT_POST_DAPM_MICBIAS_2_ON,
/* events for PA ON and OFF */
WCD_EVENT_PRE_HPHL_PA_ON,
WCD_EVENT_POST_HPHL_PA_OFF,
WCD_EVENT_PRE_HPHR_PA_ON,
WCD_EVENT_POST_HPHR_PA_OFF,
WCD_EVENT_PRE_HPHL_PA_OFF,
WCD_EVENT_PRE_HPHR_PA_OFF,
WCD_EVENT_OCP_OFF,
WCD_EVENT_OCP_ON,
WCD_EVENT_LAST,
};
enum wcd_mbhc_event_state {
WCD_MBHC_EVENT_PA_HPHL,
WCD_MBHC_EVENT_PA_HPHR,
};
struct wcd_mbhc_general_cfg {
u8 t_ldoh;
u8 t_bg_fast_settle;
u8 t_shutdown_plug_rem;
u8 mbhc_nsa;
u8 mbhc_navg;
u8 v_micbias_l;
u8 v_micbias;
u8 mbhc_reserved;
u16 settle_wait;
u16 t_micbias_rampup;
u16 t_micbias_rampdown;
u16 t_supply_bringup;
} __packed;
struct wcd_mbhc_plug_detect_cfg {
u32 mic_current;
u32 hph_current;
u16 t_mic_pid;
u16 t_ins_complete;
u16 t_ins_retry;
u16 v_removal_delta;
u8 micbias_slow_ramp;
u8 reserved0;
u8 reserved1;
u8 reserved2;
} __packed;
struct wcd_mbhc_plug_type_cfg {
u8 av_detect;
u8 mono_detect;
u8 num_ins_tries;
u8 reserved0;
s16 v_no_mic;
s16 v_av_min;
s16 v_av_max;
s16 v_hs_min;
s16 v_hs_max;
u16 reserved1;
} __packed;
struct wcd_mbhc_btn_detect_cfg {
s8 c[8];
u8 nc;
u8 n_meas;
u8 mbhc_nsc;
u8 n_btn_meas;
u8 n_btn_con;
u8 num_btn;
u8 reserved0;
u8 reserved1;
u16 t_poll;
u16 t_bounce_wait;
u16 t_rel_timeout;
s16 v_btn_press_delta_sta;
s16 v_btn_press_delta_cic;
u16 t_btn0_timeout;
s16 _v_btn_low[0]; /* v_btn_low[num_btn] */
s16 _v_btn_high[0]; /* v_btn_high[num_btn] */
u8 _n_ready[2];
u8 _n_cic[2];
u8 _gain[2];
} __packed;
struct wcd_mbhc_imped_detect_cfg {
u8 _hs_imped_detect;
u8 _n_rload;
u8 _hph_keep_on;
u8 _repeat_rload_calc;
u16 _t_dac_ramp_time;
u16 _rhph_high;
u16 _rhph_low;
u16 _rload[0]; /* rload[n_rload] */
u16 _alpha[0]; /* alpha[n_rload] */
u16 _beta[3];
} __packed;
enum wcd_mbhc_hph_type {
WCD_MBHC_HPH_NONE = 0,
WCD_MBHC_HPH_MONO,
WCD_MBHC_HPH_STEREO,
};
/*
* These enum definitions are directly mapped to the register
* definitions
*/
enum mbhc_moisture_vref {
V_OFF,
V_45_MV,
V_100_MV,
V_225_MV,
};
enum mbhc_hs_pullup_iref {
I_DEFAULT = -1,
I_OFF = 0,
I_1P0_UA,
I_2P0_UA,
I_3P0_UA,
};
enum mbhc_hs_pullup_iref_v2 {
HS_PULLUP_I_DEFAULT = -1,
HS_PULLUP_I_3P0_UA = 0,
HS_PULLUP_I_2P25_UA,
HS_PULLUP_I_1P5_UA,
HS_PULLUP_I_0P75_UA,
HS_PULLUP_I_1P125_UA = 0x05,
HS_PULLUP_I_0P375_UA = 0x07,
HS_PULLUP_I_2P0_UA,
HS_PULLUP_I_1P0_UA = 0x0A,
HS_PULLUP_I_0P5_UA,
HS_PULLUP_I_0P25_UA = 0x0F,
HS_PULLUP_I_0P125_UA = 0x17,
HS_PULLUP_I_OFF,
};
enum mbhc_moisture_rref {
R_OFF,
R_24_KOHM,
R_84_KOHM,
R_184_KOHM,
};
struct wcd_mbhc_config {
bool read_fw_bin;
void *calibration;
bool detect_extn_cable;
bool mono_stero_detection;
bool (*swap_gnd_mic)(struct snd_soc_component *component, bool active);
bool hs_ext_micbias;
bool gnd_det_en;
int key_code[WCD_MBHC_KEYCODE_NUM];
uint32_t linein_th;
bool moisture_en;
int mbhc_micbias;
int anc_micbias;
bool enable_anc_mic_detect;
u32 enable_usbc_analog;
bool moisture_duty_cycle_en;
bool usbss_hsj_connect_enable;
};
struct wcd_mbhc_intr {
int mbhc_sw_intr;
int mbhc_btn_press_intr;
int mbhc_btn_release_intr;
int mbhc_hs_ins_intr;
int mbhc_hs_rem_intr;
int hph_left_ocp;
int hph_right_ocp;
};
struct wcd_mbhc_register {
const char *id;
int reg;
u8 mask;
u8 offset;
u8 invert;
};
struct wcd_mbhc_cb {
void (*update_cross_conn_thr)
(struct wcd_mbhc *mbhc);
void (*mbhc_surge_ctl)
(struct wcd_mbhc *mbhc, bool surge_en);
void (*mbhc_comp_autozero_control)
(struct wcd_mbhc *mbhc, bool az_enable);
void (*get_micbias_val)
(struct wcd_mbhc *mbhc, int *mb);
void (*bcs_enable)
(struct wcd_mbhc *mbhc, bool bcs_enable);
int (*enable_mb_source)(struct wcd_mbhc *mbhc, bool turn_on);
void (*trim_btn_reg)(struct snd_soc_component *component);
void (*compute_impedance)(struct wcd_mbhc *mbhc,
uint32_t *zl, uint32_t *zr);
void (*set_micbias_value)(struct snd_soc_component *component);
void (*set_auto_zeroing)(struct snd_soc_component *component,
bool enable);
struct firmware_cal * (*get_hwdep_fw_cal)(struct wcd_mbhc *mbhc,
enum wcd_cal_type);
void (*set_cap_mode)(struct snd_soc_component *component,
bool micbias1, bool micbias2);
int (*register_notifier)(struct wcd_mbhc *mbhc,
struct notifier_block *nblock,
bool enable);
int (*request_irq)(struct snd_soc_component *component,
int irq, irq_handler_t handler,
const char *name, void *data);
void (*irq_control)(struct snd_soc_component *component,
int irq, bool enable);
int (*free_irq)(struct snd_soc_component *component,
int irq, void *data);
void (*clk_setup)(struct snd_soc_component *component, bool enable);
int (*map_btn_code_to_num)(struct snd_soc_component *component);
bool (*lock_sleep)(struct wcd_mbhc *mbhc, bool lock);
bool (*micbias_enable_status)(struct wcd_mbhc *mbhc, int micb_num);
void (*mbhc_bias)(struct snd_soc_component *component, bool enable);
void (*mbhc_common_micb_ctrl)(struct snd_soc_component *component,
int event, bool enable);
void (*micb_internal)(struct snd_soc_component *component,
int micb_num, bool enable);
bool (*hph_pa_on_status)(struct snd_soc_component *component);
void (*set_btn_thr)(struct snd_soc_component *component,
s16 *btn_low, s16 *btn_high,
int num_btn, bool is_micbias);
void (*hph_pull_up_control)(struct snd_soc_component *component,
enum mbhc_hs_pullup_iref);
int (*mbhc_micbias_control)(struct snd_soc_component *component,
int micb_num, int req);
void (*mbhc_micb_ramp_control)(struct snd_soc_component *component,
bool enable);
void (*skip_imped_detect)(struct snd_soc_component *component);
bool (*extn_use_mb)(struct snd_soc_component *component);
int (*mbhc_micb_ctrl_thr_mic)(struct snd_soc_component *component,
int micb_num, bool req_en);
void (*mbhc_gnd_det_ctrl)(struct snd_soc_component *component,
bool enable);
void (*hph_pull_down_ctrl)(struct snd_soc_component *component,
bool enable);
void (*mbhc_moisture_config)(struct wcd_mbhc *mbhc);
bool (*hph_register_recovery)(struct wcd_mbhc *mbhc);
void (*update_anc_state)(struct snd_soc_component *component,
bool enable, int anc_num);
bool (*is_anc_on)(struct wcd_mbhc *mbhc);
void (*hph_pull_up_control_v2)(struct snd_soc_component *component,
int pull_up_cur);
bool (*mbhc_get_moisture_status)(struct wcd_mbhc *mbhc);
void (*mbhc_moisture_polling_ctrl)(struct wcd_mbhc *mbhc, bool enable);
void (*mbhc_moisture_detect_en)(struct wcd_mbhc *mbhc, bool enable);
void (*surge_reset_routine)(struct wcd_mbhc *mbhc);
void (*zdet_leakage_resistance)(struct wcd_mbhc *mbhc, bool enable);
void (*mbhc_button_debounce_set)(struct snd_soc_component *component);
int (*mbhc_force_micbias_disable)(struct snd_soc_component *component,
int micb_num);
};
struct wcd_mbhc_fn {
irqreturn_t (*wcd_mbhc_hs_ins_irq)(int irq, void *data);
irqreturn_t (*wcd_mbhc_hs_rem_irq)(int irq, void *data);
void (*wcd_mbhc_detect_plug_type)(struct wcd_mbhc *mbhc);
bool (*wcd_mbhc_detect_anc_plug_type)(struct wcd_mbhc *mbhc);
void (*wcd_cancel_hs_detect_plug)(struct wcd_mbhc *mbhc,
struct work_struct *work);
};
struct wcd_mbhc {
/* Delayed work to report long button press */
struct delayed_work mbhc_btn_dwork;
int buttons_pressed;
struct wcd_mbhc_config *mbhc_cfg;
const struct wcd_mbhc_cb *mbhc_cb;
u32 hph_status; /* track headhpone status */
u8 hphlocp_cnt; /* headphone left ocp retry */
u8 hphrocp_cnt; /* headphone right ocp retry */
wait_queue_head_t wait_btn_press;
bool is_btn_press;
u8 current_plug;
bool in_swch_irq_handler;
bool hphl_swh; /*track HPHL switch NC / NO */
bool gnd_swh; /*track GND switch NC / NO */
u32 hs_thr;
u32 hph_thr;
u32 micb_mv;
u32 swap_thr;
u32 moist_vref;
u32 moist_iref;
u32 moist_rref;
u32 hphl_cross_conn_thr;
u32 hphr_cross_conn_thr;
u8 micbias1_cap_mode; /* track ext cap setting */
u8 micbias2_cap_mode; /* track ext cap setting */
bool hs_detect_work_stop;
bool micbias_enable;
bool btn_press_intr;
bool is_hs_recording;
bool is_extn_cable;
bool skip_imped_detection;
bool is_btn_already_regd;
bool extn_cable_hph_rem;
struct snd_soc_component *component;
/* Work to perform MBHC Firmware Read */
struct delayed_work mbhc_firmware_dwork;
const struct firmware *mbhc_fw;
struct firmware_cal *mbhc_cal;
/* track PA/DAC state to sync with userspace */
unsigned long hph_pa_dac_state;
unsigned long hph_anc_state;
unsigned long event_state;
unsigned long jiffies_atreport;
/* impedance of hphl and hphr */
uint32_t zl, zr;
bool impedance_detect;
/* Holds type of Headset - Mono/Stereo */
enum wcd_mbhc_hph_type hph_type;
struct snd_soc_jack headset_jack;
struct snd_soc_jack button_jack;
struct mutex codec_resource_lock;
/* Holds codec specific interrupt mapping */
const struct wcd_mbhc_intr *intr_ids;
/* Work to correct accessory type */
struct work_struct correct_plug_swch;
struct notifier_block nblock;
struct wcd_mbhc_register *wcd_mbhc_regs;
struct completion btn_press_compl;
bool deinit_in_progress;
/* Holds mbhc detection method - ADC/Legacy */
unsigned int mbhc_detection_logic;
unsigned long intr_status;
bool is_hph_ocp_pending;
struct wcd_mbhc_fn *mbhc_fn;
bool force_linein;
struct device_node *wcd_usbss_aatc_dev_np;
struct device_node *fsa_aatc_dev_np;
struct device_node *aatc_dev_np;
struct notifier_block aatc_dev_nb;
struct extcon_dev *extdev;
};
void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc,
enum wcd_mbhc_plug_type plug_type);
void wcd_mbhc_hs_elec_irq(struct wcd_mbhc *mbhc, int irq_type, bool enable);
void wcd_mbhc_elec_hs_report_unplug(struct wcd_mbhc *mbhc);
bool wcd_swch_level_remove(struct wcd_mbhc *mbhc);
void wcd_enable_curr_micbias(const struct wcd_mbhc *mbhc,
const enum wcd_mbhc_cs_mb_en_flag cs_mb_en);
void wcd_mbhc_jack_report(struct wcd_mbhc *mbhc,
struct snd_soc_jack *jack, int status, int mask);
int wcd_cancel_btn_work(struct wcd_mbhc *mbhc);
int wcd_mbhc_get_button_mask(struct wcd_mbhc *mbhc);
void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion,
enum snd_jack_types jack_type);
#endif /* __WCD_MBHC_V2_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_COMMON_V2
#define _WCD9XXX_COMMON_V2
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_CLSH_EVENT_PRE_DAC 0x01
#define WCD_CLSH_EVENT_POST_PA 0x02
#define MAX_VBAT_MONITOR_WRITES 17
/*
* Basic states for Class H state machine.
* represented as a bit mask within a u8 data type
* bit 0: EAR mode
* bit 1: HPH Left mode
* bit 2: HPH Right mode
* bit 3: Lineout mode
*/
#define WCD_CLSH_STATE_IDLE 0x00
#define WCD_CLSH_STATE_EAR (0x01 << 0)
#define WCD_CLSH_STATE_HPHL (0x01 << 1)
#define WCD_CLSH_STATE_HPHR (0x01 << 2)
#define WCD_CLSH_STATE_LO (0x01 << 3)
/*
* Though number of CLSH states are 4, max state shoulbe be 5
* because state array index starts from 1.
*/
#define WCD_CLSH_STATE_MAX 5
#define NUM_CLSH_STATES_V2 (0x01 << WCD_CLSH_STATE_MAX)
/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
#define WCD_CLSH_STATE_HPH_ST (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_HPHR)
#define WCD_CLSH_STATE_HPHL_LO (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPHR_LO (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPH_ST_LO (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_EAR_LO (WCD_CLSH_STATE_EAR | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPHL_EAR (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPHR_EAR (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPH_ST_EAR (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_EAR)
enum {
CLS_H_NORMAL = 0, /* Class-H Default */
CLS_H_HIFI, /* Class-H HiFi */
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB Low HIFI*/
CLS_H_LOHIFI, /* LoHIFI */
CLS_H_ULP, /* Ultra Low power */
CLS_AB_HIFI, /* Class-AB */
CLS_NONE, /* None of the above modes */
};
/* Class H data that the codec driver will maintain */
struct wcd_clsh_cdc_data {
u8 state;
int flyback_users;
int buck_users;
int clsh_users;
int interpolator_modes[WCD_CLSH_STATE_MAX];
};
struct wcd_mad_audio_header {
u32 reserved[3];
u32 num_reg_cfg;
};
struct wcd_mad_microphone_info {
uint8_t input_microphone;
uint8_t cycle_time;
uint8_t settle_time;
uint8_t padding;
} __packed;
struct wcd_mad_micbias_info {
uint8_t micbias;
uint8_t k_factor;
uint8_t external_bypass_capacitor;
uint8_t internal_biasing;
uint8_t cfilter;
uint8_t padding[3];
} __packed;
struct wcd_mad_rms_audio_beacon_info {
uint8_t rms_omit_samples;
uint8_t rms_comp_time;
uint8_t detection_mechanism;
uint8_t rms_diff_threshold;
uint8_t rms_threshold_lsb;
uint8_t rms_threshold_msb;
uint8_t padding[2];
uint8_t iir_coefficients[36];
} __packed;
struct wcd_mad_rms_ultrasound_info {
uint8_t rms_comp_time;
uint8_t detection_mechanism;
uint8_t rms_diff_threshold;
uint8_t rms_threshold_lsb;
uint8_t rms_threshold_msb;
uint8_t padding[3];
uint8_t iir_coefficients[36];
} __packed;
struct wcd_mad_audio_cal {
uint32_t version;
struct wcd_mad_microphone_info microphone_info;
struct wcd_mad_micbias_info micbias_info;
struct wcd_mad_rms_audio_beacon_info audio_info;
struct wcd_mad_rms_audio_beacon_info beacon_info;
struct wcd_mad_rms_ultrasound_info ultrasound_info;
} __packed;
struct wcd9xxx_anc_header {
u32 reserved[3];
u32 num_anc_slots;
};
struct vbat_monitor_reg {
u32 size;
u32 writes[MAX_VBAT_MONITOR_WRITES];
} __packed;
struct wcd_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
extern void wcd_clsh_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_data *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode);
extern void wcd_clsh_init(struct wcd_clsh_cdc_data *clsh);
extern int wcd_clsh_get_clsh_state(struct wcd_clsh_cdc_data *clsh);
extern void wcd_clsh_imped_config(struct snd_soc_component *component,
int imped, bool reset);
enum {
RESERVED = 0,
AANC_LPF_FF_FB = 1,
AANC_LPF_COEFF_MSB,
AANC_LPF_COEFF_LSB,
HW_MAD_AUDIO_ENABLE,
HW_MAD_ULTR_ENABLE,
HW_MAD_BEACON_ENABLE,
HW_MAD_AUDIO_SLEEP_TIME,
HW_MAD_ULTR_SLEEP_TIME,
HW_MAD_BEACON_SLEEP_TIME,
HW_MAD_TX_AUDIO_SWITCH_OFF,
HW_MAD_TX_ULTR_SWITCH_OFF,
HW_MAD_TX_BEACON_SWITCH_OFF,
MAD_AUDIO_INT_DEST_SELECT_REG,
MAD_ULT_INT_DEST_SELECT_REG,
MAD_BEACON_INT_DEST_SELECT_REG,
MAD_CLIP_INT_DEST_SELECT_REG,
VBAT_INT_DEST_SELECT_REG,
MAD_AUDIO_INT_MASK_REG,
MAD_ULT_INT_MASK_REG,
MAD_BEACON_INT_MASK_REG,
MAD_CLIP_INT_MASK_REG,
VBAT_INT_MASK_REG,
MAD_AUDIO_INT_STATUS_REG,
MAD_ULT_INT_STATUS_REG,
MAD_BEACON_INT_STATUS_REG,
MAD_CLIP_INT_STATUS_REG,
VBAT_INT_STATUS_REG,
MAD_AUDIO_INT_CLEAR_REG,
MAD_ULT_INT_CLEAR_REG,
MAD_BEACON_INT_CLEAR_REG,
MAD_CLIP_INT_CLEAR_REG,
VBAT_INT_CLEAR_REG,
SB_PGD_PORT_TX_WATERMARK_N,
SB_PGD_PORT_TX_ENABLE_N,
SB_PGD_PORT_RX_WATERMARK_N,
SB_PGD_PORT_RX_ENABLE_N,
SB_PGD_TX_PORTn_MULTI_CHNL_0,
SB_PGD_TX_PORTn_MULTI_CHNL_1,
SB_PGD_RX_PORTn_MULTI_CHNL_0,
SB_PGD_RX_PORTn_MULTI_CHNL_1,
AANC_FF_GAIN_ADAPTIVE,
AANC_FFGAIN_ADAPTIVE_EN,
AANC_GAIN_CONTROL,
SPKR_CLIP_PIPE_BANK_SEL,
SPKR_CLIPDET_VAL0,
SPKR_CLIPDET_VAL1,
SPKR_CLIPDET_VAL2,
SPKR_CLIPDET_VAL3,
SPKR_CLIPDET_VAL4,
SPKR_CLIPDET_VAL5,
SPKR_CLIPDET_VAL6,
SPKR_CLIPDET_VAL7,
VBAT_RELEASE_INT_DEST_SELECT_REG,
VBAT_RELEASE_INT_MASK_REG,
VBAT_RELEASE_INT_STATUS_REG,
VBAT_RELEASE_INT_CLEAR_REG,
MAD2_CLIP_INT_DEST_SELECT_REG,
MAD2_CLIP_INT_MASK_REG,
MAD2_CLIP_INT_STATUS_REG,
MAD2_CLIP_INT_CLEAR_REG,
SPKR2_CLIP_PIPE_BANK_SEL,
SPKR2_CLIPDET_VAL0,
SPKR2_CLIPDET_VAL1,
SPKR2_CLIPDET_VAL2,
SPKR2_CLIPDET_VAL3,
SPKR2_CLIPDET_VAL4,
SPKR2_CLIPDET_VAL5,
SPKR2_CLIPDET_VAL6,
SPKR2_CLIPDET_VAL7,
MAX_CFG_REGISTERS,
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/types.h>
#include "core.h"
#ifndef __MFD_WCD9XXX_IRQ_H
#define __MFD_WCD9XXX_IRQ_H
#ifdef CONFIG_WCD9XXX_CODEC_CORE
bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *wcd9xxx_res);
int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq,
irq_handler_t handler, const char *name, void *data);
void wcd9xxx_free_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq, void *data);
void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq);
void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq);
void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq);
int wcd9xxx_irq_init(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *wcd9xxx_res);
int wcd9xxx_irq_drv_init(void);
void wcd9xxx_irq_drv_exit(void);
#else
bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res)
{
return false;
}
void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq,
irq_handler_t handler, const char *name, void *data)
{
return 0;
}
void wcd9xxx_free_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq, void *data)
{
}
void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
{
}
void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq)
{
}
void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq)
{
}
int wcd9xxx_irq_init(struct wcd9xxx_core_resource *wcd9xxx_res)
{
return 0;
}
void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
int wcd9xxx_irq_drv_init(void)
{
return 0;
}
void wcd9xxx_irq_drv_exit(void)
{
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_REGMAP_
#define _WCD9XXX_REGMAP_
#include <linux/regmap.h>
#include "core.h"
typedef int (*regmap_patch_fptr)(struct regmap *regmap, int version);
extern struct regmap_config wcd934x_regmap_config;
extern int wcd934x_regmap_register_patch(struct regmap *regmap,
int version);
extern struct regmap_config wcd9335_regmap_config;
extern int wcd9335_regmap_register_patch(struct regmap *regmap,
int version);
static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
{
struct regmap_config *regmap_config;
switch (type) {
case WCD934X:
regmap_config = &wcd934x_regmap_config;
break;
case WCD9335:
regmap_config = &wcd9335_regmap_config;
break;
default:
regmap_config = NULL;
break;
};
return regmap_config;
}
static inline regmap_patch_fptr wcd9xxx_get_regmap_reg_patch(int type)
{
regmap_patch_fptr apply_patch;
switch (type) {
case WCD9335:
apply_patch = wcd9335_regmap_register_patch;
break;
case WCD934X:
apply_patch = wcd934x_regmap_register_patch;
break;
default:
apply_patch = NULL;
break;
}
return apply_patch;
}
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_COMMON_V2_H__
#define __WCD9XXX_COMMON_V2_H__
#include "wcd9xxx_registers.h"
#include "core.h"
enum wcd_clock_type {
WCD_CLK_OFF,
WCD_CLK_RCO,
WCD_CLK_MCLK,
};
enum {
SIDO_SOURCE_INTERNAL,
SIDO_SOURCE_RCO_BG,
};
struct wcd_resmgr_cb {
int (*cdc_rco_ctrl)(struct snd_soc_component *component, bool enable);
};
struct wcd9xxx_resmgr_v2 {
struct snd_soc_component *component;
struct wcd9xxx_core_resource *core_res;
int master_bias_users;
int clk_mclk_users;
int clk_rco_users;
struct mutex codec_bg_clk_lock;
struct mutex master_bias_lock;
enum codec_variant codec_type;
enum wcd_clock_type clk_type;
const struct wcd_resmgr_cb *resmgr_cb;
int sido_input_src;
};
#define WCD9XXX_V2_BG_CLK_LOCK(resmgr) \
{ \
struct wcd9xxx_resmgr_v2 *__resmgr = resmgr; \
pr_debug("%s: Acquiring BG_CLK\n", __func__); \
mutex_lock(&__resmgr->codec_bg_clk_lock); \
pr_debug("%s: Acquiring BG_CLK done\n", __func__); \
}
#define WCD9XXX_V2_BG_CLK_UNLOCK(resmgr) \
{ \
struct wcd9xxx_resmgr_v2 *__resmgr = resmgr; \
pr_debug("%s: Releasing BG_CLK\n", __func__); \
mutex_unlock(&__resmgr->codec_bg_clk_lock); \
}
#define WCD9XXX_V2_BG_CLK_ASSERT_LOCKED(resmgr) \
{ \
WARN_ONCE(!mutex_is_locked(&resmgr->codec_bg_clk_lock), \
"%s: BG_CLK lock should have acquired\n", __func__); \
}
int wcd_resmgr_enable_master_bias(struct wcd9xxx_resmgr_v2 *resmgr);
int wcd_resmgr_disable_master_bias(struct wcd9xxx_resmgr_v2 *resmgr);
struct wcd9xxx_resmgr_v2 *wcd_resmgr_init(
struct wcd9xxx_core_resource *core_res,
struct snd_soc_component *component);
void wcd_resmgr_remove(struct wcd9xxx_resmgr_v2 *resmgr);
int wcd_resmgr_post_init(struct wcd9xxx_resmgr_v2 *resmgr,
const struct wcd_resmgr_cb *resmgr_cb,
struct snd_soc_component *component);
int wcd_resmgr_enable_clk_block(struct wcd9xxx_resmgr_v2 *resmgr,
enum wcd_clock_type type);
int wcd_resmgr_disable_clk_block(struct wcd9xxx_resmgr_v2 *resmgr,
enum wcd_clock_type type);
int wcd_resmgr_get_clk_type(struct wcd9xxx_resmgr_v2 *resmgr);
void wcd_resmgr_post_ssr_v2(struct wcd9xxx_resmgr_v2 *resmgr);
void wcd_resmgr_set_sido_input_src_locked(struct wcd9xxx_resmgr_v2 *resmgr,
int sido_src);
void wcd_resmgr_set_sido_input_src(struct wcd9xxx_resmgr_v2 *resmgr,
int sido_src);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_SLIMSLAVE_H_
#define __WCD9XXX_SLIMSLAVE_H_
#include <linux/slimbus/slimbus.h>
#include "core.h"
/*
* client is expected to give port ids in the range of
* 1-10 for pre Taiko Tx ports and 1-16 for Taiko
* 1-7 for pre Taiko Rx ports and 1-16 for Tako,
* we need to add offset for getting the absolute slave
* port id before configuring the HW
*/
#define TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 10
#define TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 16
#define SLIM_MAX_TX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \
TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \
TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 7
#define TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 13
#define SLIM_MAX_RX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS
#define SLIM_MAX_REG_ADDR (0x180 + 4 * (SLIM_MAX_RX_PORTS))
#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \
TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS
#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \
TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 16
#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 31
#define TABLA_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 9
#define TAIKO_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 15
/* below details are taken from SLIMBUS slave SWI */
#define SB_PGD_PORT_BASE 0x000
#define SB_PGD_PORT_CFG_BYTE_ADDR(offset, port_num) \
(SB_PGD_PORT_BASE + offset + (1 * port_num))
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0(port_num) \
(SB_PGD_PORT_BASE + 0x100 + 4*port_num)
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_START_PORT_ID 0
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID 7
#define SB_PGD_TX_PORT_MULTI_CHANNEL_1(port_num) \
(SB_PGD_PORT_BASE + 0x101 + 4*port_num)
#define SB_PGD_TX_PORT_MULTI_CHANNEL_1_START_PORT_ID 8
#define SB_PGD_RX_PORT_MULTI_CHANNEL_0(offset, port_num) \
(SB_PGD_PORT_BASE + offset + (4 * port_num))
/* slave port water mark level
* (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
*/
#define SLAVE_PORT_WATER_MARK_6BYTES 0
#define SLAVE_PORT_WATER_MARK_9BYTES 1
#define SLAVE_PORT_WATER_MARK_12BYTES 2
#define SLAVE_PORT_WATER_MARK_15BYTES 3
#define SLAVE_PORT_WATER_MARK_SHIFT 1
#define SLAVE_PORT_ENABLE 1
#define SLAVE_PORT_DISABLE 0
#define WATER_MARK_VAL \
((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
(SLAVE_PORT_ENABLE))
#define BASE_CH_NUM 128
int wcd9xxx_init_slimslave(struct wcd9xxx *wcd9xxx,
u8 wcd9xxx_pgd_la,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot);
int wcd9xxx_deinit_slimslave(struct wcd9xxx *wcd9xxx);
int wcd9xxx_cfg_slim_sch_rx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list,
unsigned int rate, unsigned int bit_width,
u16 *grph);
int wcd9xxx_cfg_slim_sch_tx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list,
unsigned int rate, unsigned int bit_width,
u16 *grph);
int wcd9xxx_close_slim_sch_rx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_close_slim_sch_tx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_get_channel(struct wcd9xxx *wcd9xxx,
unsigned int *rx_ch,
unsigned int *tx_ch);
int wcd9xxx_get_slave_port(unsigned int ch_num);
int wcd9xxx_disconnect_port(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_rx_vport_validation(u32 port_id,
struct list_head *codec_dai_list);
int wcd9xxx_tx_vport_validation(u32 vtable, u32 port_id,
struct wcd9xxx_codec_dai_data *codec_dai,
u32 num_codec_dais);
#endif /* __WCD9XXX_SLIMSLAVE_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_REGISTERS_H
#define _WCD9XXX_REGISTERS_H
#define WCD9XXX_A_CHIP_CTL (0x00)
#define WCD9XXX_A_CHIP_CTL__POR (0x00000000)
#define WCD9XXX_A_CHIP_STATUS (0x01)
#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04)
#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05)
#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06)
#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07)
#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001)
#define WCD9XXX_A_CHIP_VERSION (0x08)
#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020)
#define WCD9XXX_A_SB_VERSION (0x09)
#define WCD9XXX_A_SB_VERSION__POR (0x00000010)
#define WCD9XXX_A_SLAVE_ID_1 (0x0C)
#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077)
#define WCD9XXX_A_SLAVE_ID_2 (0x0D)
#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066)
#define WCD9XXX_A_SLAVE_ID_3 (0x0E)
#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055)
#define WCD9XXX_A_CDC_CTL (0x80)
#define WCD9XXX_A_CDC_CTL__POR (0x00000000)
#define WCD9XXX_A_LEAKAGE_CTL (0x88)
#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004)
#define WCD9XXX_A_INTR_MODE (0x90)
#define WCD9XXX_A_INTR_MASK0 (0x94)
#define WCD9XXX_A_INTR_STATUS0 (0x98)
#define WCD9XXX_A_INTR_CLEAR0 (0x9C)
#define WCD9XXX_A_INTR_LEVEL0 (0xA0)
#define WCD9XXX_A_INTR_LEVEL1 (0xA1)
#define WCD9XXX_A_INTR_LEVEL2 (0xA2)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
#define WCD9XXX_A_CLK_BUFF_EN1 (0x108)
#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04)
#define WCD9XXX_A_CLK_BUFF_EN2 (0x109)
#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02)
#define WCD9XXX_A_RX_COM_BIAS (0x1A2)
#define WCD9XXX_A_RX_COM_BIAS__POR (0x00)
#define WCD9XXX_A_RC_OSC_FREQ (0x1FA)
#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46)
#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105)
#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16)
#define WCD9XXX_A_RC_OSC_TEST (0x1FB)
#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0)
#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE)
#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0)
#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF)
#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD)
#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF)
#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00)
#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E)
#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00)
#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA)
#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68)
#define WCD9XXX_A_MICB_1_CTL (0x12B)
#define WCD9XXX_A_MICB_1_CTL__POR (0x16)
#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C)
#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_1_MBHC (0x12D)
#define WCD9XXX_A_MICB_1_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E)
#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F)
#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_2_CTL (0x131)
#define WCD9XXX_A_MICB_2_CTL__POR (0x16)
#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132)
#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_2_MBHC (0x133)
#define WCD9XXX_A_MICB_2_MBHC__POR (0x02)
#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134)
#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135)
#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_3_CTL (0x137)
#define WCD9XXX_A_MICB_3_CTL__POR (0x16)
#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138)
#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_3_MBHC (0x139)
#define WCD9XXX_A_MICB_3_MBHC__POR (0x00)
#define WCD9XXX_A_MICB_4_CTL (0x13D)
#define WCD9XXX_A_MICB_4_CTL__POR (0x16)
#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E)
#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_4_MBHC (0x13F)
#define WCD9XXX_A_MICB_4_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129)
#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3)
#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00)
#define WCD9XXX_A_MBHC_HPH (0x1FE)
#define WCD9XXX_A_MBHC_HPH__POR (0x44)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00)
#define WCD9XXX_A_TX_7_MBHC_EN (0x171)
#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C)
#define WCD9XXX_A_PIN_CTL_OE0 (0x010)
#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00)
#define WCD9XXX_A_PIN_CTL_OE1 (0x011)
#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00)
#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128)
#define WCD9XXX_A_LDO_H_MODE_1 (0x110)
#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65)
#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38)
#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F)
#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80)
#define WCD9XXX_A_TX_COM_BIAS (0x14C)
#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0)
#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) /* TAIKO and later */
#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00)
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00)
#define WCD9XXX_A_MAD_ANA_CTRL (0x150)
#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00)
/* Class H related common registers */
#define WCD9XXX_A_BUCK_MODE_1 (0x181)
#define WCD9XXX_A_BUCK_MODE_1__POR (0x21)
#define WCD9XXX_A_BUCK_MODE_2 (0x182)
#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF)
#define WCD9XXX_A_BUCK_MODE_3 (0x183)
#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC)
#define WCD9XXX_A_BUCK_MODE_4 (0x184)
#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A)
#define WCD9XXX_A_BUCK_MODE_5 (0x185)
#define WCD9XXX_A_BUCK_MODE_5__POR (0x00)
#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186)
#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48)
#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187)
#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3)
#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188)
#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82)
#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189)
#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB)
#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A)
#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC)
#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B)
#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A)
#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C)
#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77)
#define WCD9XXX_A_BUCK_TMUX_A_D (0x190)
#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00)
#define WCD9XXX_A_NCP_EN (0x192)
#define WCD9XXX_A_NCP_EN__POR (0xFE)
#define WCD9XXX_A_NCP_STATIC (0x194)
#define WCD9XXX_A_NCP_STATIC__POR (0x28)
#define WCD9XXX_A_NCP_BUCKREF (0x191)
#define WCD9XXX_A_NCP_BUCKREF__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320)
#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4)
#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321)
#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322)
#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23)
#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328)
#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329)
#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00)
#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5)
#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80)
#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD)
#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE)
#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4)
#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5)
#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4)
#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6)
#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A)
#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF)
#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5)
#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00)
#define WCD9XXX_A_NCP_CLK (0x193)
#define WCD9XXX_A_NCP_CLK__POR (0x94)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0)
#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42)
#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6)
#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00)
#define WCD9330_A_LEAKAGE_CTL (0x03C)
#define WCD9330_A_LEAKAGE_CTL__POR (0x04)
#define WCD9330_A_CDC_CTL (0x034)
#define WCD9330_A_CDC_CTL__POR (0x00)
/* Class-H registers for codecs from and above WCD9335 */
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42)
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08)
#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09)
#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608)
#define WCD9XXX_A_ANA_HPH (0x609)
#define WCD9XXX_A_CDC_CLSH_CRC (0xC01)
#define WCD9XXX_FLYBACK_EN (0x6A4)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (0x6A5)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (0x6AF)
#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7)
#define WCD9XXX_HPH_L_EN (0x6D3)
#define WCD9XXX_HPH_R_EN (0x6D6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD)
#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B)
#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04)
#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49)
#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41)
#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C)
/* RX Gain control registers of codecs from and above WCD9335 */
#define WCD9XXX_CDC_RX1_RX_VOL_CTL (0xB59)
#define WCD9XXX_CDC_RX1_RX_VOL_MIX_CTL (0xB5C)
#define WCD9XXX_CDC_RX1_RX_PATH_SEC1 (0xB5E)
#define WCD9XXX_CDC_RX2_RX_VOL_CTL (0xB6D)
#define WCD9XXX_CDC_RX2_RX_VOL_MIX_CTL (0xB70)
#define WCD9XXX_CDC_RX2_RX_PATH_SEC1 (0xB72)
/* Class-H registers for codecs from and above WCD934X */
#define WCD9XXX_HPH_CNP_WG_CTL (0x06cc)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (0x06a8)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (0x0738)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (0x06bf)
#define WCD9XXX_HPH_PA_CTL1 (0x06d1)
#endif

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qcom/opensource/audio-kernel/include/asoc/wcdcal-hwdep.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014, 2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_HWDEP_H__
#define __WCD9XXX_HWDEP_H__
#include <sound/msmcal-hwdep.h>
enum wcd_cal_states {
WCDCAL_UNINITIALISED,
WCDCAL_INITIALISED,
WCDCAL_RECIEVED
};
struct fw_info {
struct firmware_cal *fw[WCD9XXX_MAX_CAL];
DECLARE_BITMAP(cal_bit, WCD9XXX_MAX_CAL);
/* for calibration tracking */
unsigned long wcdcal_state[WCD9XXX_MAX_CAL];
struct mutex lock;
};
struct firmware_cal {
u8 *data;
size_t size;
};
struct snd_soc_codec;
int wcd_cal_create_hwdep(void *fw, int node,
struct snd_soc_component *component);
struct firmware_cal *wcdcal_get_fw_cal(struct fw_info *fw_data,
enum wcd_cal_type type);
#endif /* __WCD9XXX_HWDEP_H__ */