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sm8750: init kernel modules repo

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This commit is contained in:
Sascha Nesterovic
2025-08-11 12:21:01 +02:00
parent 2681143b87
commit facad83b01
8851 changed files with 6894561 additions and 0 deletions
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29
qcom/opensource/audio-kernel/include/asoc/bolero-slave-internal.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* from Slave to bolero events */
enum {
SLV_BOLERO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
SLV_BOLERO_EVT_IMPED_TRUE, /* for imped true */
SLV_BOLERO_EVT_IMPED_FALSE, /* for imped false */
SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
SLV_BOLERO_EVT_BCS_CLK_OFF,
SLV_BOLERO_EVT_RX_PA_GAIN_UPDATE,
SLV_BOLERO_EVT_HPHL_HD2_ENABLE, /* to enable hd2 config for hphl */
SLV_BOLERO_EVT_HPHR_HD2_ENABLE, /* to enable hd2 config for hphr */
};
/* from bolero to SLV events */
enum {
BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR = 1,
BOLERO_SLV_EVT_PA_OFF_PRE_SSR,
BOLERO_SLV_EVT_SSR_DOWN,
BOLERO_SLV_EVT_SSR_UP,
BOLERO_SLV_EVT_PA_ON_POST_FSCLK,
BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB,
BOLERO_SLV_EVT_CLK_NOTIFY,
BOLERO_SLV_EVT_RX_MACRO_PA_ON,
};

553
qcom/opensource/audio-kernel/include/asoc/core.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_TABLA_CORE_H__
#define __MFD_TABLA_CORE_H__
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include "pdata.h"
#define WCD9XXX_MAX_IRQ_REGS 4
#define WCD9XXX_MAX_NUM_IRQS (WCD9XXX_MAX_IRQ_REGS * 8)
#define WCD9XXX_SLIM_NUM_PORT_REG 3
#define TABLA_VERSION_1_0 0
#define TABLA_VERSION_1_1 1
#define TABLA_VERSION_2_0 2
#define TABLA_IS_1_X(ver) \
(((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0)
#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)
#define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"
#define SITAR_VERSION_1P0 0
#define SITAR_VERSION_1P1 1
#define SITAR_IS_1P0(ver) \
((ver == SITAR_VERSION_1P0) ? 1 : 0)
#define SITAR_IS_1P1(ver) \
((ver == SITAR_VERSION_1P1) ? 1 : 0)
#define TAIKO_VERSION_1_0 1
#define TAIKO_IS_1_0(ver) \
((ver == TAIKO_VERSION_1_0) ? 1 : 0)
#define TAPAN_VERSION_1_0 0
#define TAPAN_IS_1_0(ver) \
((ver == TAPAN_VERSION_1_0) ? 1 : 0)
#define TOMTOM_VERSION_1_0 1
#define TOMTOM_IS_1_0(ver) \
((ver == TOMTOM_VERSION_1_0) ? 1 : 0)
#define TASHA_VERSION_1_0 0
#define TASHA_VERSION_1_1 1
#define TASHA_VERSION_2_0 2
#define TASHA_IS_1_0(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_1_0) ? 1 : 0) : 0)
#define TASHA_IS_1_1(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_1_1) ? 1 : 0) : 0)
#define TASHA_IS_2_0(wcd) \
((wcd->type == WCD9335 || wcd->type == WCD9326) ? \
((wcd->version == TASHA_VERSION_2_0) ? 1 : 0) : 0)
/*
* As fine version info cannot be retrieved before tavil probe.
* Define three coarse versions for possible future use before tavil probe.
*/
#define TAVIL_VERSION_1_0 0
#define TAVIL_VERSION_1_1 1
#define TAVIL_VERSION_WCD9340_1_0 2
#define TAVIL_VERSION_WCD9341_1_0 3
#define TAVIL_VERSION_WCD9340_1_1 4
#define TAVIL_VERSION_WCD9341_1_1 5
#define TAVIL_IS_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_1_0 || \
wcd->version == TAVIL_VERSION_WCD9340_1_0 || \
wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_1_1 || \
wcd->version == TAVIL_VERSION_WCD9340_1_1 || \
wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9340_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9340_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9341_1_0(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9341_1_0) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9340_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9340_1_1) ? 1 : 0) : 0)
#define TAVIL_IS_WCD9341_1_1(wcd) \
((wcd->type == WCD934X) ? \
((wcd->version == TAVIL_VERSION_WCD9341_1_1) ? 1 : 0) : 0)
#define IS_CODEC_TYPE(wcd, wcdtype) \
((wcd->type == wcdtype) ? true : false)
#define IS_CODEC_VERSION(wcd, wcdversion) \
((wcd->version == wcdversion) ? true : false)
enum {
CDC_V_1_0,
CDC_V_1_1,
CDC_V_2_0,
};
enum codec_variant {
WCD9XXX,
WCD9330,
WCD9335,
WCD9326,
WCD934X,
};
enum wcd9xxx_slim_slave_addr_type {
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0,
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1,
};
enum wcd9xxx_pm_state {
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE,
WCD9XXX_PM_ASLEEP,
};
enum {
WCD9XXX_INTR_STATUS_BASE = 0,
WCD9XXX_INTR_CLEAR_BASE,
WCD9XXX_INTR_MASK_BASE,
WCD9XXX_INTR_LEVEL_BASE,
WCD9XXX_INTR_CLR_COMMIT,
WCD9XXX_INTR_REG_MAX,
};
enum wcd9xxx_intf_status {
WCD9XXX_INTERFACE_TYPE_PROBING,
WCD9XXX_INTERFACE_TYPE_SLIMBUS,
WCD9XXX_INTERFACE_TYPE_I2C,
};
enum {
/* INTR_REG 0 */
WCD9XXX_IRQ_SLIMBUS = 0,
WCD9XXX_IRQ_MBHC_REMOVAL,
WCD9XXX_IRQ_MBHC_SHORT_TERM,
WCD9XXX_IRQ_MBHC_PRESS,
WCD9XXX_IRQ_MBHC_RELEASE,
WCD9XXX_IRQ_MBHC_POTENTIAL,
WCD9XXX_IRQ_MBHC_INSERTION,
WCD9XXX_IRQ_BG_PRECHARGE,
/* INTR_REG 1 */
WCD9XXX_IRQ_PA1_STARTUP,
WCD9XXX_IRQ_PA2_STARTUP,
WCD9XXX_IRQ_PA3_STARTUP,
WCD9XXX_IRQ_PA4_STARTUP,
WCD9306_IRQ_HPH_PA_OCPR_FAULT = WCD9XXX_IRQ_PA4_STARTUP,
WCD9XXX_IRQ_PA5_STARTUP,
WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9306_IRQ_HPH_PA_OCPL_FAULT = WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
/* INTR_REG 2 */
WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_L_PA_STARTUP,
WCD9XXX_IRQ_HPH_R_PA_STARTUP,
WCD9320_IRQ_EAR_PA_STARTUP,
WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_1,
WCD9330_IRQ_SVASS_ERR_EXCEPTION = WCD9310_NUM_IRQS,
WCD9330_IRQ_MBHC_JACK_SWITCH,
/* INTR_REG 3 */
WCD9XXX_IRQ_MAD_AUDIO,
WCD9XXX_IRQ_MAD_ULTRASOUND,
WCD9XXX_IRQ_MAD_BEACON,
WCD9XXX_IRQ_SPEAKER_CLIPPING,
WCD9320_IRQ_MBHC_JACK_SWITCH,
WCD9306_NUM_IRQS,
WCD9XXX_IRQ_VBAT_MONITOR_ATTACK = WCD9306_NUM_IRQS,
WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
WCD9XXX_NUM_IRQS,
/* WCD9330 INTR1_REG 3*/
WCD9330_IRQ_SVASS_ENGINE = WCD9XXX_IRQ_MAD_AUDIO,
WCD9330_IRQ_MAD_AUDIO,
WCD9330_IRQ_MAD_ULTRASOUND,
WCD9330_IRQ_MAD_BEACON,
WCD9330_IRQ_SPEAKER1_CLIPPING,
WCD9330_IRQ_SPEAKER2_CLIPPING,
WCD9330_IRQ_VBAT_MONITOR_ATTACK,
WCD9330_IRQ_VBAT_MONITOR_RELEASE,
WCD9330_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_2 = WCD9330_NUM_IRQS,
};
enum {
TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
TAPAN_NUM_IRQS = WCD9306_NUM_IRQS,
TOMTOM_NUM_IRQS = WCD9330_NUM_IRQS,
};
struct intr_data {
int intr_num;
bool clear_first;
};
struct wcd9xxx_core_resource {
struct mutex irq_lock;
struct mutex nested_irq_lock;
enum wcd9xxx_pm_state pm_state;
struct mutex pm_lock;
/* pm_wq notifies change of pm_state */
wait_queue_head_t pm_wq;
struct pm_qos_request pm_qos_req;
int wlock_holders;
/* holds the table of interrupts per codec */
const struct intr_data *intr_table;
int intr_table_size;
unsigned int irq_base;
unsigned int irq;
u8 irq_masks_cur[WCD9XXX_MAX_IRQ_REGS];
u8 irq_masks_cache[WCD9XXX_MAX_IRQ_REGS];
bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
int num_irqs;
int num_irq_regs;
u16 intr_reg[WCD9XXX_INTR_REG_MAX];
struct regmap *wcd_core_regmap;
/* Pointer to parent container data structure */
void *parent;
struct device *dev;
struct irq_domain *domain;
};
/*
* data structure for Slimbus and I2S channel.
* Some of fields are only used in smilbus mode
*/
struct wcd9xxx_ch {
u32 sph; /* share channel handle - slimbus only */
u32 ch_num; /*
* vitrual channel number, such as 128 -144.
* apply for slimbus only
*/
u16 ch_h; /* chanel handle - slimbus only */
u16 port; /*
* tabla port for RX and TX
* such as 0-9 for TX and 10 -16 for RX
* apply for both i2s and slimbus
*/
u16 shift; /*
* shift bit for RX and TX
* apply for both i2s and slimbus
*/
struct list_head list; /*
* channel link list
* apply for both i2s and slimbus
*/
};
struct wcd9xxx_codec_dai_data {
u32 rate; /* sample rate */
u32 bit_width; /* sit width 16,24,32 */
struct list_head wcd9xxx_ch_list; /* channel list */
u16 grph; /* slimbus group handle */
unsigned long ch_mask;
wait_queue_head_t dai_wait;
bool bus_down_in_recovery;
};
#define WCD9XXX_CH(xport, xshift) \
{.port = xport, .shift = xshift}
enum wcd9xxx_chipid_major {
TABLA_MAJOR = cpu_to_le16(0x100),
SITAR_MAJOR = cpu_to_le16(0x101),
TAIKO_MAJOR = cpu_to_le16(0x102),
TAPAN_MAJOR = cpu_to_le16(0x103),
TOMTOM_MAJOR = cpu_to_le16(0x105),
TASHA_MAJOR = cpu_to_le16(0x0),
TASHA2P0_MAJOR = cpu_to_le16(0x107),
TAVIL_MAJOR = cpu_to_le16(0x108),
};
enum codec_power_states {
WCD_REGION_POWER_COLLAPSE_REMOVE,
WCD_REGION_POWER_COLLAPSE_BEGIN,
WCD_REGION_POWER_DOWN,
};
enum wcd_power_regions {
WCD9XXX_DIG_CORE_REGION_1,
WCD9XXX_MAX_PWR_REGIONS,
};
struct wcd9xxx_codec_type {
u16 id_major;
u16 id_minor;
struct mfd_cell *dev;
int size;
int num_irqs;
int version; /* -1 to retrieve version from chip version register */
enum wcd9xxx_slim_slave_addr_type slim_slave_type;
u16 i2c_chip_status;
const struct intr_data *intr_tbl;
int intr_tbl_size;
u16 intr_reg[WCD9XXX_INTR_REG_MAX];
};
struct wcd9xxx_power_region {
enum codec_power_states power_state;
u16 pwr_collapse_reg_min;
u16 pwr_collapse_reg_max;
};
struct wcd9xxx {
struct device *dev;
struct slim_device *slim;
struct slim_device *slim_slave;
struct mutex io_lock;
struct mutex xfer_lock;
struct mutex reset_lock;
u8 version;
int reset_gpio;
struct device_node *wcd_rst_np;
int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *dest, bool interface_reg);
int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src, bool interface_reg);
int (*multi_reg_write)(struct wcd9xxx *wcd9xxx, const void *data,
size_t count);
int (*dev_down)(struct wcd9xxx *wcd9xxx);
int (*post_reset)(struct wcd9xxx *wcd9xxx);
void *ssr_priv;
bool dev_up;
u32 num_of_supplies;
struct regulator_bulk_data *supplies;
struct wcd9xxx_core_resource core_res;
u16 id_minor;
u16 id_major;
/* Slimbus or I2S port */
u32 num_rx_port;
u32 num_tx_port;
struct wcd9xxx_ch *rx_chs;
struct wcd9xxx_ch *tx_chs;
u32 mclk_rate;
enum codec_variant type;
struct regmap *regmap;
struct wcd9xxx_codec_type *codec_type;
bool prev_pg_valid;
u8 prev_pg;
u8 avoid_cdc_rstlow;
struct wcd9xxx_power_region *wcd9xxx_pwr[WCD9XXX_MAX_PWR_REGIONS];
};
struct wcd9xxx_reg_val {
unsigned short reg; /* register address */
u8 *buf; /* buffer to be written to reg. addr */
int bytes; /* number of bytes to be written */
};
#ifdef CONFIG_WCD9XXX_CODEC_CORE
int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val);
int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src);
int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
u32 bw_ops, bool commit);
int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states,
enum wcd_power_regions);
int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
enum wcd_power_regions);
int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg);
int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_reg_val *bulk_reg,
unsigned int size, bool interface);
int wcd9xxx_vote_ondemand_regulator(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_pdata *pdata,
const char *supply_name,
bool enable);
extern int wcd9xxx_core_res_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
int num_irqs, int num_irq_regs, struct regmap *wcd_regmap);
extern void wcd9xxx_core_res_deinit(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_core_res_suspend(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
pm_message_t pmesg);
extern int wcd9xxx_core_res_resume(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_core_irq_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res);
extern int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
unsigned int irq,
unsigned int irq_base);
extern enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
extern void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status);
extern enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
enum wcd9xxx_pm_state o,
enum wcd9xxx_pm_state n);
static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
}
int wcd9xxx_init(void);
void wcd9xxx_exit(void);
#else
static inline int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg)
{
return 0;
}
static inline int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val)
{
return 0;
}
static inline int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la)
{
return 0;
}
static inline int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src)
{
return 0;
}
static inline int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
u32 bw_ops, bool commit)
{
return 0;
}
static inline int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx, enum codec_power_states
cdc_power_state, enum wcd_power_regions pwr_region)
{
return 0;
}
static inline int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
enum wcd_power_regions pwr_region)
{
return 0;
}
static inline int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
{
return 0;
}
static inline int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_reg_val *bulk_reg,
unsigned int size, bool interface)
{
return 0;
}
static inline int wcd9xxx_core_res_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
int num_irqs, int num_irq_regs, struct regmap *wcd_regmap)
{
return 0;
}
static inline void wcd9xxx_core_res_deinit(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
}
static inline int wcd9xxx_core_res_suspend(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
pm_message_t pmesg)
{
return 0;
}
static inline int wcd9xxx_core_res_resume(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
return 0;
}
static inline int wcd9xxx_core_irq_init(
struct wcd9xxx_core_resource *wcd9xxx_core_res)
{
return 0;
}
static inline int wcd9xxx_assign_irq(struct wcd9xxx_core_resource *wcd9xxx_core_res,
unsigned int irq,
unsigned int irq_base)
{
return 0;
}
static inline enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void)
{
return 0;
}
static inline void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status int_state)
{
}
static inline enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
struct wcd9xxx_core_resource *wcd9xxx_core_res,
enum wcd9xxx_pm_state o,
enum wcd9xxx_pm_state n)
{
return 0;
}
static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
}
static inline int wcd9xxx_init(void)
{
return 0;
}
static inline void wcd9xxx_exit(void)
{
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __CPE_CORE_H__
#define __CPE_CORE_H__
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/dma-mapping.h>
#include <audio/sound/lsm_params.h>
enum {
CMD_INIT_STATE = 0,
CMD_SENT,
CMD_RESP_RCVD,
};
enum wcd_cpe_event {
WCD_CPE_PRE_ENABLE = 1,
WCD_CPE_POST_ENABLE,
WCD_CPE_PRE_DISABLE,
WCD_CPE_POST_DISABLE,
};
struct wcd_cpe_afe_port_cfg {
u8 port_id;
u16 bit_width;
u16 num_channels;
u32 sample_rate;
};
struct lsm_out_fmt_cfg {
u8 format;
u8 pack_mode;
u8 data_path_events;
u8 transfer_mode;
};
struct lsm_hw_params {
u32 sample_rate;
u16 num_chs;
u16 bit_width;
};
struct cpe_lsm_session {
/* sound model related */
void *snd_model_data;
u8 *conf_levels;
void *cmi_reg_handle;
/* Clients private data */
void *priv_d;
void (*event_cb)(void *priv_data,
u8 detect_status,
u8 size, u8 *payload);
struct completion cmd_comp;
struct wcd_cpe_afe_port_cfg afe_port_cfg;
struct wcd_cpe_afe_port_cfg afe_out_port_cfg;
struct mutex lsm_lock;
u32 snd_model_size;
u32 lsm_mem_handle;
u16 cmd_err_code;
u8 id;
u8 num_confidence_levels;
u16 afe_out_port_id;
struct task_struct *lsm_lab_thread;
bool started;
u32 lab_enable;
struct lsm_out_fmt_cfg out_fmt_cfg;
bool is_topology_used;
};
struct wcd_cpe_afe_ops {
int (*afe_set_params)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg,
bool afe_mad_ctl);
int (*afe_port_start)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_stop)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_suspend)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_resume)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
int (*afe_port_cmd_cfg)(void *core_handle,
struct wcd_cpe_afe_port_cfg *cfg);
};
struct wcd_cpe_lsm_ops {
struct cpe_lsm_session *(*lsm_alloc_session)
(void *core_handle, void *lsm_priv_d,
void (*event_cb)(void *priv_data,
u8 detect_status,
u8 size, u8 *payload));
int (*lsm_dealloc_session)
(void *core_handle, struct cpe_lsm_session *session);
int (*lsm_open_tx)(void *core_handle,
struct cpe_lsm_session *session, u16 app_id,
u16 sample_rate);
int (*lsm_close_tx)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_shmem_alloc)(void *core_handle,
struct cpe_lsm_session *session, u32 size);
int (*lsm_shmem_dealloc)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_register_snd_model)(void *core_handle,
struct cpe_lsm_session *session,
enum lsm_detection_mode,
bool detect_failure);
int (*lsm_deregister_snd_model)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_get_afe_out_port_id)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_start)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_stop)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_lab_control)(void *core_handle,
struct cpe_lsm_session *session,
bool enable);
int (*lab_ch_setup)(void *core_handle,
struct cpe_lsm_session *session,
enum wcd_cpe_event event);
int (*lsm_set_data)(void *core_handle,
struct cpe_lsm_session *session,
enum lsm_detection_mode detect_mode,
bool detect_failure);
int (*lsm_set_fmt_cfg)(void *core_handle,
struct cpe_lsm_session *session);
int (*lsm_set_one_param)(void *core_handle,
struct cpe_lsm_session *session,
struct lsm_params_info *p_info,
void *data, uint32_t param_type);
void (*lsm_get_snd_model_offset)
(void *core_handle, struct cpe_lsm_session *session,
size_t *offset);
int (*lsm_set_media_fmt_params)(void *core_handle,
struct cpe_lsm_session *session,
struct lsm_hw_params *param);
int (*lsm_set_port)(void *core_handle,
struct cpe_lsm_session *session, void *data);
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD_CPE)
int wcd_cpe_get_lsm_ops(struct wcd_cpe_lsm_ops *lsm_ops);
int wcd_cpe_get_afe_ops(struct wcd_cpe_afe_ops *afe_ops);
void *wcd_cpe_get_core_handle(struct snd_soc_component *component);
#else /* CONFIG_SND_SOC_WCD_CPE */
static inline int wcd_cpe_get_lsm_ops(struct wcd_cpe_lsm_ops *lsm_ops)
{
return 0;
}
static inline int wcd_cpe_get_afe_ops(struct wcd_cpe_afe_ops *afe_ops)
{
return 0;
}
static inline void *wcd_cpe_get_core_handle(struct snd_soc_component *component)
{
return NULL;
}
#endif /* CONFIG_SND_SOC_WCD_CPE */
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_CDC_PINCTRL_H_
#define __MFD_CDC_PINCTRL_H_
#include <linux/types.h>
#include <linux/of.h>
#if IS_ENABLED(CONFIG_MSM_CDC_PINCTRL)
extern int msm_cdc_pinctrl_select_sleep_state(struct device_node *np);
extern int msm_cdc_pinctrl_select_active_state(struct device_node *np);
extern int msm_cdc_pinctrl_select_alt_active_state(struct device_node *np);
extern int msm_cdc_pinctrl_get_state(struct device_node *np);
extern int msm_cdc_get_gpio_state(struct device_node *np);
extern int msm_cdc_pinctrl_set_wakeup_capable(struct device_node *np,
bool enable);
int msm_cdc_pinctrl_drv_init(void);
void msm_cdc_pinctrl_drv_exit(void);
#else
int msm_cdc_pinctrl_select_sleep_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_select_active_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_select_alt_active_state(struct device_node *np)
{
return 0;
}
int msm_cdc_get_gpio_state(struct device_node *np)
{
return 0;
}
int msm_cdc_pinctrl_drv_init(void)
{
return 0;
}
void msm_cdc_pinctrl_drv_exit(void)
{
}
int msm_cdc_pinctrl_get_state(struct device_node *np)
{
return true;
}
static int msm_cdc_pinctrl_set_wakeup_capable(struct device_node *np,
bool enable)
{
return 0;
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016, 2018-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __CODEC_POWER_SUPPLY_H__
#define __CODEC_POWER_SUPPLY_H__
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
struct cdc_regulator {
const char *name;
int min_uV;
int max_uV;
int optimum_uA;
bool ondemand;
bool lpm_supported;
bool rem_supported;
bool vote;
struct regulator *regulator;
};
struct cdc_wcd_supply {
const char *name;
struct device *dev;
struct snd_soc_component *component;
};
extern int msm_cdc_get_power_supplies(struct device *dev,
struct cdc_regulator **cdc_vreg,
int *total_num_supplies);
extern bool msm_cdc_is_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern bool msm_cdc_supply_supports_retention_mode(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern bool msm_cdc_check_supply_vote(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_disable_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_enable_ondemand_supply(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name);
extern int msm_cdc_disable_static_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_release_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_enable_static_supplies(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_set_supplies_lpm_mode(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies,
bool flag);
extern int msm_cdc_init_supplies(struct device *dev,
struct regulator_bulk_data **supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies);
extern int msm_cdc_init_supplies_v2(struct device *dev,
struct regulator_bulk_data **supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies,
u32 vote_regulator_on_demand);
int msm_cdc_init_wcd_supply(struct device_node *np, const char *name,
struct cdc_wcd_supply *cdc_supply);
int msm_cdc_enable_wcd_supply(struct cdc_wcd_supply *cdc_supply, bool enable);
extern int msm_cdc_set_supply_min_voltage(struct device *dev,
struct regulator_bulk_data *supplies,
struct cdc_regulator *cdc_vreg,
int num_supplies, char *supply_name,
int vval_min, bool override_min_vol);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __MFD_WCD9XXX_PDATA_H__
#define __MFD_WCD9XXX_PDATA_H__
#if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE)
#include <linux/slimbus/slimbus.h>
#endif
#include "msm-cdc-supply.h"
#define MICBIAS_EXT_BYP_CAP 0x00
#define MICBIAS_NO_EXT_BYP_CAP 0x01
#define SITAR_LDOH_1P95_V 0x0
#define SITAR_LDOH_2P35_V 0x1
#define SITAR_LDOH_2P75_V 0x2
#define SITAR_LDOH_2P85_V 0x3
#define SITAR_CFILT1_SEL 0x0
#define SITAR_CFILT2_SEL 0x1
#define SITAR_CFILT3_SEL 0x2
#define WCD9XXX_LDOH_1P95_V 0x0
#define WCD9XXX_LDOH_2P35_V 0x1
#define WCD9XXX_LDOH_2P75_V 0x2
#define WCD9XXX_LDOH_2P85_V 0x3
#define WCD9XXX_LDOH_3P0_V 0x3
#define TABLA_LDOH_1P95_V 0x0
#define TABLA_LDOH_2P35_V 0x1
#define TABLA_LDOH_2P75_V 0x2
#define TABLA_LDOH_2P85_V 0x3
#define TABLA_CFILT1_SEL 0x0
#define TABLA_CFILT2_SEL 0x1
#define TABLA_CFILT3_SEL 0x2
#define MAX_AMIC_CHANNEL 7
#define TABLA_OCP_300_MA 0x0
#define TABLA_OCP_350_MA 0x2
#define TABLA_OCP_365_MA 0x3
#define TABLA_OCP_150_MA 0x4
#define TABLA_OCP_190_MA 0x6
#define TABLA_OCP_220_MA 0x7
#define TABLA_DCYCLE_255 0x0
#define TABLA_DCYCLE_511 0x1
#define TABLA_DCYCLE_767 0x2
#define TABLA_DCYCLE_1023 0x3
#define TABLA_DCYCLE_1279 0x4
#define TABLA_DCYCLE_1535 0x5
#define TABLA_DCYCLE_1791 0x6
#define TABLA_DCYCLE_2047 0x7
#define TABLA_DCYCLE_2303 0x8
#define TABLA_DCYCLE_2559 0x9
#define TABLA_DCYCLE_2815 0xA
#define TABLA_DCYCLE_3071 0xB
#define TABLA_DCYCLE_3327 0xC
#define TABLA_DCYCLE_3583 0xD
#define TABLA_DCYCLE_3839 0xE
#define TABLA_DCYCLE_4095 0xF
#define WCD9XXX_MCLK_CLK_12P288MHZ 12288000
#define WCD9XXX_MCLK_CLK_9P6HZ 9600000
/* Only valid for 9.6 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_600KHZ 600000
#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
#define WCD9XXX_DMIC_SAMPLE_RATE_3P2MHZ 3200000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
/* Only valid for 12.288 MHz mclk */
#define WCD9XXX_DMIC_SAMPLE_RATE_768KHZ 768000
#define WCD9XXX_DMIC_SAMPLE_RATE_2P048MHZ 2048000
#define WCD9XXX_DMIC_SAMPLE_RATE_3P072MHZ 3072000
#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
#define WCD9XXX_DMIC_SAMPLE_RATE_6P144MHZ 6144000
#define WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED 0
#define WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED 0
struct wcd9xxx_amic {
/*legacy mode, txfe_enable and txfe_buff take 7 input
* each bit represent the channel / TXFE number
* and numbered as below
* bit 0 = channel 1 / TXFE1_ENABLE / TXFE1_BUFF
* bit 1 = channel 2 / TXFE2_ENABLE / TXFE2_BUFF
* ...
* bit 7 = channel 7 / TXFE7_ENABLE / TXFE7_BUFF
*/
u8 legacy_mode:MAX_AMIC_CHANNEL;
u8 txfe_enable:MAX_AMIC_CHANNEL;
u8 txfe_buff:MAX_AMIC_CHANNEL;
u8 use_pdata:MAX_AMIC_CHANNEL;
};
/* Each micbias can be assigned to one of three cfilters
* Vbatt_min >= .15V + ldoh_v
* ldoh_v >= .15v + cfiltx_mv
* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
*/
struct wcd9xxx_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv; /* in mv */
u32 cfilt2_mv; /* in mv */
u32 cfilt3_mv; /* in mv */
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb4_mv;
/* Different WCD9xxx series codecs may not
* have 4 mic biases. If a codec has fewer
* mic biases, some of these properties will
* not be used.
*/
u8 bias1_cfilt_sel;
u8 bias2_cfilt_sel;
u8 bias3_cfilt_sel;
u8 bias4_cfilt_sel;
u8 bias1_cap_mode;
u8 bias2_cap_mode;
u8 bias3_cap_mode;
u8 bias4_cap_mode;
bool bias2_is_headset_only;
};
struct wcd9xxx_ocp_setting {
unsigned int use_pdata:1; /* 0 - use sys default as recommended */
unsigned int num_attempts:4; /* up to 15 attempts */
unsigned int run_time:4; /* in duty cycle */
unsigned int wait_time:4; /* in duty cycle */
unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
};
#define WCD9XXX_MAX_REGULATOR 9
/*
* format : TABLA_<POWER_SUPPLY_PIN_NAME>_CUR_MAX
*
* <POWER_SUPPLY_PIN_NAME> from Tabla objective spec
*/
#define WCD9XXX_CDC_VDDA_CP_CUR_MAX 500000
#define WCD9XXX_CDC_VDDA_RX_CUR_MAX 20000
#define WCD9XXX_CDC_VDDA_TX_CUR_MAX 20000
#define WCD9XXX_VDDIO_CDC_CUR_MAX 5000
#define WCD9XXX_VDDD_CDC_D_CUR_MAX 5000
#define WCD9XXX_VDDD_CDC_A_CUR_MAX 5000
#define WCD9XXX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
#define WCD9XXX_VDD_SPKDRV2_NAME "cdc-vdd-spkdrv-2"
struct wcd9xxx_regulator {
const char *name;
int min_uV;
int max_uV;
int optimum_uA;
bool ondemand;
struct regulator *regulator;
};
struct wcd9xxx_pdata {
int irq;
int irq_base;
int num_irqs;
int reset_gpio;
bool has_buck_vsel_gpio;
bool has_micb_supply_en_gpio;
struct device_node *buck_vsel_ctl_np;
struct device_node *micb_en_ctl;
struct device_node *wcd_rst_np;
struct wcd9xxx_amic amic_settings;
#if IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE)
struct slim_device slimbus_slave_device;
#endif
struct wcd9xxx_micbias_setting micbias;
struct wcd9xxx_ocp_setting ocp;
struct cdc_regulator *regulator;
int num_supplies;
u32 mclk_rate;
u32 dmic_sample_rate;
u32 mad_dmic_sample_rate;
u32 ecpp_dmic_sample_rate;
u32 dmic_clk_drv;
u16 use_pinctrl;
u32 vote_regulator_on_demand;
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2019,, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD_CLSH
#define _WCD_CLSH
#include <linux/stringify.h>
#define WCD_CLSH_STRINGIFY(s) __stringify(s)
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_CLSH_EVENT_PRE_DAC 0x01
#define WCD_CLSH_EVENT_POST_PA 0x02
/*
* Basic states for Class H state machine.
* represented as a bit mask within a u8 data type
* bit 0: EAR mode
* bit 1: HPH Left mode
* bit 2: HPH Right mode
* bit 3: AUX mode
*/
#define WCD_CLSH_STATE_IDLE 0x00
#define WCD_CLSH_STATE_EAR (0x01 << 0)
#define WCD_CLSH_STATE_HPHL (0x01 << 1)
#define WCD_CLSH_STATE_HPHR (0x01 << 2)
#define WCD_CLSH_STATE_AUX (0x01 << 3)
/*
* Though number of CLSH states is 4, max state should be 5
* because state array index starts from 1.
*/
#define WCD_CLSH_STATE_MAX 5
#define NUM_CLSH_STATES (0x01 << WCD_CLSH_STATE_MAX)
/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
#define WCD_CLSH_STATE_HPH_ST (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_HPHR)
#define WCD_CLSH_STATE_HPHL_AUX (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPHR_AUX (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPH_ST_AUX (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_EAR_AUX (WCD_CLSH_STATE_EAR | \
WCD_CLSH_STATE_AUX)
#define WCD_CLSH_STATE_HPHL_EAR (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPHR_EAR (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPH_ST_EAR (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_EAR)
#define WCD9XXX_BASE_ADDRESS 0x3000
#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008)
#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009)
#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098)
#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF)
#define WCD9XXX_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7)
#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138)
enum {
CLS_H_NORMAL = 0, /* Class-H Default */
CLS_H_HIFI, /* Class-H HiFi */
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB Low HIFI*/
CLS_H_LOHIFI, /* LoHIFI */
CLS_H_ULP, /* Ultra Low power */
CLS_AB_HIFI, /* Class-AB */
CLS_AB_LP, /* Class-AB Low Power */
CLS_AB_LOHIFI, /* Class-AB Low HIFI */
CLS_NONE, /* None of the above modes */
};
/* Class H data that the codec driver will maintain */
struct wcd_clsh_cdc_info {
u8 state;
int flyback_users;
int buck_users;
int interpolator_modes[WCD_CLSH_STATE_MAX];
};
#ifdef CONFIG_SND_SOC_WCD9XXX_V2
extern void wcd_cls_h_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_info *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode);
extern void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh);
extern void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
int mode);
#else
static inline void wcd_cls_h_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_info *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode)
{
}
static inline extern void wcd_cls_h_init(struct wcd_clsh_cdc_info *clsh)
{
}
static inline extern void wcd_clsh_set_hph_mode(struct snd_soc_component *component,
int mode)
{
}
#endif /* CONFIG_SND_SOC_WCD9XXX_V2 */
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD_IRQ_H_
#define __WCD_IRQ_H_
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
struct wcd_irq_info {
struct regmap_irq_chip *wcd_regmap_irq_chip;
char *codec_name;
struct regmap *regmap;
struct regmap_irq_chip_data *irq_chip;
struct device *dev;
};
#if (IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE) | \
IS_ENABLED(CONFIG_WCD9XXX_CODEC_CORE_V2))
int wcd_irq_init(struct wcd_irq_info *irq_info, struct irq_domain **virq);
int wcd_irq_exit(struct wcd_irq_info *irq_info, struct irq_domain *virq);
int wcd_request_irq(struct wcd_irq_info *irq_info, int irq, const char *name,
irq_handler_t handler, void *data);
void wcd_free_irq(struct wcd_irq_info *irq_info, int irq, void *data);
void wcd_enable_irq(struct wcd_irq_info *irq_info, int irq);
void wcd_disable_irq(struct wcd_irq_info *irq_info, int irq);
#else
static inline int wcd_irq_init(struct wcd_irq_info *irq_info,
struct irq_domain **virq)
{
return 0;
};
static inline int wcd_irq_exit(struct wcd_irq_info *irq_info,
struct irq_domain *virq)
{
return 0;
};
static inline int wcd_request_irq(struct wcd_irq_info *irq_info,
int irq, const char *name,
irq_handler_t handler, void *data)
{
return 0;
};
static inline void wcd_free_irq(struct wcd_irq_info *irq_info, int irq, void *data);
{
};
static inline void wcd_enable_irq(struct wcd_irq_info *irq_info, int irq);
{
};
static inline void wcd_disable_irq(struct wcd_irq_info *irq_info, int irq);
{
};
#endif
#endif /* __WCD_IRQ_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD_MBHC_V2_API_H__
#define __WCD_MBHC_V2_API_H__
#include "wcd-mbhc-v2.h"
#if IS_ENABLED(CONFIG_SND_SOC_WCD_MBHC)
int wcd_mbhc_start(struct wcd_mbhc *mbhc,
struct wcd_mbhc_config *mbhc_cfg);
void wcd_mbhc_stop(struct wcd_mbhc *mbhc);
int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_component *component,
const struct wcd_mbhc_cb *mbhc_cb,
const struct wcd_mbhc_intr *mbhc_cdc_intr_ids,
struct wcd_mbhc_register *wcd_mbhc_regs,
bool impedance_det_en);
int wcd_mbhc_get_impedance(struct wcd_mbhc *mbhc, uint32_t *zl,
uint32_t *zr);
void wcd_mbhc_deinit(struct wcd_mbhc *mbhc);
#else
static inline void wcd_mbhc_stop(struct wcd_mbhc *mbhc)
{
}
int wcd_mbhc_init(struct wcd_mbhc *mbhc, struct snd_soc_component *component,
const struct wcd_mbhc_cb *mbhc_cb,
const struct wcd_mbhc_intr *mbhc_cdc_intr_ids,
struct wcd_mbhc_register *wcd_mbhc_regs,
bool impedance_det_en)
{
return 0;
}
static inline int wcd_mbhc_start(struct wcd_mbhc *mbhc,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline int wcd_mbhc_get_impedance(struct wcd_mbhc *mbhc,
uint32_t *zl,
uint32_t *zr)
{
*zl = 0;
*zr = 0;
return -EINVAL;
}
static inline void wcd_mbhc_deinit(struct wcd_mbhc *mbhc)
{
}
#endif
#endif /* __WCD_MBHC_V2_API_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __WCD_MBHC_V2_H__
#define __WCD_MBHC_V2_H__
#include <linux/wait.h>
#include <linux/stringify.h>
#include <linux/power_supply.h>
#include <linux/extcon.h>
#include <linux/extcon-provider.h>
#include "wcdcal-hwdep.h"
#include <sound/jack.h>
#define TOMBAK_MBHC_NC 0
#define TOMBAK_MBHC_NO 1
#define WCD_MBHC_DEF_BUTTONS 8
#define WCD_MBHC_KEYCODE_NUM 8
#define WCD_MBHC_USLEEP_RANGE_MARGIN_US 100
#define WCD_MBHC_THR_HS_MICB_MV 2700
/* z value defined in Ohms */
#define WCD_MONO_HS_MIN_THR 2
#define WCD_MBHC_STRINGIFY(s) __stringify(s)
#define WCD_MBHC_REGISTER(rid, rreg, rmask, rshift, rinvert) \
{ .id = rid, .reg = rreg, .mask = rmask, .offset = rshift, .invert = rinvert }
#define WCD_MBHC_RSC_LOCK(mbhc) \
{ \
pr_debug("%s: Acquiring BCL\n", __func__); \
mutex_lock(&mbhc->codec_resource_lock); \
pr_debug("%s: Acquiring BCL done\n", __func__); \
}
#define WCD_MBHC_RSC_UNLOCK(mbhc) \
{ \
pr_debug("%s: Release BCL\n", __func__); \
mutex_unlock(&mbhc->codec_resource_lock); \
}
#define WCD_MBHC_RSC_ASSERT_LOCKED(mbhc) \
{ \
WARN_ONCE(!mutex_is_locked(&mbhc->codec_resource_lock), \
"%s: BCL should have acquired\n", __func__); \
}
/*
* Macros to update and read mbhc register bits. Check for
* "0" before updating or reading the register, because it
* is possible that one codec wants to write to that bit and
* other codec does not.
*/
#define WCD_MBHC_REG_UPDATE_BITS(function, val) \
do { \
if (mbhc->wcd_mbhc_regs[function].reg) { \
snd_soc_component_update_bits(mbhc->component, \
mbhc->wcd_mbhc_regs[function].reg, \
mbhc->wcd_mbhc_regs[function].mask, \
val << (mbhc->wcd_mbhc_regs[function].offset)); \
} \
} while (0)
#define WCD_MBHC_REG_READ(function, val) \
do { \
if (mbhc->wcd_mbhc_regs[function].reg) { \
val = (((snd_soc_component_read(mbhc->component, \
mbhc->wcd_mbhc_regs[function].reg)) & \
(mbhc->wcd_mbhc_regs[function].mask)) >> \
(mbhc->wcd_mbhc_regs[function].offset)); \
} else { \
val = -EINVAL; \
} \
} while (0)
#define WCD_MBHC_CAL_SIZE(buttons, rload) ( \
sizeof(struct wcd_mbhc_general_cfg) + \
sizeof(struct wcd_mbhc_plug_detect_cfg) + \
((sizeof(s16) + sizeof(s16)) * buttons) + \
sizeof(struct wcd_mbhc_plug_type_cfg) + \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
((sizeof(u16) + sizeof(u16)) * rload) \
)
#define WCD_MBHC_CAL_GENERAL_PTR(cali) ( \
(struct wcd_mbhc_general_cfg *) cali)
#define WCD_MBHC_CAL_PLUG_DET_PTR(cali) ( \
(struct wcd_mbhc_plug_detect_cfg *) \
&(WCD_MBHC_CAL_GENERAL_PTR(cali)[1]))
#define WCD_MBHC_CAL_PLUG_TYPE_PTR(cali) ( \
(struct wcd_mbhc_plug_type_cfg *) \
&(WCD_MBHC_CAL_PLUG_DET_PTR(cali)[1]))
#define WCD_MBHC_CAL_BTN_DET_PTR(cali) ( \
(struct wcd_mbhc_btn_detect_cfg *) \
&(WCD_MBHC_CAL_PLUG_TYPE_PTR(cali)[1]))
#define WCD_MBHC_CAL_IMPED_DET_PTR(cali) ( \
(struct wcd_mbhc_imped_detect_cfg *) \
(((void *)&WCD_MBHC_CAL_BTN_DET_PTR(cali)[1]) + \
(WCD_MBHC_CAL_BTN_DET_PTR(cali)->num_btn * \
(sizeof(WCD_MBHC_CAL_BTN_DET_PTR(cali)->_v_btn_low[0]) + \
sizeof(WCD_MBHC_CAL_BTN_DET_PTR(cali)->_v_btn_high[0])))) \
)
#define WCD_MBHC_CAL_MIN_SIZE ( \
sizeof(struct wcd_mbhc_general_cfg) + \
sizeof(struct wcd_mbhc_plug_detect_cfg) + \
sizeof(struct wcd_mbhc_plug_type_cfg) + \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
(sizeof(u16)*2) \
)
#define WCD_MBHC_CAL_BTN_SZ(cfg_ptr) ( \
sizeof(struct wcd_mbhc_btn_detect_cfg) + \
(cfg_ptr->num_btn * (sizeof(cfg_ptr->_v_btn_low[0]) + \
sizeof(cfg_ptr->_v_btn_high[0]))))
#define WCD_MBHC_CAL_IMPED_MIN_SZ ( \
sizeof(struct wcd_mbhc_imped_detect_cfg) + sizeof(u16) * 2)
#define WCD_MBHC_CAL_IMPED_SZ(cfg_ptr) ( \
sizeof(struct wcd_mbhc_imped_detect_cfg) + \
(cfg_ptr->_n_rload * \
(sizeof(cfg_ptr->_rload[0]) + sizeof(cfg_ptr->_alpha[0]))))
#if IS_ENABLED(CONFIG_AUDIO_QGKI)
#define WCD_MBHC_JACK_MASK (SND_JACK_HEADSET | SND_JACK_OC_HPHL | \
SND_JACK_OC_HPHR | SND_JACK_LINEOUT | \
SND_JACK_MECHANICAL | \
SND_JACK_UNSUPPORTED)
#else
#define WCD_MBHC_JACK_MASK (SND_JACK_HEADSET | SND_JACK_LINEOUT | \
SND_JACK_MECHANICAL)
#endif /* CONFIG_AUDIO_QGKI */
#define WCD_MBHC_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
SND_JACK_BTN_2 | SND_JACK_BTN_3 | \
SND_JACK_BTN_4 | SND_JACK_BTN_5)
#define OCP_ATTEMPT 20
#define HS_DETECT_PLUG_TIME_MS (3 * 1000)
#define SPECIAL_HS_DETECT_TIME_MS (2 * 1000)
#define MBHC_BUTTON_PRESS_THRESHOLD_MIN 250
#define GND_MIC_SWAP_THRESHOLD 4
#define GND_MIC_USBC_SWAP_THRESHOLD 2
#define WCD_FAKE_REMOVAL_MIN_PERIOD_MS 100
#define HS_VREF_MIN_VAL 1400
#define FW_READ_ATTEMPTS 15
#define FW_READ_TIMEOUT 4000000
#define FAKE_REM_RETRY_ATTEMPTS 3
#define HPHL_CROSS_CONN_THRESHOLD 100
#define HPHR_CROSS_CONN_THRESHOLD 100
#define WCD_MBHC_BTN_PRESS_COMPL_TIMEOUT_MS 50
#define ANC_DETECT_RETRY_CNT 7
#define WCD_MBHC_SPL_HS_CNT 1
enum wcd_mbhc_detect_logic {
WCD_DETECTION_LEGACY,
WCD_DETECTION_ADC,
};
enum wcd_mbhc_cs_mb_en_flag {
WCD_MBHC_EN_CS = 0,
WCD_MBHC_EN_MB,
WCD_MBHC_EN_PULLUP,
WCD_MBHC_EN_NONE,
};
enum {
WCD_MBHC_ELEC_HS_INS,
WCD_MBHC_ELEC_HS_REM,
};
struct wcd_mbhc;
enum wcd_mbhc_register_function {
WCD_MBHC_L_DET_EN,
WCD_MBHC_GND_DET_EN,
WCD_MBHC_MECH_DETECTION_TYPE,
WCD_MBHC_MIC_CLAMP_CTL,
WCD_MBHC_ELECT_DETECTION_TYPE,
WCD_MBHC_HS_L_DET_PULL_UP_CTRL,
WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL,
WCD_MBHC_HPHL_PLUG_TYPE,
WCD_MBHC_GND_PLUG_TYPE,
WCD_MBHC_SW_HPH_LP_100K_TO_GND,
WCD_MBHC_ELECT_SCHMT_ISRC,
WCD_MBHC_FSM_EN,
WCD_MBHC_INSREM_DBNC,
WCD_MBHC_BTN_DBNC,
WCD_MBHC_HS_VREF,
WCD_MBHC_HS_COMP_RESULT,
WCD_MBHC_IN2P_CLAMP_STATE,
WCD_MBHC_MIC_SCHMT_RESULT,
WCD_MBHC_HPHL_SCHMT_RESULT,
WCD_MBHC_HPHR_SCHMT_RESULT,
WCD_MBHC_OCP_FSM_EN,
WCD_MBHC_BTN_RESULT,
WCD_MBHC_BTN_ISRC_CTL,
WCD_MBHC_ELECT_RESULT,
WCD_MBHC_MICB_CTRL, /* Pull-up and micb control */
WCD_MBHC_HPH_CNP_WG_TIME,
WCD_MBHC_HPHR_PA_EN,
WCD_MBHC_HPHL_PA_EN,
WCD_MBHC_HPH_PA_EN,
WCD_MBHC_SWCH_LEVEL_REMOVE,
WCD_MBHC_PULLDOWN_CTRL,
WCD_MBHC_ANC_DET_EN,
WCD_MBHC_FSM_STATUS,
WCD_MBHC_MUX_CTL,
WCD_MBHC_MOISTURE_STATUS,
WCD_MBHC_HPHR_GND,
WCD_MBHC_HPHL_GND,
WCD_MBHC_HPHL_OCP_DET_EN,
WCD_MBHC_HPHR_OCP_DET_EN,
WCD_MBHC_HPHL_OCP_STATUS,
WCD_MBHC_HPHR_OCP_STATUS,
WCD_MBHC_ADC_EN,
WCD_MBHC_ADC_COMPLETE,
WCD_MBHC_ADC_TIMEOUT,
WCD_MBHC_ADC_RESULT,
WCD_MBHC_MICB2_VOUT,
WCD_MBHC_ADC_MODE,
WCD_MBHC_DETECTION_DONE,
WCD_MBHC_ELECT_ISRC_EN,
WCD_MBHC_REG_FUNC_MAX,
};
enum wcd_mbhc_plug_type {
MBHC_PLUG_TYPE_INVALID = -1,
MBHC_PLUG_TYPE_NONE,
MBHC_PLUG_TYPE_HEADSET,
MBHC_PLUG_TYPE_HEADPHONE,
MBHC_PLUG_TYPE_HIGH_HPH,
MBHC_PLUG_TYPE_GND_MIC_SWAP,
MBHC_PLUG_TYPE_ANC_HEADPHONE,
};
enum pa_dac_ack_flags {
WCD_MBHC_HPHL_PA_OFF_ACK = 0,
WCD_MBHC_HPHR_PA_OFF_ACK,
};
enum anc_ack_flags {
WCD_MBHC_ANC0_OFF_ACK = 0,
WCD_MBHC_ANC1_OFF_ACK,
};
enum wcd_mbhc_btn_det_mem {
WCD_MBHC_BTN_DET_V_BTN_LOW,
WCD_MBHC_BTN_DET_V_BTN_HIGH
};
enum {
MIC_BIAS_1 = 1,
MIC_BIAS_2,
MIC_BIAS_3,
MIC_BIAS_4
};
enum {
MICB_PULLUP_ENABLE,
MICB_PULLUP_DISABLE,
MICB_ENABLE,
MICB_DISABLE,
};
enum {
MBHC_COMMON_MICB_PRECHARGE,
MBHC_COMMON_MICB_SET_VAL,
MBHC_COMMON_MICB_TAIL_CURR,
};
enum wcd_notify_event {
WCD_EVENT_INVALID,
/* events for micbias ON and OFF */
WCD_EVENT_PRE_MICBIAS_2_OFF,
WCD_EVENT_POST_MICBIAS_2_OFF,
WCD_EVENT_PRE_MICBIAS_2_ON,
WCD_EVENT_POST_MICBIAS_2_ON,
WCD_EVENT_PRE_DAPM_MICBIAS_2_OFF,
WCD_EVENT_POST_DAPM_MICBIAS_2_OFF,
WCD_EVENT_PRE_DAPM_MICBIAS_2_ON,
WCD_EVENT_POST_DAPM_MICBIAS_2_ON,
/* events for PA ON and OFF */
WCD_EVENT_PRE_HPHL_PA_ON,
WCD_EVENT_POST_HPHL_PA_OFF,
WCD_EVENT_PRE_HPHR_PA_ON,
WCD_EVENT_POST_HPHR_PA_OFF,
WCD_EVENT_PRE_HPHL_PA_OFF,
WCD_EVENT_PRE_HPHR_PA_OFF,
WCD_EVENT_OCP_OFF,
WCD_EVENT_OCP_ON,
WCD_EVENT_LAST,
};
enum wcd_mbhc_event_state {
WCD_MBHC_EVENT_PA_HPHL,
WCD_MBHC_EVENT_PA_HPHR,
};
struct wcd_mbhc_general_cfg {
u8 t_ldoh;
u8 t_bg_fast_settle;
u8 t_shutdown_plug_rem;
u8 mbhc_nsa;
u8 mbhc_navg;
u8 v_micbias_l;
u8 v_micbias;
u8 mbhc_reserved;
u16 settle_wait;
u16 t_micbias_rampup;
u16 t_micbias_rampdown;
u16 t_supply_bringup;
} __packed;
struct wcd_mbhc_plug_detect_cfg {
u32 mic_current;
u32 hph_current;
u16 t_mic_pid;
u16 t_ins_complete;
u16 t_ins_retry;
u16 v_removal_delta;
u8 micbias_slow_ramp;
u8 reserved0;
u8 reserved1;
u8 reserved2;
} __packed;
struct wcd_mbhc_plug_type_cfg {
u8 av_detect;
u8 mono_detect;
u8 num_ins_tries;
u8 reserved0;
s16 v_no_mic;
s16 v_av_min;
s16 v_av_max;
s16 v_hs_min;
s16 v_hs_max;
u16 reserved1;
} __packed;
struct wcd_mbhc_btn_detect_cfg {
s8 c[8];
u8 nc;
u8 n_meas;
u8 mbhc_nsc;
u8 n_btn_meas;
u8 n_btn_con;
u8 num_btn;
u8 reserved0;
u8 reserved1;
u16 t_poll;
u16 t_bounce_wait;
u16 t_rel_timeout;
s16 v_btn_press_delta_sta;
s16 v_btn_press_delta_cic;
u16 t_btn0_timeout;
s16 _v_btn_low[0]; /* v_btn_low[num_btn] */
s16 _v_btn_high[0]; /* v_btn_high[num_btn] */
u8 _n_ready[2];
u8 _n_cic[2];
u8 _gain[2];
} __packed;
struct wcd_mbhc_imped_detect_cfg {
u8 _hs_imped_detect;
u8 _n_rload;
u8 _hph_keep_on;
u8 _repeat_rload_calc;
u16 _t_dac_ramp_time;
u16 _rhph_high;
u16 _rhph_low;
u16 _rload[0]; /* rload[n_rload] */
u16 _alpha[0]; /* alpha[n_rload] */
u16 _beta[3];
} __packed;
enum wcd_mbhc_hph_type {
WCD_MBHC_HPH_NONE = 0,
WCD_MBHC_HPH_MONO,
WCD_MBHC_HPH_STEREO,
};
/*
* These enum definitions are directly mapped to the register
* definitions
*/
enum mbhc_moisture_vref {
V_OFF,
V_45_MV,
V_100_MV,
V_225_MV,
};
enum mbhc_hs_pullup_iref {
I_DEFAULT = -1,
I_OFF = 0,
I_1P0_UA,
I_2P0_UA,
I_3P0_UA,
};
enum mbhc_hs_pullup_iref_v2 {
HS_PULLUP_I_DEFAULT = -1,
HS_PULLUP_I_3P0_UA = 0,
HS_PULLUP_I_2P25_UA,
HS_PULLUP_I_1P5_UA,
HS_PULLUP_I_0P75_UA,
HS_PULLUP_I_1P125_UA = 0x05,
HS_PULLUP_I_0P375_UA = 0x07,
HS_PULLUP_I_2P0_UA,
HS_PULLUP_I_1P0_UA = 0x0A,
HS_PULLUP_I_0P5_UA,
HS_PULLUP_I_0P25_UA = 0x0F,
HS_PULLUP_I_0P125_UA = 0x17,
HS_PULLUP_I_OFF,
};
enum mbhc_moisture_rref {
R_OFF,
R_24_KOHM,
R_84_KOHM,
R_184_KOHM,
};
struct wcd_mbhc_config {
bool read_fw_bin;
void *calibration;
bool detect_extn_cable;
bool mono_stero_detection;
bool (*swap_gnd_mic)(struct snd_soc_component *component, bool active);
bool hs_ext_micbias;
bool gnd_det_en;
int key_code[WCD_MBHC_KEYCODE_NUM];
uint32_t linein_th;
bool moisture_en;
int mbhc_micbias;
int anc_micbias;
bool enable_anc_mic_detect;
u32 enable_usbc_analog;
bool moisture_duty_cycle_en;
bool usbss_hsj_connect_enable;
};
struct wcd_mbhc_intr {
int mbhc_sw_intr;
int mbhc_btn_press_intr;
int mbhc_btn_release_intr;
int mbhc_hs_ins_intr;
int mbhc_hs_rem_intr;
int hph_left_ocp;
int hph_right_ocp;
};
struct wcd_mbhc_register {
const char *id;
int reg;
u8 mask;
u8 offset;
u8 invert;
};
struct wcd_mbhc_cb {
void (*update_cross_conn_thr)
(struct wcd_mbhc *mbhc);
void (*mbhc_surge_ctl)
(struct wcd_mbhc *mbhc, bool surge_en);
void (*mbhc_comp_autozero_control)
(struct wcd_mbhc *mbhc, bool az_enable);
void (*get_micbias_val)
(struct wcd_mbhc *mbhc, int *mb);
void (*bcs_enable)
(struct wcd_mbhc *mbhc, bool bcs_enable);
int (*enable_mb_source)(struct wcd_mbhc *mbhc, bool turn_on);
void (*trim_btn_reg)(struct snd_soc_component *component);
void (*compute_impedance)(struct wcd_mbhc *mbhc,
uint32_t *zl, uint32_t *zr);
void (*set_micbias_value)(struct snd_soc_component *component);
void (*set_auto_zeroing)(struct snd_soc_component *component,
bool enable);
struct firmware_cal * (*get_hwdep_fw_cal)(struct wcd_mbhc *mbhc,
enum wcd_cal_type);
void (*set_cap_mode)(struct snd_soc_component *component,
bool micbias1, bool micbias2);
int (*register_notifier)(struct wcd_mbhc *mbhc,
struct notifier_block *nblock,
bool enable);
int (*request_irq)(struct snd_soc_component *component,
int irq, irq_handler_t handler,
const char *name, void *data);
void (*irq_control)(struct snd_soc_component *component,
int irq, bool enable);
int (*free_irq)(struct snd_soc_component *component,
int irq, void *data);
void (*clk_setup)(struct snd_soc_component *component, bool enable);
int (*map_btn_code_to_num)(struct snd_soc_component *component);
bool (*lock_sleep)(struct wcd_mbhc *mbhc, bool lock);
bool (*micbias_enable_status)(struct wcd_mbhc *mbhc, int micb_num);
void (*mbhc_bias)(struct snd_soc_component *component, bool enable);
void (*mbhc_common_micb_ctrl)(struct snd_soc_component *component,
int event, bool enable);
void (*micb_internal)(struct snd_soc_component *component,
int micb_num, bool enable);
bool (*hph_pa_on_status)(struct snd_soc_component *component);
void (*set_btn_thr)(struct snd_soc_component *component,
s16 *btn_low, s16 *btn_high,
int num_btn, bool is_micbias);
void (*hph_pull_up_control)(struct snd_soc_component *component,
enum mbhc_hs_pullup_iref);
int (*mbhc_micbias_control)(struct snd_soc_component *component,
int micb_num, int req);
void (*mbhc_micb_ramp_control)(struct snd_soc_component *component,
bool enable);
void (*skip_imped_detect)(struct snd_soc_component *component);
bool (*extn_use_mb)(struct snd_soc_component *component);
int (*mbhc_micb_ctrl_thr_mic)(struct snd_soc_component *component,
int micb_num, bool req_en);
void (*mbhc_gnd_det_ctrl)(struct snd_soc_component *component,
bool enable);
void (*hph_pull_down_ctrl)(struct snd_soc_component *component,
bool enable);
void (*mbhc_moisture_config)(struct wcd_mbhc *mbhc);
bool (*hph_register_recovery)(struct wcd_mbhc *mbhc);
void (*update_anc_state)(struct snd_soc_component *component,
bool enable, int anc_num);
bool (*is_anc_on)(struct wcd_mbhc *mbhc);
void (*hph_pull_up_control_v2)(struct snd_soc_component *component,
int pull_up_cur);
bool (*mbhc_get_moisture_status)(struct wcd_mbhc *mbhc);
void (*mbhc_moisture_polling_ctrl)(struct wcd_mbhc *mbhc, bool enable);
void (*mbhc_moisture_detect_en)(struct wcd_mbhc *mbhc, bool enable);
void (*surge_reset_routine)(struct wcd_mbhc *mbhc);
void (*zdet_leakage_resistance)(struct wcd_mbhc *mbhc, bool enable);
void (*mbhc_button_debounce_set)(struct snd_soc_component *component);
int (*mbhc_force_micbias_disable)(struct snd_soc_component *component,
int micb_num);
};
struct wcd_mbhc_fn {
irqreturn_t (*wcd_mbhc_hs_ins_irq)(int irq, void *data);
irqreturn_t (*wcd_mbhc_hs_rem_irq)(int irq, void *data);
void (*wcd_mbhc_detect_plug_type)(struct wcd_mbhc *mbhc);
bool (*wcd_mbhc_detect_anc_plug_type)(struct wcd_mbhc *mbhc);
void (*wcd_cancel_hs_detect_plug)(struct wcd_mbhc *mbhc,
struct work_struct *work);
};
struct wcd_mbhc {
/* Delayed work to report long button press */
struct delayed_work mbhc_btn_dwork;
int buttons_pressed;
struct wcd_mbhc_config *mbhc_cfg;
const struct wcd_mbhc_cb *mbhc_cb;
u32 hph_status; /* track headhpone status */
u8 hphlocp_cnt; /* headphone left ocp retry */
u8 hphrocp_cnt; /* headphone right ocp retry */
wait_queue_head_t wait_btn_press;
bool is_btn_press;
u8 current_plug;
bool in_swch_irq_handler;
bool hphl_swh; /*track HPHL switch NC / NO */
bool gnd_swh; /*track GND switch NC / NO */
u32 hs_thr;
u32 hph_thr;
u32 micb_mv;
u32 swap_thr;
u32 moist_vref;
u32 moist_iref;
u32 moist_rref;
u32 hphl_cross_conn_thr;
u32 hphr_cross_conn_thr;
u8 micbias1_cap_mode; /* track ext cap setting */
u8 micbias2_cap_mode; /* track ext cap setting */
bool hs_detect_work_stop;
bool micbias_enable;
bool btn_press_intr;
bool is_hs_recording;
bool is_extn_cable;
bool skip_imped_detection;
bool is_btn_already_regd;
bool extn_cable_hph_rem;
struct snd_soc_component *component;
/* Work to perform MBHC Firmware Read */
struct delayed_work mbhc_firmware_dwork;
const struct firmware *mbhc_fw;
struct firmware_cal *mbhc_cal;
/* track PA/DAC state to sync with userspace */
unsigned long hph_pa_dac_state;
unsigned long hph_anc_state;
unsigned long event_state;
unsigned long jiffies_atreport;
/* impedance of hphl and hphr */
uint32_t zl, zr;
bool impedance_detect;
/* Holds type of Headset - Mono/Stereo */
enum wcd_mbhc_hph_type hph_type;
struct snd_soc_jack headset_jack;
struct snd_soc_jack button_jack;
struct mutex codec_resource_lock;
/* Holds codec specific interrupt mapping */
const struct wcd_mbhc_intr *intr_ids;
/* Work to correct accessory type */
struct work_struct correct_plug_swch;
struct notifier_block nblock;
struct wcd_mbhc_register *wcd_mbhc_regs;
struct completion btn_press_compl;
bool deinit_in_progress;
/* Holds mbhc detection method - ADC/Legacy */
unsigned int mbhc_detection_logic;
unsigned long intr_status;
bool is_hph_ocp_pending;
struct wcd_mbhc_fn *mbhc_fn;
bool force_linein;
struct device_node *wcd_usbss_aatc_dev_np;
struct device_node *fsa_aatc_dev_np;
struct device_node *aatc_dev_np;
struct notifier_block aatc_dev_nb;
struct extcon_dev *extdev;
};
void wcd_mbhc_find_plug_and_report(struct wcd_mbhc *mbhc,
enum wcd_mbhc_plug_type plug_type);
void wcd_mbhc_hs_elec_irq(struct wcd_mbhc *mbhc, int irq_type, bool enable);
void wcd_mbhc_elec_hs_report_unplug(struct wcd_mbhc *mbhc);
bool wcd_swch_level_remove(struct wcd_mbhc *mbhc);
void wcd_enable_curr_micbias(const struct wcd_mbhc *mbhc,
const enum wcd_mbhc_cs_mb_en_flag cs_mb_en);
void wcd_mbhc_jack_report(struct wcd_mbhc *mbhc,
struct snd_soc_jack *jack, int status, int mask);
int wcd_cancel_btn_work(struct wcd_mbhc *mbhc);
int wcd_mbhc_get_button_mask(struct wcd_mbhc *mbhc);
void wcd_mbhc_report_plug(struct wcd_mbhc *mbhc, int insertion,
enum snd_jack_types jack_type);
#endif /* __WCD_MBHC_V2_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_COMMON_V2
#define _WCD9XXX_COMMON_V2
#define CLSH_REQ_ENABLE true
#define CLSH_REQ_DISABLE false
#define WCD_CLSH_EVENT_PRE_DAC 0x01
#define WCD_CLSH_EVENT_POST_PA 0x02
#define MAX_VBAT_MONITOR_WRITES 17
/*
* Basic states for Class H state machine.
* represented as a bit mask within a u8 data type
* bit 0: EAR mode
* bit 1: HPH Left mode
* bit 2: HPH Right mode
* bit 3: Lineout mode
*/
#define WCD_CLSH_STATE_IDLE 0x00
#define WCD_CLSH_STATE_EAR (0x01 << 0)
#define WCD_CLSH_STATE_HPHL (0x01 << 1)
#define WCD_CLSH_STATE_HPHR (0x01 << 2)
#define WCD_CLSH_STATE_LO (0x01 << 3)
/*
* Though number of CLSH states are 4, max state shoulbe be 5
* because state array index starts from 1.
*/
#define WCD_CLSH_STATE_MAX 5
#define NUM_CLSH_STATES_V2 (0x01 << WCD_CLSH_STATE_MAX)
/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
#define WCD_CLSH_STATE_HPH_ST (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_HPHR)
#define WCD_CLSH_STATE_HPHL_LO (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPHR_LO (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPH_ST_LO (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_EAR_LO (WCD_CLSH_STATE_EAR | \
WCD_CLSH_STATE_LO)
#define WCD_CLSH_STATE_HPHL_EAR (WCD_CLSH_STATE_HPHL | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPHR_EAR (WCD_CLSH_STATE_HPHR | \
WCD_CLSH_STATE_EAR)
#define WCD_CLSH_STATE_HPH_ST_EAR (WCD_CLSH_STATE_HPH_ST | \
WCD_CLSH_STATE_EAR)
enum {
CLS_H_NORMAL = 0, /* Class-H Default */
CLS_H_HIFI, /* Class-H HiFi */
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB Low HIFI*/
CLS_H_LOHIFI, /* LoHIFI */
CLS_H_ULP, /* Ultra Low power */
CLS_AB_HIFI, /* Class-AB */
CLS_NONE, /* None of the above modes */
};
/* Class H data that the codec driver will maintain */
struct wcd_clsh_cdc_data {
u8 state;
int flyback_users;
int buck_users;
int clsh_users;
int interpolator_modes[WCD_CLSH_STATE_MAX];
};
struct wcd_mad_audio_header {
u32 reserved[3];
u32 num_reg_cfg;
};
struct wcd_mad_microphone_info {
uint8_t input_microphone;
uint8_t cycle_time;
uint8_t settle_time;
uint8_t padding;
} __packed;
struct wcd_mad_micbias_info {
uint8_t micbias;
uint8_t k_factor;
uint8_t external_bypass_capacitor;
uint8_t internal_biasing;
uint8_t cfilter;
uint8_t padding[3];
} __packed;
struct wcd_mad_rms_audio_beacon_info {
uint8_t rms_omit_samples;
uint8_t rms_comp_time;
uint8_t detection_mechanism;
uint8_t rms_diff_threshold;
uint8_t rms_threshold_lsb;
uint8_t rms_threshold_msb;
uint8_t padding[2];
uint8_t iir_coefficients[36];
} __packed;
struct wcd_mad_rms_ultrasound_info {
uint8_t rms_comp_time;
uint8_t detection_mechanism;
uint8_t rms_diff_threshold;
uint8_t rms_threshold_lsb;
uint8_t rms_threshold_msb;
uint8_t padding[3];
uint8_t iir_coefficients[36];
} __packed;
struct wcd_mad_audio_cal {
uint32_t version;
struct wcd_mad_microphone_info microphone_info;
struct wcd_mad_micbias_info micbias_info;
struct wcd_mad_rms_audio_beacon_info audio_info;
struct wcd_mad_rms_audio_beacon_info beacon_info;
struct wcd_mad_rms_ultrasound_info ultrasound_info;
} __packed;
struct wcd9xxx_anc_header {
u32 reserved[3];
u32 num_anc_slots;
};
struct vbat_monitor_reg {
u32 size;
u32 writes[MAX_VBAT_MONITOR_WRITES];
} __packed;
struct wcd_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
extern void wcd_clsh_fsm(struct snd_soc_component *component,
struct wcd_clsh_cdc_data *cdc_clsh_d,
u8 clsh_event, u8 req_state,
int int_mode);
extern void wcd_clsh_init(struct wcd_clsh_cdc_data *clsh);
extern int wcd_clsh_get_clsh_state(struct wcd_clsh_cdc_data *clsh);
extern void wcd_clsh_imped_config(struct snd_soc_component *component,
int imped, bool reset);
enum {
RESERVED = 0,
AANC_LPF_FF_FB = 1,
AANC_LPF_COEFF_MSB,
AANC_LPF_COEFF_LSB,
HW_MAD_AUDIO_ENABLE,
HW_MAD_ULTR_ENABLE,
HW_MAD_BEACON_ENABLE,
HW_MAD_AUDIO_SLEEP_TIME,
HW_MAD_ULTR_SLEEP_TIME,
HW_MAD_BEACON_SLEEP_TIME,
HW_MAD_TX_AUDIO_SWITCH_OFF,
HW_MAD_TX_ULTR_SWITCH_OFF,
HW_MAD_TX_BEACON_SWITCH_OFF,
MAD_AUDIO_INT_DEST_SELECT_REG,
MAD_ULT_INT_DEST_SELECT_REG,
MAD_BEACON_INT_DEST_SELECT_REG,
MAD_CLIP_INT_DEST_SELECT_REG,
VBAT_INT_DEST_SELECT_REG,
MAD_AUDIO_INT_MASK_REG,
MAD_ULT_INT_MASK_REG,
MAD_BEACON_INT_MASK_REG,
MAD_CLIP_INT_MASK_REG,
VBAT_INT_MASK_REG,
MAD_AUDIO_INT_STATUS_REG,
MAD_ULT_INT_STATUS_REG,
MAD_BEACON_INT_STATUS_REG,
MAD_CLIP_INT_STATUS_REG,
VBAT_INT_STATUS_REG,
MAD_AUDIO_INT_CLEAR_REG,
MAD_ULT_INT_CLEAR_REG,
MAD_BEACON_INT_CLEAR_REG,
MAD_CLIP_INT_CLEAR_REG,
VBAT_INT_CLEAR_REG,
SB_PGD_PORT_TX_WATERMARK_N,
SB_PGD_PORT_TX_ENABLE_N,
SB_PGD_PORT_RX_WATERMARK_N,
SB_PGD_PORT_RX_ENABLE_N,
SB_PGD_TX_PORTn_MULTI_CHNL_0,
SB_PGD_TX_PORTn_MULTI_CHNL_1,
SB_PGD_RX_PORTn_MULTI_CHNL_0,
SB_PGD_RX_PORTn_MULTI_CHNL_1,
AANC_FF_GAIN_ADAPTIVE,
AANC_FFGAIN_ADAPTIVE_EN,
AANC_GAIN_CONTROL,
SPKR_CLIP_PIPE_BANK_SEL,
SPKR_CLIPDET_VAL0,
SPKR_CLIPDET_VAL1,
SPKR_CLIPDET_VAL2,
SPKR_CLIPDET_VAL3,
SPKR_CLIPDET_VAL4,
SPKR_CLIPDET_VAL5,
SPKR_CLIPDET_VAL6,
SPKR_CLIPDET_VAL7,
VBAT_RELEASE_INT_DEST_SELECT_REG,
VBAT_RELEASE_INT_MASK_REG,
VBAT_RELEASE_INT_STATUS_REG,
VBAT_RELEASE_INT_CLEAR_REG,
MAD2_CLIP_INT_DEST_SELECT_REG,
MAD2_CLIP_INT_MASK_REG,
MAD2_CLIP_INT_STATUS_REG,
MAD2_CLIP_INT_CLEAR_REG,
SPKR2_CLIP_PIPE_BANK_SEL,
SPKR2_CLIPDET_VAL0,
SPKR2_CLIPDET_VAL1,
SPKR2_CLIPDET_VAL2,
SPKR2_CLIPDET_VAL3,
SPKR2_CLIPDET_VAL4,
SPKR2_CLIPDET_VAL5,
SPKR2_CLIPDET_VAL6,
SPKR2_CLIPDET_VAL7,
MAX_CFG_REGISTERS,
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
*/
#include <linux/types.h>
#include "core.h"
#ifndef __MFD_WCD9XXX_IRQ_H
#define __MFD_WCD9XXX_IRQ_H
#ifdef CONFIG_WCD9XXX_CODEC_CORE
bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *wcd9xxx_res);
int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq,
irq_handler_t handler, const char *name, void *data);
void wcd9xxx_free_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq, void *data);
void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq);
void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq);
void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq);
int wcd9xxx_irq_init(struct wcd9xxx_core_resource *wcd9xxx_res);
void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *wcd9xxx_res);
int wcd9xxx_irq_drv_init(void);
void wcd9xxx_irq_drv_exit(void);
#else
bool wcd9xxx_lock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res)
{
return false;
}
void wcd9xxx_unlock_sleep(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq,
irq_handler_t handler, const char *name, void *data)
{
return 0;
}
void wcd9xxx_free_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq, void *data)
{
}
void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
{
}
void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq)
{
}
void wcd9xxx_disable_irq_sync(struct wcd9xxx_core_resource *wcd9xxx_res,
int irq)
{
}
int wcd9xxx_irq_init(struct wcd9xxx_core_resource *wcd9xxx_res)
{
return 0;
}
void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *wcd9xxx_res)
{
}
int wcd9xxx_irq_drv_init(void)
{
return 0;
}
void wcd9xxx_irq_drv_exit(void)
{
}
#endif
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_REGMAP_
#define _WCD9XXX_REGMAP_
#include <linux/regmap.h>
#include "core.h"
typedef int (*regmap_patch_fptr)(struct regmap *regmap, int version);
extern struct regmap_config wcd934x_regmap_config;
extern int wcd934x_regmap_register_patch(struct regmap *regmap,
int version);
extern struct regmap_config wcd9335_regmap_config;
extern int wcd9335_regmap_register_patch(struct regmap *regmap,
int version);
static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
{
struct regmap_config *regmap_config;
switch (type) {
case WCD934X:
regmap_config = &wcd934x_regmap_config;
break;
case WCD9335:
regmap_config = &wcd9335_regmap_config;
break;
default:
regmap_config = NULL;
break;
};
return regmap_config;
}
static inline regmap_patch_fptr wcd9xxx_get_regmap_reg_patch(int type)
{
regmap_patch_fptr apply_patch;
switch (type) {
case WCD9335:
apply_patch = wcd9335_regmap_register_patch;
break;
case WCD934X:
apply_patch = wcd934x_regmap_register_patch;
break;
default:
apply_patch = NULL;
break;
}
return apply_patch;
}
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_COMMON_V2_H__
#define __WCD9XXX_COMMON_V2_H__
#include "wcd9xxx_registers.h"
#include "core.h"
enum wcd_clock_type {
WCD_CLK_OFF,
WCD_CLK_RCO,
WCD_CLK_MCLK,
};
enum {
SIDO_SOURCE_INTERNAL,
SIDO_SOURCE_RCO_BG,
};
struct wcd_resmgr_cb {
int (*cdc_rco_ctrl)(struct snd_soc_component *component, bool enable);
};
struct wcd9xxx_resmgr_v2 {
struct snd_soc_component *component;
struct wcd9xxx_core_resource *core_res;
int master_bias_users;
int clk_mclk_users;
int clk_rco_users;
struct mutex codec_bg_clk_lock;
struct mutex master_bias_lock;
enum codec_variant codec_type;
enum wcd_clock_type clk_type;
const struct wcd_resmgr_cb *resmgr_cb;
int sido_input_src;
};
#define WCD9XXX_V2_BG_CLK_LOCK(resmgr) \
{ \
struct wcd9xxx_resmgr_v2 *__resmgr = resmgr; \
pr_debug("%s: Acquiring BG_CLK\n", __func__); \
mutex_lock(&__resmgr->codec_bg_clk_lock); \
pr_debug("%s: Acquiring BG_CLK done\n", __func__); \
}
#define WCD9XXX_V2_BG_CLK_UNLOCK(resmgr) \
{ \
struct wcd9xxx_resmgr_v2 *__resmgr = resmgr; \
pr_debug("%s: Releasing BG_CLK\n", __func__); \
mutex_unlock(&__resmgr->codec_bg_clk_lock); \
}
#define WCD9XXX_V2_BG_CLK_ASSERT_LOCKED(resmgr) \
{ \
WARN_ONCE(!mutex_is_locked(&resmgr->codec_bg_clk_lock), \
"%s: BG_CLK lock should have acquired\n", __func__); \
}
int wcd_resmgr_enable_master_bias(struct wcd9xxx_resmgr_v2 *resmgr);
int wcd_resmgr_disable_master_bias(struct wcd9xxx_resmgr_v2 *resmgr);
struct wcd9xxx_resmgr_v2 *wcd_resmgr_init(
struct wcd9xxx_core_resource *core_res,
struct snd_soc_component *component);
void wcd_resmgr_remove(struct wcd9xxx_resmgr_v2 *resmgr);
int wcd_resmgr_post_init(struct wcd9xxx_resmgr_v2 *resmgr,
const struct wcd_resmgr_cb *resmgr_cb,
struct snd_soc_component *component);
int wcd_resmgr_enable_clk_block(struct wcd9xxx_resmgr_v2 *resmgr,
enum wcd_clock_type type);
int wcd_resmgr_disable_clk_block(struct wcd9xxx_resmgr_v2 *resmgr,
enum wcd_clock_type type);
int wcd_resmgr_get_clk_type(struct wcd9xxx_resmgr_v2 *resmgr);
void wcd_resmgr_post_ssr_v2(struct wcd9xxx_resmgr_v2 *resmgr);
void wcd_resmgr_set_sido_input_src_locked(struct wcd9xxx_resmgr_v2 *resmgr,
int sido_src);
void wcd_resmgr_set_sido_input_src(struct wcd9xxx_resmgr_v2 *resmgr,
int sido_src);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_SLIMSLAVE_H_
#define __WCD9XXX_SLIMSLAVE_H_
#include <linux/slimbus/slimbus.h>
#include "core.h"
/*
* client is expected to give port ids in the range of
* 1-10 for pre Taiko Tx ports and 1-16 for Taiko
* 1-7 for pre Taiko Rx ports and 1-16 for Tako,
* we need to add offset for getting the absolute slave
* port id before configuring the HW
*/
#define TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 10
#define TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS 16
#define SLIM_MAX_TX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \
TABLA_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS \
TAIKO_SB_PGD_MAX_NUMBER_OF_TX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 7
#define TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS 13
#define SLIM_MAX_RX_PORTS TAIKO_SB_PGD_MAX_NUMBER_OF_RX_SLAVE_DEV_PORTS
#define SLIM_MAX_REG_ADDR (0x180 + 4 * (SLIM_MAX_RX_PORTS))
#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \
TABLA_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS
#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_START_PORT_ID \
TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS
#define TABLA_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 16
#define TAIKO_SB_PGD_RX_PORT_MULTI_CHANNEL_0_END_PORT_ID 31
#define TABLA_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 9
#define TAIKO_SB_PGD_TX_PORT_MULTI_CHANNEL_1_END_PORT_ID 15
/* below details are taken from SLIMBUS slave SWI */
#define SB_PGD_PORT_BASE 0x000
#define SB_PGD_PORT_CFG_BYTE_ADDR(offset, port_num) \
(SB_PGD_PORT_BASE + offset + (1 * port_num))
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0(port_num) \
(SB_PGD_PORT_BASE + 0x100 + 4*port_num)
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_START_PORT_ID 0
#define SB_PGD_TX_PORT_MULTI_CHANNEL_0_END_PORT_ID 7
#define SB_PGD_TX_PORT_MULTI_CHANNEL_1(port_num) \
(SB_PGD_PORT_BASE + 0x101 + 4*port_num)
#define SB_PGD_TX_PORT_MULTI_CHANNEL_1_START_PORT_ID 8
#define SB_PGD_RX_PORT_MULTI_CHANNEL_0(offset, port_num) \
(SB_PGD_PORT_BASE + offset + (4 * port_num))
/* slave port water mark level
* (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
*/
#define SLAVE_PORT_WATER_MARK_6BYTES 0
#define SLAVE_PORT_WATER_MARK_9BYTES 1
#define SLAVE_PORT_WATER_MARK_12BYTES 2
#define SLAVE_PORT_WATER_MARK_15BYTES 3
#define SLAVE_PORT_WATER_MARK_SHIFT 1
#define SLAVE_PORT_ENABLE 1
#define SLAVE_PORT_DISABLE 0
#define WATER_MARK_VAL \
((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
(SLAVE_PORT_ENABLE))
#define BASE_CH_NUM 128
int wcd9xxx_init_slimslave(struct wcd9xxx *wcd9xxx,
u8 wcd9xxx_pgd_la,
unsigned int tx_num, unsigned int *tx_slot,
unsigned int rx_num, unsigned int *rx_slot);
int wcd9xxx_deinit_slimslave(struct wcd9xxx *wcd9xxx);
int wcd9xxx_cfg_slim_sch_rx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list,
unsigned int rate, unsigned int bit_width,
u16 *grph);
int wcd9xxx_cfg_slim_sch_tx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list,
unsigned int rate, unsigned int bit_width,
u16 *grph);
int wcd9xxx_close_slim_sch_rx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_close_slim_sch_tx(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_get_channel(struct wcd9xxx *wcd9xxx,
unsigned int *rx_ch,
unsigned int *tx_ch);
int wcd9xxx_get_slave_port(unsigned int ch_num);
int wcd9xxx_disconnect_port(struct wcd9xxx *wcd9xxx,
struct list_head *wcd9xxx_ch_list, u16 grph);
int wcd9xxx_rx_vport_validation(u32 port_id,
struct list_head *codec_dai_list);
int wcd9xxx_tx_vport_validation(u32 vtable, u32 port_id,
struct wcd9xxx_codec_dai_data *codec_dai,
u32 num_codec_dais);
#endif /* __WCD9XXX_SLIMSLAVE_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD9XXX_REGISTERS_H
#define _WCD9XXX_REGISTERS_H
#define WCD9XXX_A_CHIP_CTL (0x00)
#define WCD9XXX_A_CHIP_CTL__POR (0x00000000)
#define WCD9XXX_A_CHIP_STATUS (0x01)
#define WCD9XXX_A_CHIP_STATUS__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_0 (0x04)
#define WCD9XXX_A_CHIP_ID_BYTE_0__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_1 (0x05)
#define WCD9XXX_A_CHIP_ID_BYTE_1__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_2 (0x06)
#define WCD9XXX_A_CHIP_ID_BYTE_2__POR (0x00000000)
#define WCD9XXX_A_CHIP_ID_BYTE_3 (0x07)
#define WCD9XXX_A_CHIP_ID_BYTE_3__POR (0x00000001)
#define WCD9XXX_A_CHIP_VERSION (0x08)
#define WCD9XXX_A_CHIP_VERSION__POR (0x00000020)
#define WCD9XXX_A_SB_VERSION (0x09)
#define WCD9XXX_A_SB_VERSION__POR (0x00000010)
#define WCD9XXX_A_SLAVE_ID_1 (0x0C)
#define WCD9XXX_A_SLAVE_ID_1__POR (0x00000077)
#define WCD9XXX_A_SLAVE_ID_2 (0x0D)
#define WCD9XXX_A_SLAVE_ID_2__POR (0x00000066)
#define WCD9XXX_A_SLAVE_ID_3 (0x0E)
#define WCD9XXX_A_SLAVE_ID_3__POR (0x00000055)
#define WCD9XXX_A_CDC_CTL (0x80)
#define WCD9XXX_A_CDC_CTL__POR (0x00000000)
#define WCD9XXX_A_LEAKAGE_CTL (0x88)
#define WCD9XXX_A_LEAKAGE_CTL__POR (0x00000004)
#define WCD9XXX_A_INTR_MODE (0x90)
#define WCD9XXX_A_INTR_MASK0 (0x94)
#define WCD9XXX_A_INTR_STATUS0 (0x98)
#define WCD9XXX_A_INTR_CLEAR0 (0x9C)
#define WCD9XXX_A_INTR_LEVEL0 (0xA0)
#define WCD9XXX_A_INTR_LEVEL1 (0xA1)
#define WCD9XXX_A_INTR_LEVEL2 (0xA2)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_RX_HPH_CNP_EN (0x1AB)
#define WCD9XXX_A_RX_HPH_CNP_EN__POR (0x80)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL (0x101)
#define WCD9XXX_A_BIAS_CENTRAL_BG_CTL__POR (0x50)
#define WCD9XXX_A_CLK_BUFF_EN1 (0x108)
#define WCD9XXX_A_CLK_BUFF_EN1__POR (0x04)
#define WCD9XXX_A_CLK_BUFF_EN2 (0x109)
#define WCD9XXX_A_CLK_BUFF_EN2__POR (0x02)
#define WCD9XXX_A_RX_COM_BIAS (0x1A2)
#define WCD9XXX_A_RX_COM_BIAS__POR (0x00)
#define WCD9XXX_A_RC_OSC_FREQ (0x1FA)
#define WCD9XXX_A_RC_OSC_FREQ__POR (0x46)
#define WCD9XXX_A_BIAS_OSC_BG_CTL (0x105)
#define WCD9XXX_A_BIAS_OSC_BG_CTL__POR (0x16)
#define WCD9XXX_A_RC_OSC_TEST (0x1FB)
#define WCD9XXX_A_RC_OSC_TEST__POR (0x0A)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL (0x311)
#define WCD9XXX_A_CDC_CLK_MCLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_EN_CTL (0x3C0)
#define WCD9XXX_A_CDC_MBHC_EN_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
#define WCD9XXX_A_CDC_MBHC_FIR_B1_CFG__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
#define WCD9XXX_A_CDC_MBHC_FIR_B2_CFG__POR (0x06)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
#define WCD9XXX_A_CDC_MBHC_TIMER_B1_CTL__POR (0x03)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
#define WCD9XXX_A_CDC_MBHC_TIMER_B2_CTL__POR (0x09)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
#define WCD9XXX_A_CDC_MBHC_TIMER_B3_CTL__POR (0x1E)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
#define WCD9XXX_A_CDC_MBHC_TIMER_B4_CTL__POR (0x45)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
#define WCD9XXX_A_CDC_MBHC_TIMER_B5_CTL__POR (0x04)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
#define WCD9XXX_A_CDC_MBHC_TIMER_B6_CTL__POR (0x78)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS (0x3C9)
#define WCD9XXX_A_CDC_MBHC_B1_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS (0x3CA)
#define WCD9XXX_A_CDC_MBHC_B2_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS (0x3CB)
#define WCD9XXX_A_CDC_MBHC_B3_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS (0x3CC)
#define WCD9XXX_A_CDC_MBHC_B4_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS (0x3CD)
#define WCD9XXX_A_CDC_MBHC_B5_STATUS__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_B1_CTL (0x3CE)
#define WCD9XXX_A_CDC_MBHC_B1_CTL__POR (0xC0)
#define WCD9XXX_A_CDC_MBHC_B2_CTL (0x3CF)
#define WCD9XXX_A_CDC_MBHC_B2_CTL__POR (0x5D)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
#define WCD9XXX_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
#define WCD9XXX_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
#define WCD9XXX_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
#define WCD9XXX_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
#define WCD9XXX_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
#define WCD9XXX_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
#define WCD9XXX_A_CDC_MBHC_VOLT_B7_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
#define WCD9XXX_A_CDC_MBHC_VOLT_B8_CTL__POR (0x07)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
#define WCD9XXX_A_CDC_MBHC_VOLT_B9_CTL__POR (0xFF)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
#define WCD9XXX_A_CDC_MBHC_VOLT_B10_CTL__POR (0x7F)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
#define WCD9XXX_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
#define WCD9XXX_A_CDC_MBHC_VOLT_B12_CTL__POR (0x80)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL (0x3DC)
#define WCD9XXX_A_CDC_MBHC_CLK_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_INT_CTL (0x3DD)
#define WCD9XXX_A_CDC_MBHC_INT_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL (0x3DE)
#define WCD9XXX_A_CDC_MBHC_DEBUG_CTL__POR (0x00)
#define WCD9XXX_A_CDC_MBHC_SPARE (0x3DF)
#define WCD9XXX_A_CDC_MBHC_SPARE__POR (0x00)
#define WCD9XXX_A_MBHC_SCALING_MUX_1 (0x14E)
#define WCD9XXX_A_MBHC_SCALING_MUX_1__POR (0x00)
#define WCD9XXX_A_RX_HPH_OCP_CTL (0x1AA)
#define WCD9XXX_A_RX_HPH_OCP_CTL__POR (0x68)
#define WCD9XXX_A_MICB_1_CTL (0x12B)
#define WCD9XXX_A_MICB_1_CTL__POR (0x16)
#define WCD9XXX_A_MICB_1_INT_RBIAS (0x12C)
#define WCD9XXX_A_MICB_1_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_1_MBHC (0x12D)
#define WCD9XXX_A_MICB_1_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_2_CTL (0x12E)
#define WCD9XXX_A_MICB_CFILT_2_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_2_VAL (0x12F)
#define WCD9XXX_A_MICB_CFILT_2_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG (0x130)
#define WCD9XXX_A_MICB_CFILT_2_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_2_CTL (0x131)
#define WCD9XXX_A_MICB_2_CTL__POR (0x16)
#define WCD9XXX_A_MICB_2_INT_RBIAS (0x132)
#define WCD9XXX_A_MICB_2_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_2_MBHC (0x133)
#define WCD9XXX_A_MICB_2_MBHC__POR (0x02)
#define WCD9XXX_A_MICB_CFILT_3_CTL (0x134)
#define WCD9XXX_A_MICB_CFILT_3_CTL__POR (0x40)
#define WCD9XXX_A_MICB_CFILT_3_VAL (0x135)
#define WCD9XXX_A_MICB_CFILT_3_VAL__POR (0x80)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG (0x136)
#define WCD9XXX_A_MICB_CFILT_3_PRECHRG__POR (0x38)
#define WCD9XXX_A_MICB_3_CTL (0x137)
#define WCD9XXX_A_MICB_3_CTL__POR (0x16)
#define WCD9XXX_A_MICB_3_INT_RBIAS (0x138)
#define WCD9XXX_A_MICB_3_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_3_MBHC (0x139)
#define WCD9XXX_A_MICB_3_MBHC__POR (0x00)
#define WCD9XXX_A_MICB_4_CTL (0x13D)
#define WCD9XXX_A_MICB_4_CTL__POR (0x16)
#define WCD9XXX_A_MICB_4_INT_RBIAS (0x13E)
#define WCD9XXX_A_MICB_4_INT_RBIAS__POR (0x24)
#define WCD9XXX_A_MICB_4_MBHC (0x13F)
#define WCD9XXX_A_MICB_4_MBHC__POR (0x01)
#define WCD9XXX_A_MICB_CFILT_1_VAL (0x129)
#define WCD9XXX_A_MICB_CFILT_1_VAL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_STATUS (0x1B3)
#define WCD9XXX_A_RX_HPH_L_STATUS__POR (0x00)
#define WCD9XXX_A_MBHC_HPH (0x1FE)
#define WCD9XXX_A_MBHC_HPH__POR (0x44)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME (0x1AD)
#define WCD9XXX_A_RX_HPH_CNP_WG_TIME__POR (0x2A)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL (0x1B7)
#define WCD9XXX_A_RX_HPH_R_DAC_CTL__POR (0x00)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL (0x1B1)
#define WCD9XXX_A_RX_HPH_L_DAC_CTL__POR (0x00)
#define WCD9XXX_A_TX_7_MBHC_EN (0x171)
#define WCD9XXX_A_TX_7_MBHC_EN__POR (0x0C)
#define WCD9XXX_A_PIN_CTL_OE0 (0x010)
#define WCD9XXX_A_PIN_CTL_OE0__POR (0x00)
#define WCD9XXX_A_PIN_CTL_OE1 (0x011)
#define WCD9XXX_A_PIN_CTL_OE1__POR (0x00)
#define WCD9XXX_A_MICB_CFILT_1_CTL (0x128)
#define WCD9XXX_A_LDO_H_MODE_1 (0x110)
#define WCD9XXX_A_LDO_H_MODE_1__POR (0x65)
#define WCD9XXX_A_MICB_CFILT_1_CTL__POR (0x40)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL (0x174)
#define WCD9XXX_A_TX_7_MBHC_TEST_CTL__POR (0x38)
#define WCD9XXX_A_MBHC_SCALING_MUX_2 (0x14F)
#define WCD9XXX_A_MBHC_SCALING_MUX_2__POR (0x80)
#define WCD9XXX_A_TX_COM_BIAS (0x14C)
#define WCD9XXX_A_TX_COM_BIAS__POR (0xF0)
#define WCD9XXX_A_MBHC_INSERT_DETECT (0x14A) /* TAIKO and later */
#define WCD9XXX_A_MBHC_INSERT_DETECT__POR (0x00)
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS (0x14B) /* TAIKO and later */
#define WCD9XXX_A_MBHC_INSERT_DET_STATUS__POR (0x00)
#define WCD9XXX_A_MAD_ANA_CTRL (0x150)
#define WCD9XXX_A_MAD_ANA_CTRL__POR (0xF1)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL (0x30C)
#define WCD9XXX_A_CDC_CLK_OTHR_CTL__POR (0x00)
/* Class H related common registers */
#define WCD9XXX_A_BUCK_MODE_1 (0x181)
#define WCD9XXX_A_BUCK_MODE_1__POR (0x21)
#define WCD9XXX_A_BUCK_MODE_2 (0x182)
#define WCD9XXX_A_BUCK_MODE_2__POR (0xFF)
#define WCD9XXX_A_BUCK_MODE_3 (0x183)
#define WCD9XXX_A_BUCK_MODE_3__POR (0xCC)
#define WCD9XXX_A_BUCK_MODE_4 (0x184)
#define WCD9XXX_A_BUCK_MODE_4__POR (0x3A)
#define WCD9XXX_A_BUCK_MODE_5 (0x185)
#define WCD9XXX_A_BUCK_MODE_5__POR (0x00)
#define WCD9XXX_A_BUCK_CTRL_VCL_1 (0x186)
#define WCD9XXX_A_BUCK_CTRL_VCL_1__POR (0x48)
#define WCD9XXX_A_BUCK_CTRL_VCL_2 (0x187)
#define WCD9XXX_A_BUCK_CTRL_VCL_2__POR (0xA3)
#define WCD9XXX_A_BUCK_CTRL_VCL_3 (0x188)
#define WCD9XXX_A_BUCK_CTRL_VCL_3__POR (0x82)
#define WCD9XXX_A_BUCK_CTRL_CCL_1 (0x189)
#define WCD9XXX_A_BUCK_CTRL_CCL_1__POR (0xAB)
#define WCD9XXX_A_BUCK_CTRL_CCL_2 (0x18A)
#define WCD9XXX_A_BUCK_CTRL_CCL_2__POR (0xDC)
#define WCD9XXX_A_BUCK_CTRL_CCL_3 (0x18B)
#define WCD9XXX_A_BUCK_CTRL_CCL_3__POR (0x6A)
#define WCD9XXX_A_BUCK_CTRL_CCL_4 (0x18C)
#define WCD9XXX_A_BUCK_CTRL_CCL_4__POR (0x58)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1 (0x18D)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_1__POR (0x50)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2 (0x18E)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_2__POR (0x64)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3 (0x18F)
#define WCD9XXX_A_BUCK_CTRL_PWM_DRVR_3__POR (0x77)
#define WCD9XXX_A_BUCK_TMUX_A_D (0x190)
#define WCD9XXX_A_BUCK_TMUX_A_D__POR (0x00)
#define WCD9XXX_A_NCP_EN (0x192)
#define WCD9XXX_A_NCP_EN__POR (0xFE)
#define WCD9XXX_A_NCP_STATIC (0x194)
#define WCD9XXX_A_NCP_STATIC__POR (0x28)
#define WCD9XXX_A_NCP_BUCKREF (0x191)
#define WCD9XXX_A_NCP_BUCKREF__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B1_CTL (0x320)
#define WCD9XXX_A_CDC_CLSH_B1_CTL__POR (0xE4)
#define WCD9XXX_A_CDC_CLSH_B2_CTL (0x321)
#define WCD9XXX_A_CDC_CLSH_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_B3_CTL (0x322)
#define WCD9XXX_A_CDC_CLSH_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS (0x323)
#define WCD9XXX_A_CDC_CLSH_BUCK_NCP_VARS__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD (0x324)
#define WCD9XXX_A_CDC_CLSH_IDLE_HPH_THSD__POR (0x12)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD (0x325)
#define WCD9XXX_A_CDC_CLSH_IDLE_EAR_THSD__POR (0x0C)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD (0x326)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR (0x18)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD (0x327)
#define WCD9XXX_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR (0x23)
#define WCD9XXX_A_CDC_CLSH_K_ADDR (0x328)
#define WCD9XXX_A_CDC_CLSH_K_ADDR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_K_DATA (0x329)
#define WCD9XXX_A_CDC_CLSH_K_DATA__POR (0xA4)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L (0x32A)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_L__POR (0xD7)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U (0x32B)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_HPH_U__POR (0x05)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L (0x32C)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_L__POR (0x60)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U (0x32D)
#define WCD9XXX_A_CDC_CLSH_I_PA_FACT_EAR_U__POR (0x09)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR (0x32E)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH (0x32F)
#define WCD9XXX_A_CDC_CLSH_V_PA_HD_HPH__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR (0x330)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_EAR__POR (0x00)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH (0x331)
#define WCD9XXX_A_CDC_CLSH_V_PA_MIN_HPH__POR (0x00)
#define WCD9XXX_A_CDC_RX1_B6_CTL (0x2B5)
#define WCD9XXX_A_CDC_RX1_B6_CTL__POR (0x80)
#define WCD9XXX_A_CDC_RX2_B6_CTL (0x2BD)
#define WCD9XXX_A_CDC_RX2_B6_CTL__POR (0x80)
#define WCD9XXX_A_RX_HPH_L_GAIN (0x1AE)
#define WCD9XXX_A_RX_HPH_L_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_GAIN (0x1B4)
#define WCD9XXX_A_RX_HPH_R_GAIN__POR (0x00)
#define WCD9XXX_A_RX_HPH_CHOP_CTL (0x1A5)
#define WCD9XXX_A_RX_HPH_CHOP_CTL__POR (0xB4)
#define WCD9XXX_A_RX_HPH_BIAS_PA (0x1A6)
#define WCD9XXX_A_RX_HPH_BIAS_PA__POR (0x7A)
#define WCD9XXX_A_RX_HPH_L_TEST (0x1AF)
#define WCD9XXX_A_RX_HPH_L_TEST__POR (0x00)
#define WCD9XXX_A_RX_HPH_R_TEST (0x1B5)
#define WCD9XXX_A_RX_HPH_R_TEST__POR (0x00)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL (0x30F)
#define WCD9XXX_A_CDC_CLK_RX_B1_CTL__POR (0x00)
#define WCD9XXX_A_NCP_CLK (0x193)
#define WCD9XXX_A_NCP_CLK__POR (0x94)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP (0x1A9)
#define WCD9XXX_A_RX_HPH_BIAS_WG_OCP__POR (0x2A)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL (0x1AC)
#define WCD9XXX_A_RX_HPH_CNP_WG_CTL__POR (0xDE)
#define WCD9XXX_A_RX_HPH_L_PA_CTL (0x1B0)
#define WCD9XXX_A_RX_HPH_L_PA_CTL__POR (0x42)
#define WCD9XXX_A_RX_HPH_R_PA_CTL (0x1B6)
#define WCD9XXX_A_RX_HPH_R_PA_CTL__POR (0x42)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL (0x383)
#define WCD9XXX_A_CDC_CONN_RX2_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL (0x361)
#define WCD9XXX_A_CDC_PA_RAMP_B1_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL (0x362)
#define WCD9XXX_A_CDC_PA_RAMP_B2_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL (0x363)
#define WCD9XXX_A_CDC_PA_RAMP_B3_CTL__POR (0x00)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL (0x364)
#define WCD9XXX_A_CDC_PA_RAMP_B4_CTL__POR (0x00)
#define WCD9330_A_LEAKAGE_CTL (0x03C)
#define WCD9330_A_LEAKAGE_CTL__POR (0x04)
#define WCD9330_A_CDC_CTL (0x034)
#define WCD9330_A_CDC_CTL__POR (0x00)
/* Class-H registers for codecs from and above WCD9335 */
#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 (0xB42)
#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 (0xB56)
#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 (0xB6A)
#define WCD9XXX_A_CDC_CLSH_K1_MSB (0xC08)
#define WCD9XXX_A_CDC_CLSH_K1_LSB (0xC09)
#define WCD9XXX_A_ANA_RX_SUPPLIES (0x608)
#define WCD9XXX_A_ANA_HPH (0x609)
#define WCD9XXX_A_CDC_CLSH_CRC (0xC01)
#define WCD9XXX_FLYBACK_EN (0x6A4)
#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (0x6A5)
#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (0x6AF)
#define WCD9XXX_RX_BIAS_FLYB_BUFF (0x6C7)
#define WCD9XXX_HPH_L_EN (0x6D3)
#define WCD9XXX_HPH_R_EN (0x6D6)
#define WCD9XXX_HPH_REFBUFF_UHQA_CTL (0x6DD)
#define WCD9XXX_CLASSH_CTRL_VCL_2 (0x69B)
#define WCD9XXX_CDC_CLSH_HPH_V_PA (0xC04)
#define WCD9XXX_CDC_RX0_RX_PATH_SEC0 (0xB49)
#define WCD9XXX_CDC_RX1_RX_PATH_CTL (0xB55)
#define WCD9XXX_CDC_RX2_RX_PATH_CTL (0xB69)
#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL (0xD41)
#define WCD9XXX_CLASSH_CTRL_CCL_1 (0x69C)
/* RX Gain control registers of codecs from and above WCD9335 */
#define WCD9XXX_CDC_RX1_RX_VOL_CTL (0xB59)
#define WCD9XXX_CDC_RX1_RX_VOL_MIX_CTL (0xB5C)
#define WCD9XXX_CDC_RX1_RX_PATH_SEC1 (0xB5E)
#define WCD9XXX_CDC_RX2_RX_VOL_CTL (0xB6D)
#define WCD9XXX_CDC_RX2_RX_VOL_MIX_CTL (0xB70)
#define WCD9XXX_CDC_RX2_RX_PATH_SEC1 (0xB72)
/* Class-H registers for codecs from and above WCD934X */
#define WCD9XXX_HPH_CNP_WG_CTL (0x06cc)
#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (0x06a8)
#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (0x0738)
#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (0x06bf)
#define WCD9XXX_HPH_PA_CTL1 (0x06d1)
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014, 2018, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef __WCD9XXX_HWDEP_H__
#define __WCD9XXX_HWDEP_H__
#include <sound/msmcal-hwdep.h>
enum wcd_cal_states {
WCDCAL_UNINITIALISED,
WCDCAL_INITIALISED,
WCDCAL_RECIEVED
};
struct fw_info {
struct firmware_cal *fw[WCD9XXX_MAX_CAL];
DECLARE_BITMAP(cal_bit, WCD9XXX_MAX_CAL);
/* for calibration tracking */
unsigned long wcdcal_state[WCD9XXX_MAX_CAL];
struct mutex lock;
};
struct firmware_cal {
u8 *data;
size_t size;
};
struct snd_soc_codec;
int wcd_cal_create_hwdep(void *fw, int node,
struct snd_soc_component *component);
struct firmware_cal *wcdcal_get_fw_cal(struct fw_info *fw_data,
enum wcd_cal_type type);
#endif /* __WCD9XXX_HWDEP_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.*/
#ifndef __AUDIO_CODEC_PORT_TYPES_H
#define __AUDIO_CODEC_PORT_TYPES_H
#define OFFSET1_VAL0 0
#define OFFSET1_VAL1 1
#define OFFSET1_VAL2 2
#define OFFSET1_VAL3 3
#define OFFSET1_VAL4 4
#define OFFSET1_VAL5 5
#define OFFSET1_VAL6 6
#define OFFSET1_VAL7 7
#define OFFSET1_VAL8 8
#define OFFSET1_VAL9 9
#define OFFSET1_VAL10 10
#define OFFSET1_VAL11 11
#define OFFSET1_VAL12 12
#define OFFSET1_VAL13 13
#define OFFSET1_VAL14 14
#define OFFSET1_VAL15 15
#define OFFSET1_VAL16 16
#define OFFSET1_VAL17 17
#define OFFSET1_VAL18 18
#define OFFSET1_VAL19 19
#define OFFSET1_VAL20 20
#define OFFSET1_VAL21 21
#define OFFSET1_VAL22 22
#define OFFSET1_VAL23 23
#define OFFSET1_VAL24 24
#define OFFSET1_VAL25 25
#define LANE0 0
#define LANE1 1
#define LANE2 2
#define SPKR_L 1
#define SPKR_L_COMP 2
#define SPKR_L_BOOST 3
#define SPKR_R 4
#define SPKR_R_COMP 5
#define SPKR_R_BOOST 6
#define PBR 7
#define SPKR_HAPT 8
#define OCPM 9
#define SPKR_L_VI 10
#define SPKR_R_VI 11
#define SPKR_IPCM 12
#define CPS 13
#define HPH_L 14
#define HPH_R 15
#define COMP_L 16
#define COMP_R 17
#define CLSH 18
#define LO 19
#define DSD_L 20
#define DSD_R 21
#define PCM_OUT1 22
#define GPPO 23
#define HAPT 24
#define HIFI 25
#define HPTH 26
#define CMPT 27
#define IPCM 28
#define MBHC 29
#define ADC1 30
#define ADC2 31
#define ADC3 32
#define ADC4 33
#define DMIC0 34
#define DMIC1 35
#define DMIC2 36
#define DMIC3 37
#define DMIC4 38
#define DMIC5 39
#define DMIC6 40
#define DMIC7 41
#define DMIC8 42
#define DMIC9 43
#define DMIC10 44
#define SWRM_TX_PCM_OUT 45
#define SWRM_TX1_CH1 46
#define SWRM_TX1_CH2 47
#define SWRM_TX1_CH3 48
#define SWRM_TX1_CH4 49
#define SWRM_TX2_CH1 50
#define SWRM_TX2_CH2 51
#define SWRM_TX2_CH3 52
#define SWRM_TX2_CH4 53
#define SWRM_TX3_CH1 54
#define SWRM_TX3_CH2 55
#define SWRM_TX3_CH3 56
#define SWRM_TX3_CH4 57
#define SWRM_TX_PCM_IN 58
#define HIFI_PCM_L 59
#define HIFI_PCM_R 60
// BT SWR PORT defines
#define BT_AUDIO_RX1 101
#define BT_AUDIO_TX1 102
#define BT_AUDIO_RX2 103
#define BT_AUDIO_TX2 104
#define BT_AUDIO_RX3 105
#define BT_AUDIO_TX3 106
#define FM_AUDIO_TX1 107
#endif /* __AUDIO_CODEC_PORT_TYPES_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.*/
#ifndef __AUDIO_EXT_CLK_H
#define __AUDIO_EXT_CLK_H
/* Audio External Clocks */
#define AUDIO_PMI_CLK 0
#define AUDIO_PMIC_LNBB_CLK 1
#define AUDIO_LPASS_MCLK 2 /* VA CORE CLK */
#define AUDIO_LPASS_MCLK_2 3 /* WSA1 CORE CLK */
#define AUDIO_LPASS_MCLK_3 4 /* WSA1 NPL CLK */
#define AUDIO_LPASS_MCLK_4 5 /* RX CORE CLK */
#define AUDIO_LPASS_MCLK_5 6 /* RX NPL CLK */
#define AUDIO_LPASS_MCLK_6 7 /* TX CORE CLK */
#define AUDIO_LPASS_MCLK_7 8 /* TX NPL CLK */
#define AUDIO_LPASS_CORE_HW_VOTE 9
#define AUDIO_LPASS_MCLK_8 10 /* VA NPL CLK */
#define AUDIO_LPASS_AUDIO_HW_VOTE 11
#define AUDIO_LPASS_MCLK_9 12 /* WSA2 CORE CLK */
#define AUDIO_LPASS_MCLK_10 13 /* RX_TX CORE CLK */
#define AUDIO_LPASS_MCLK_11 14 /* WSA_TX CORE CLK */
#define AUDIO_LPASS_MCLK_12 15 /* WSA2_TX CORE CLK */
#define AUDIO_LPASS_MCLK_13 16 /* RX_MCLK2 2X CLK */
#define AUDIO_LPASS_MCLK_14 17 /* HW SEQUNCER MCLK */
#define AUDIO_LPASS_MCLK_15 18 /* BT_SWR CLK */
#define AUDIO_LPASS_MCLK_16 19 /* BT_SWR 2X CLK */
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __BOLERO_CODEC_CLK_RSC_H
#define __BOLERO_CODEC_CLK_RSC_H
/* Bolero clock types */
#define TX_CORE_CLK 0
#define RX_CORE_CLK 1
#define WSA_CORE_CLK 2
#define VA_CORE_CLK 3
#define TX_NPL_CLK 4
#define RX_NPL_CLK 5
#define WSA_NPL_CLK 6
#define VA_NPL_CLK 7
#define MAX_CLK 8
#endif /* __BOLERO_CODEC_CLK_RSC_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
#ifndef __DT_BINDINGS_QCOM_GPR_H
#define __DT_BINDINGS_QCOM_GPR_H
/* Domain IDs */
#define GPR_DOMAIN_SIM 0x0
#define GPR_DOMAIN_MODEM 0x1
#define GPR_DOMAIN_ADSP 0x2
#define GPR_DOMAIN_APPS 0x3
#define GPR_DOMAIN_SDSP 0x4
#define GPR_DOMAIN_CDSP 0x5
#define GPR_DOMAIN_MAX 0x6
/* ADSP service IDs */
#define GPR_SVC_ADSP_CORE 0x3
#define GPR_SVC_AFE 0x4
#define GPR_SVC_VSM 0x5
#define GPR_SVC_VPM 0x6
#define GPR_SVC_ASM 0x7
#define GPR_SVC_ADM 0x8
#define GPR_SVC_ADSP_MVM 0x09
#define GPR_SVC_ADSP_CVS 0x0A
#define GPR_SVC_ADSP_CVP 0x0B
#define GPR_SVC_USM 0x0C
#define GPR_SVC_LSM 0x0D
#define GPR_SVC_VIDC 0x16
#define GPR_SVC_MAX 0x17
#endif /* __DT_BINDINGS_QCOM_GPR_H */

20
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#ifndef __LPASS_CDC_CLK_RSC_H
#define __LPASS_CDC_CLK_RSC_H
/* LPASS codec clock types */
#define TX_CORE_CLK 0
#define RX_CORE_CLK 1
#define WSA_CORE_CLK 2
#define VA_CORE_CLK 3
#define WSA2_CORE_CLK 4
#define RX_TX_CORE_CLK 5
#define WSA_TX_CORE_CLK 6
#define WSA2_TX_CORE_CLK 7
#define MAX_CLK 8
#endif /* __LPASS_CDC_CLK_RSC_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014, 2017, 2020 The Linux Foundation. All rights reserved.
*/
#ifndef _AUDIO_CALIBRATION_H
#define _AUDIO_CALIBRATION_H
#include <audio/linux/msm_audio_calibration.h>
/* Used by driver in buffer_number field to notify client
* To update all blocks, for example: freeing all memory
*/
#define ALL_CAL_BLOCKS -1
struct audio_cal_callbacks {
int (*alloc)(int32_t cal_type, size_t data_size, void *data);
int (*dealloc)(int32_t cal_type, size_t data_size, void *data);
int (*pre_cal)(int32_t cal_type, size_t data_size, void *data);
int (*set_cal)(int32_t cal_type, size_t data_size, void *data);
int (*get_cal)(int32_t cal_type, size_t data_size, void *data);
int (*post_cal)(int32_t cal_type, size_t data_size, void *data);
};
struct audio_cal_reg {
int32_t cal_type;
struct audio_cal_callbacks callbacks;
};
int audio_cal_register(int num_cal_types, struct audio_cal_reg *reg_data);
int audio_cal_deregister(int num_cal_types, struct audio_cal_reg *reg_data);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved.
*/
#ifndef __AUDIO_NOTIFIER_H_
#define __AUDIO_NOTIFIER_H_
/* State of the notifier domain */
enum {
AUDIO_NOTIFIER_SERVICE_DOWN,
AUDIO_NOTIFIER_SERVICE_UP
};
/* Service order determines connection priority
* Highest number connected first
*/
enum {
AUDIO_NOTIFIER_SSR_SERVICE,
AUDIO_NOTIFIER_PDR_SERVICE,
AUDIO_NOTIFIER_MAX_SERVICES
};
enum {
AUDIO_NOTIFIER_ADSP_DOMAIN,
AUDIO_NOTIFIER_MODEM_DOMAIN,
AUDIO_NOTIFIER_MAX_DOMAINS
};
/* Structure populated in void *data of nb function
* callback used for audio_notifier_register
*/
struct audio_notifier_cb_data {
int service;
int domain;
};
#if IS_ENABLED(CONFIG_MSM_QDSP6_NOTIFIER)
/*
* Use audio_notifier_register to register any audio
* clients who need to be notified of a remote process.
* This API will determine and register the client with
* the best available subsystem (SSR or PDR) for that
* domain (Adsp or Modem). When an event is sent from that
* domain the notifier block callback function will be called.
*
* client_name - A unique user name defined by the client.
* If the same name is used for multiple calls each will
* be tracked & called back separately and a single call
* to deregister will delete them all.
* domain - Domain the client wants to get events from.
* AUDIO_NOTIFIER_ADSP_DOMAIN
* AUDIO_NOTIFIER_MODEM_DOMAIN
* *nb - Pointer to a notifier block. Provide a callback function
* to be notified of an even on that domain.
*
* nb_func(struct notifier_block *this, unsigned long opcode, void *data)
* this - pointer to own nb
* opcode - event from registered domain
* AUDIO_NOTIFIER_SERVICE_DOWN
* AUDIO_NOTIFIER_SERVICE_UP
* *data - pointer to struct audio_notifier_cb_data
*
* Returns: Success: 0
* Error: -#
*/
int audio_notifier_register(char *client_name, int domain,
struct notifier_block *nb);
/*
* Use audio_notifier_deregister to deregister the clients from
* all domains registered using audio_notifier_register that
* match the client name.
*
* client_name - Unique user name used in audio_notifier_register.
* Returns: Success: 0
* Error: -#
*/
int audio_notifier_deregister(char *client_name);
bool audio_notifier_probe_status(void);
#else
static inline int audio_notifier_register(char *client_name, int domain,
struct notifier_block *nb)
{
return 0;
}
static inline int audio_notifier_deregister(char *client_name)
{
return 0;
}
static inline bool audio_notifier_probe_status(void)
{
return 0;
}
#endif /* CONFIG_MSM_QDSP6_NOTIFIER */
#endif

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/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AUDIO_PRM_H__
#define __AUDIO_PRM_H__
#define PRM_MODULE_INSTANCE_ID 0x00000002
/* Request and release response payload of the #PRM_CMD_RSP_REQUEST_HW_RSC
* and PRM_CMD_RSP_ RELEASE_HW_RSC commands respectively.
* This is sent in response to request and release common payload commands.
*/
struct prm_rsp_req_rel_hw_rsc {
/* ID of the resource being requested. The supported values
* are HW_RSC_ID_AUDIO_HW_CLK and HW_RSC_ID_LPASS_CORE_CLK.
*/
uint32_t param_id;
/* Overall command response status with value 0 for success and non-zero
* value for command failure. In case of partial or complete command
* failure, this field is followed by resource specific response payload.
*/
uint32_t status;
};
/* Clock configuration structure for request */
struct clk_cfg {
/* Unique ID of the clock being requested. */
uint32_t clk_id;
/* Clock frequency in Hz. */
uint32_t clk_freq_in_hz;
/* Clock attributes with values
* 0:invalid
* 1:CLOCK_ATTR_NO_COUPLING
* 2:CLOCK_ATTR_COUPLE_DIVIDEND
* 3:CLOCK_ATTR_COUPLE_DIVISOR
* 4:CLOCK_ATTR_INVERT_NO_COUPLING*/
uint32_t clk_attri;
/* Clock root for this clock with 0 as DEFAULT. */
uint32_t clk_root;
};
/* Below payload is used to report failed clock ID's and error code. */
struct hw_rsc_clk_req_rel_rsp {
/* Number of failures while requesting for 1 or more clock IDs. */
uint32_t num_failures;
};
/* Clock status structure for response payload */
struct clock_status {
/* ID of the clock being requested as part of the REQUEST
* command and resulted in failure.
*/
uint32_t clock_id;
/* Error code corresponding to failure occurred while
* requesting this clock ID.
*/
uint32_t status;
};
typedef struct apm_cmd_header_t
{
uint32_t payload_address_lsw;
/**< Lower 32 bits of the payload address. */
uint32_t payload_address_msw;
/**< Upper 32 bits of the payload address.
The 64-bit number formed by payload_address_lsw and
payload_address_msw must be aligned to a 32-byte boundary and be in
contiguous memory.
@values
- For a 32-bit shared memory address, this field must be set to 0.
- For a 36-bit shared memory address, bits 31 to 4 of this field must
be set to 0. @tablebulletend */
uint32_t mem_map_handle;
/**< Unique identifier for a shared memory address.
@values
- NULL -- The message is in the payload (in-band).
- Non-NULL -- The parameter data payload begins at the address
specified by a pointer to the physical address of the payload in
shared memory (out-of-band).
@contcell
The aDSP returns this memory map handle through
#apm_CMD_SHARED_MEM_MAP_REGIONS.
An optional field is available if parameter data is in-band:
%afe_port_param_data_v2_t param_data[...].
See <b>Parameter data variable payload</b>. */
uint32_t payload_size;
/**< Actual size of the variable payload accompanying the message or in
shared memory. This field is used for parsing both in-band and
out-of-band data.
@values > 0 bytes, in multiples of 4 bytes */
}apm_cmd_header_t;
typedef struct apm_module_param_data_t
{
uint32_t module_instance_id;
/**< Valid instance ID of module
@values */
uint32_t param_id;
/**< Valid ID of the parameter.
@values See Chapter */
uint32_t param_size;
/**< Size of the parameter data based upon the
module_instance_id/param_id combination.
@values > 0 bytes, in multiples of
4 bytes at least */
uint32_t error_code;
/**< Error code populated by the entity hosting the module.
Applicable only for out-of-band command mode */
}apm_module_param_data_t;
typedef struct audio_hw_clk_cfg_req_param_t
{
uint32_t num_clock_id;
/**< Number of clock ID's being configured */
}audio_hw_clk_cfg_req_param_t;
typedef struct audio_hw_clk_cfg_t
{
uint32_t clock_id;
/**< Unique Clock ID of the clock being requested */
uint32_t clock_freq;
/**< Clock frequency in Hz to set. */
uint32_t clock_attri;
/**< Divider for two clocks that are coupled, if necessary:
divider = A/B, where A is the dividend and B is the divisor.
@values
- #_CLOCK_ATTRIBUTE_COUPLE_NO -- For no divider-related clocks
- #_CLOCK_ATTRIBUTE_COUPLE_DIVIDEND
- #_CLOCK_ATTRIBUTE_COUPLE_DIVISOR
- #_CLOCK_ATTRIBUTE_INVERT_COUPLE_NO */
uint32_t clock_root;
/**< Root clock source.
@values #_CLOCK_ROOT_DEFAULT
Currently, only _CLOCK_ROOT_DEFAULT is valid. */
}audio_hw_clk_cfg_t;
typedef struct audio_hw_clk_rel_cfg_t
{
uint32_t clock_id;
}audio_hw_clk_rel_cfg_t;
#define MAX_AUD_HW_CLK_NUM_REQ 1
typedef struct prm_cmd_request_rsc_t
{
apm_cmd_header_t payload_header;
apm_module_param_data_t module_payload_0;
audio_hw_clk_cfg_req_param_t num_clk_id_t;
audio_hw_clk_cfg_t clock_ids_t[MAX_AUD_HW_CLK_NUM_REQ];
}prm_cmd_request_rsc_t;
typedef struct prm_cmd_release_rsc_t
{
apm_cmd_header_t payload_header;
apm_module_param_data_t module_payload_0;
audio_hw_clk_cfg_req_param_t num_clk_id_t;
audio_hw_clk_rel_cfg_t clock_ids_t[MAX_AUD_HW_CLK_NUM_REQ];
}prm_cmd_release_rsc_t;
typedef struct prm_cmd_request_hw_core_t
{
apm_cmd_header_t payload_header;
apm_module_param_data_t module_payload_0;
uint32_t hw_core_id;
}prm_cmd_request_hw_core_t;
#define LPR_CPU_SS_SLEEP_DISABLED 1
struct prm_cpu_lpr_request_t {
apm_cmd_header_t payload_header;
apm_module_param_data_t module_payload_0;
uint32_t lpr_state;
};
#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
#define PRM_CMD_RELEASE_HW_RSC 0x01001010
#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
/* Param ID for audio hardware clock */
#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
/** Param ID for CPU low power resource */
#define PARAM_ID_RSC_CPU_LPR 0x08001A6E
/* Param ID for lpass core clock */
#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
#define PARAM_ID_RSC_HW_CORE 0x08001032
/* Param ID for island vote */
#define PARAM_ID_RSC_VOTE_AGAINST_ISLAND 0x0800131D
#define HW_RSC_ID_AUDIO_HW_CLK 0x0800102C
#define MAX_EARPA_REG 2
#define MAX_EARPA_CDC_DUTY_CYC_OPERATION 2
typedef struct audio_hw_codec_op_info_t {
uint32_t hw_codec_op_id;
uint32_t hw_codec_op_value;
} audio_hw_codec_op_info_t;
typedef struct audio_hw_codec_reg_op_info_t {
uint32_t hw_codec_reg_id;
uint32_t hw_codec_reg_addr_msw;
uint32_t hw_codec_reg_addr_lsw;
uint32_t num_ops;
audio_hw_codec_op_info_t hw_codec_op[MAX_EARPA_REG];
} audio_hw_codec_reg_op_info_t;
typedef struct audio_hw_codec_reg_info_t {
uint32_t num_reg_info_t;
audio_hw_codec_reg_op_info_t hw_codec_reg[MAX_EARPA_REG];
} audio_hw_codec_reg_info_t;
typedef struct prm_cmd_request_cdc_duty_cycling_t {
apm_cmd_header_t payload_header;
apm_module_param_data_t module_payload_0;
audio_hw_codec_reg_info_t hw_codec_reg_info_t;
} prm_cmd_request_cdc_duty_cycling_t;
/* earpa_register config */
#define DIG_MUTE_ENABLE 0x34
#define DIG_MUTE_DISABLE 0x24
struct lpass_swr_ear_pa_dep_cfg_t {
uint32_t ear_pa_enable_pkd_reg_addr;
uint32_t ear_pa_disable_pkd_reg_addr;
} __packed;
struct lpass_swr_ear_pa_reg_cfg_t {
uint32_t lpass_cdc_rx0_rx_path_ctl_phy_addr;
uint32_t lpass_wr_fifo_reg_phy_addr;
} __packed;
struct prm_earpa_hw_intf_config {
struct lpass_swr_ear_pa_reg_cfg_t ear_pa_hw_reg_cfg;
struct lpass_swr_ear_pa_dep_cfg_t ear_pa_pkd_cfg;
uint32_t ear_pa_pkd_reg_addr;
const char *backend_used;
} __packed;
#define PARAM_ID_RSC_HW_CODEC_REG_INFO 0x0800131B
#define HW_CODEC_DIG_REG_ID_MUTE_CTRL 0x1
#define HW_CODEC_OP_DIG_MUTE_ENABLE 0x1
#define HW_CODEC_OP_DIG_MUTE_DISABLE 0x2
#define HW_CODEC_ANALOG_REG_ID_CMD_FIFO_WRITE 0x2
#define HW_CODEC_OP_ANA_PGA_ENABLE 0x3
#define HW_CODEC_OP_ANA_PGA_DISABLE 0x4
/* Supported OSR clock values */
#define OSR_CLOCK_12_P288_MHZ 0xBB8000
#define OSR_CLOCK_11_P2896_MHZ 0xAC4400
#define OSR_CLOCK_9_P600_MHZ 0x927C00
#define OSR_CLOCK_8_P192_MHZ 0x7D0000
#define OSR_CLOCK_6_P144_MHZ 0x5DC000
#define OSR_CLOCK_4_P096_MHZ 0x3E8000
#define OSR_CLOCK_3_P072_MHZ 0x2EE000
#define OSR_CLOCK_2_P048_MHZ 0x1F4000
#define OSR_CLOCK_1_P536_MHZ 0x177000
#define OSR_CLOCK_1_P024_MHZ 0xFA000
#define OSR_CLOCK_768_kHZ 0xBB800
#define OSR_CLOCK_512_kHZ 0x7D000
#define OSR_CLOCK_DISABLE 0x0
/* Supported Bit clock values */
#define IBIT_CLOCK_12_P288_MHZ 0xBB8000
#define IBIT_CLOCK_11_P2896_MHZ 0xAC4400
#define IBIT_CLOCK_8_P192_MHZ 0x7D0000
#define IBIT_CLOCK_6_P144_MHZ 0x5DC000
#define IBIT_CLOCK_4_P096_MHZ 0x3E8000
#define IBIT_CLOCK_3_P072_MHZ 0x2EE000
#define IBIT_CLOCK_2_P8224_MHZ 0x2b1100
#define IBIT_CLOCK_2_P048_MHZ 0x1F4000
#define IBIT_CLOCK_1_P536_MHZ 0x177000
#define IBIT_CLOCK_1_P4112_MHZ 0x158880
#define IBIT_CLOCK_1_P024_MHZ 0xFA000
#define IBIT_CLOCK_768_KHZ 0xBB800
#define IBIT_CLOCK_512_KHZ 0x7D000
#define IBIT_CLOCK_256_KHZ 0x3E800
#define IBIT_CLOCK_DISABLE 0x0
/** Clock ID of the primary MI2S internal bit clock (IBIT). */
#define CLOCK_ID_PRI_MI2S_IBIT 0x100
/** Clock ID of the primary MI2S external bit clock (EBIT). */
#define CLOCK_ID_PRI_MI2S_EBIT 0x101
/** Clock ID of the secondary MI2S IBIT. */
#define CLOCK_ID_SEC_MI2S_IBIT 0x102
/** Clock ID of the secondary MI2S EBIT. */
#define CLOCK_ID_SEC_MI2S_EBIT 0x103
/** Clock ID of the tertiary MI2S IBIT. */
#define CLOCK_ID_TER_MI2S_IBIT 0x104
/** Clock ID of the tertiary MI2S EBIT. */
#define CLOCK_ID_TER_MI2S_EBIT 0x105
/** Clock ID of the quaternary MI2S IBIT. */
#define CLOCK_ID_QUAD_MI2S_IBIT 0x106
/** Clock ID of the quaternary MI2S EBIT. */
#define CLOCK_ID_QUAD_MI2S_EBIT 0x107
/** Clock ID of the quinary MI2S IBIT. */
#define CLOCK_ID_QUI_MI2S_IBIT 0x108
/** Clock ID of the quinary MI2S EBIT. */
#define CLOCK_ID_QUI_MI2S_EBIT 0x109
/** Clock ID of the quinary MI2S OSR. */
#define CLOCK_ID_QUI_MI2S_OSR 0x10A
/** Clock ID of the senary MI2S IBIT. */
#define CLOCK_ID_SEN_MI2S_IBIT 0x10B
/** Clock ID of the senary MI2S EBIT. */
#define CLOCK_ID_SEN_MI2S_EBIT 0x10C
/** Clock ID of the septenary MI2S IBIT. */
#define CLOCK_ID_SEP_MI2S_IBIT 0x10D
/** Clock ID of the septenary MI2S EBIT. */
#define CLOCK_ID_SEP_MI2S_EBIT 0x10E
/** ID of I2S IBIT clock 0 that is used with integrated codec. */
#define CLOCK_ID_INT0_I2S_IBIT 0x10D
/** ID of I2S IBIT clock 1 that is used with integrated codec. */
#define CLOCK_ID_INT1_I2S_IBIT 0x10E
/** ID of I2S IBIT clock 2 that is used with integrated codec. */
#define CLOCK_ID_INT2_I2S_IBIT 0x10F
/** ID of I2S IBIT clock 3 that is used with integrated codec. */
#define CLOCK_ID_INT3_I2S_IBIT 0x110
/** ID of I2S IBIT clock 4 that is used with integrated codec. */
#define CLOCK_ID_INT4_I2S_IBIT 0x111
/** ID of I2S IBIT clock 5 that is used with integrated codec. */
#define CLOCK_ID_INT5_I2S_IBIT 0x112
/** ID of I2S IBIT clock 6 that is used with integrated codec. */
#define CLOCK_ID_INT6_I2S_IBIT 0x113
/** Clock ID of the primary PCM IBIT. */
#define CLOCK_ID_PRI_PCM_IBIT 0x200
/** Clock ID of the primary PCM EBIT. */
#define CLOCK_ID_PRI_PCM_EBIT 0x201
/** Clock ID of the secondary PCM IBIT. */
#define CLOCK_ID_SEC_PCM_IBIT 0x202
/** Clock ID of the secondary PCM EBIT. */
#define CLOCK_ID_SEC_PCM_EBIT 0x203
/** Clock ID of the tertiary PCM IBIT. */
#define CLOCK_ID_TER_PCM_IBIT 0x204
/** Clock ID of the tertiary PCM EBIT. */
#define CLOCK_ID_TER_PCM_EBIT 0x205
/** Clock ID of the quaternary PCM IBIT. */
#define CLOCK_ID_QUAD_PCM_IBIT 0x206
/** Clock ID of the quaternary PCM EBIT. */
#define CLOCK_ID_QUAD_PCM_EBIT 0x207
/** Clock ID of the quinary PCM IBIT. */
#define CLOCK_ID_QUI_PCM_IBIT 0x208
/** Clock ID of the quinary PCM EBIT. */
#define CLOCK_ID_QUI_PCM_EBIT 0x209
/** Clock ID of the quinary PCM OSR. */
#define CLOCK_ID_QUI_PCM_OSR 0x20A
/** Clock ID of the senary PCM IBIT. */
#define CLOCK_ID_SEN_PCM_IBIT 0x20B
/** Clock ID of the senary PCM EBIT. */
#define CLOCK_ID_SEN_PCM_EBIT 0x20C
/** Clock ID for the primary TDM IBIT. */
#define CLOCK_ID_PRI_TDM_IBIT 0x200
/** Clock ID for the primary TDM EBIT. */
#define CLOCK_ID_PRI_TDM_EBIT 0x201
/** Clock ID for the secondary TDM IBIT. */
#define CLOCK_ID_SEC_TDM_IBIT 0x202
/** Clock ID for the secondary TDM EBIT. */
#define CLOCK_ID_SEC_TDM_EBIT 0x203
/** Clock ID for the tertiary TDM IBIT. */
#define CLOCK_ID_TER_TDM_IBIT 0x204
/** Clock ID for the tertiary TDM EBIT. */
#define CLOCK_ID_TER_TDM_EBIT 0x205
/** Clock ID for the quaternary TDM IBIT. */
#define CLOCK_ID_QUAD_TDM_IBIT 0x206
/** Clock ID for the quaternary TDM EBIT. */
#define CLOCK_ID_QUAD_TDM_EBIT 0x207
/** Clock ID for the quinary TDM IBIT. */
#define CLOCK_ID_QUI_TDM_IBIT 0x208
/** Clock ID for the quinary TDM EBIT. */
#define CLOCK_ID_QUI_TDM_EBIT 0x209
/** Clock ID for the quinary TDM OSR. */
#define CLOCK_ID_QUI_TDM_OSR 0x20A
/** Clock ID for the senary TDM IBIT. */
#define CLOCK_ID_SEN_TDM_IBIT 0x20B
/** Clock ID for the senary TDM EBIT. */
#define CLOCK_ID_SEN_TDM_EBIT 0x20C
/** Clock ID of the septenary TDM IBIT. */
#define CLOCK_ID_SEP_TDM_IBIT 0x20D
/** Clock ID of the septenary TDM EBIT. */
#define CLOCK_ID_SEP_TDM_EBIT 0x20E
/** Clock ID for MCLK 1. */
#define CLOCK_ID_MCLK_1 0x300
/** Clock ID for MCLK 2. */
#define CLOCK_ID_MCLK_2 0x301
/** Clock ID for MCLK 3. */
#define CLOCK_ID_MCLK_3 0x302
/** Clock ID for MCLK 4. */
#define CLOCK_ID_MCLK_4 0x303
/** Clock ID for MCLK 5. */
#define CLOCK_ID_MCLK_5 0x304
/** Clock ID for MCLK for WSA core */
#define CLOCK_ID_WSA_CORE_MCLK 0x305
/** Clock ID for NPL MCLK for WSA core */
#define CLOCK_ID_WSA_CORE_NPL_MCLK 0x306
/** Clock ID for 2X WSA MCLK (2X MCLK or NPL MCLK, both are same) */
#define CLOCK_ID_WSA_CORE_2X_MCLK CLOCK_ID_WSA_CORE_NPL_MCLK
/** Clock ID for MCLK for VA core */
#define CLOCK_ID_VA_CORE_MCLK 0x307
/** Clock ID for MCLK for TX */
#define CLOCK_ID_TX_CORE_MCLK 0x30C
/** Clock ID for RX Core TX MCLK */
#define CLOCK_ID_RX_CORE_TX_MCLK 0x312
/** Clock ID for WSA core TX MCLK */
#define CLOCK_ID_WSA_CORE_TX_MCLK 0x314
/** Clock ID for WSA2 core TX MCLK */
#define CLOCK_ID_WSA2_CORE_TX_MCLK 0x316
/** Clock ID for the primary SPDIF output core. */
#define CLOCK_ID_PRI_SPDIF_OUTPUT_CORE 0x400
/** Clock ID for the secondary SPDIF output core. */
#define CLOCK_ID_SEC_SPDIF_OUTPUT_CORE 0x401
/** Clock ID for the primary SPDIF input core. */
#define CLOCK_ID_PRI_SPDIF_INPUT_CORE 0x402
/** Clock ID for the secondary SPDIF input core. */
#define CLOCK_ID_SEC_SPDIF_INPUT_CORE 0x403
/** Clock ID for the secondary SPDIF output NPL clk. */
#define CLOCK_ID_PRI_SPDIF_OUTPUT_NPL 0x404
/** Clock ID for the primary SPDIF output NPL clk. */
#define CLOCK_ID_SEC_SPDIF_OUTPUT_NPL 0x405
/** Clock attribute is invalid (reserved for internal use). */
#define CLOCK_ATTRIBUTE_INVALID 0x0
/** Clock attribute for no coupled clocks. */
#define CLOCK_ATTRIBUTE_COUPLE_NO 0x1
/** Clock attribute for the dividend of the coupled clocks. */
#define CLOCK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
/** Clock attribute for the divisor of the coupled clocks. */
#define CLOCK_ATTRIBUTE_COUPLE_DIVISOR 0x3
/** Clock attribute for the invert-and-no-couple case. */
#define CLOCK_ATTRIBUTE_INVERT_COUPLE_NO 0x4
/** Default root clock source. */
#define CLOCK_ROOT_DEFAULT 0x0
/** Hardware core identifier for LPASS. */
#define HW_CORE_ID_LPASS 0x1
/** Hardware core identifier for digital codec. */
#define HW_CORE_ID_DCODEC 0x2
/** Default clock source. */
#define CLOCK_ROOT_SRC_DEFAULT 0x0
/** Xo Clock source. */
#define CLOCK_ROOT_SRC_XO 0x1
/** RCO Clock source. */
#define CLOCK_ROOT_SRC_RCO 0x2
int audio_prm_set_lpass_clk_cfg(struct clk_cfg *cfg, uint8_t enable);
int audio_prm_set_lpass_hw_core_req(struct clk_cfg *cfg, uint32_t hw_core_id, uint8_t enable);
int audio_prm_set_cdc_earpa_duty_cycling_req(struct prm_earpa_hw_intf_config *earpa_config,
uint32_t enable);
void audio_prm_set_lpi_logging_status(int lpi_pcm_logging_enable);
int audio_prm_set_vote_against_sleep(uint8_t enable);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef DIGITAL_CDC_RSC_MGR_H
#define DIGITAL_CDC_RSC_MGR_H
#include <linux/clk.h>
#ifdef CONFIG_DIGITAL_CDC_RSC_MGR
int digital_cdc_rsc_mgr_hw_vote_enable(struct clk *vote_handle, struct device *dev);
void digital_cdc_rsc_mgr_hw_vote_disable(struct clk *vote_handle, struct device *dev);
void digital_cdc_rsc_mgr_hw_vote_reset(struct clk *vote_handle);
void digital_cdc_rsc_mgr_init(void);
void digital_cdc_rsc_mgr_exit(void);
#else
static inline int digital_cdc_rsc_mgr_hw_vote_enable(struct clk *vote_handle, struct device *dev)
{
return 0;
}
static inline void digital_cdc_rsc_mgr_hw_vote_disable(struct clk *vote_handle, struct device *dev)
{
}
static inline void digital_cdc_rsc_mgr_hw_vote_reset(struct clk *vote_handle)
{
}
static inline void digital_cdc_rsc_mgr_init(void)
{
}
static inline void digital_cdc_rsc_mgr_exit(void)
{
}
#endif /* CONFIG_DIGITAL_CDC_RSC_MGR */
#endif /* DIGITAL_CDC_RSC_MGR_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __MSM_AUDIO_EVENT_NOTIFY_H_
#define __MSM_AUDIO_EVENT_NOTIFY_H_
#include <linux/notifier.h>
#if (IS_ENABLED(CONFIG_SND_SOC_MSM_QDSP6V2_INTF) || \
IS_ENABLED(CONFIG_SND_SOC_MSM_QDSP6V2_VM))
int msm_aud_evt_register_client(struct notifier_block *nb);
int msm_aud_evt_unregister_client(struct notifier_block *nb);
int msm_aud_evt_notifier_call_chain(unsigned long val, void *v);
int msm_aud_evt_blocking_register_client(struct notifier_block *nb);
int msm_aud_evt_blocking_unregister_client(struct notifier_block *nb);
int msm_aud_evt_blocking_notifier_call_chain(unsigned long val, void *v);
#else
static inline int msm_aud_evt_register_client(struct notifier_block *nb)
{
return -ENOSYS;
}
static inline int msm_aud_evt_unregister_client(struct notifier_block *nb)
{
return -ENOSYS;
}
static inline int msm_aud_evt_notifier_call_chain(unsigned long val, void *v)
{
return -ENOSYS;
}
static inline int msm_aud_evt_blocking_register_client(
struct notifier_block *nb)
{
return -ENOSYS;
}
static inline int msm_aud_evt_blocking_unregister_client(
struct notifier_block *nb)
{
return -ENOSYS;
}
static inline int msm_aud_evt_blocking_notifier_call_chain(
unsigned long val, void *v)
{
return -ENOSYS;
}
#endif
enum {
MSM_AUD_DC_EVENT = 1,
SWR_WAKE_IRQ_REGISTER,
SWR_WAKE_IRQ_DEREGISTER,
SWR_WAKE_IRQ_EVENT,
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013-2015, 2017-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _LINUX_MSM_AUDIO_ION_H
#define _LINUX_MSM_AUDIO_ION_H
#include <sound/pcm.h>
#include <linux/msm_ion.h>
#include <linux/dma-mapping.h>
enum {
HLOS_TO_ADSP = 1,
ADSP_TO_HLOS,
};
#define VMID_CP_ADSP_SHARED 33
enum {
MSM_AUDIO_ION_INV_CACHES = 0,
MSM_AUDIO_ION_CLEAN_CACHES,
};
struct audio_buffer {
dma_addr_t phys;
void *data;
uint32_t used;
uint32_t size;/* size of buffer */
uint32_t actual_size; /* actual number of bytes read by DSP */
struct dma_buf *dma_buf;
};
int msm_audio_get_phy_addr(int fd, dma_addr_t *paddr, size_t *pa_len);
void msm_audio_ion_crash_handler(void);
#endif /* _LINUX_MSM_AUDIO_ION_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#ifndef __SP_PARAMS_H__
#define __SP_PARAMS_H__
#if IS_ENABLED(CONFIG_XT_LOGGING)
int afe_get_sp_xt_logging_data(u16 port_id);
#else
static inline int afe_get_sp_xt_logging_data(u16 port_id)
{
return 0;
}
#endif
#endif /* __SP_PARAMS_H__ */

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/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SPF_CORE_H__
#define __SPF_CORE_H__
#include <ipc/gpr-lite.h>
bool spf_core_is_apm_ready(int timeout_ms);
void spf_core_apm_close_all(void);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2010-2017, 2019-2021, The Linux Foundation. All rights reserved.
*/
#ifndef __APR_H_
#define __APR_H_
#include <linux/mutex.h>
enum apr_subsys_state {
APR_SUBSYS_DOWN,
APR_SUBSYS_UP,
APR_SUBSYS_LOADED,
APR_SUBSYS_UNKNOWN,
};
struct apr_q6 {
void *pil;
atomic_t q6_state;
atomic_t modem_state;
struct mutex lock;
/*
* ToDo - Multiple client support to be added.
* And checking for state UNKNOWN currently.
*/
void (*state_notify_cb)(enum apr_subsys_state state,
void *client_handle);
void *client_handle;
};
struct apr_hdr {
uint16_t hdr_field;
uint16_t pkt_size;
uint8_t src_svc;
uint8_t src_domain;
uint16_t src_port;
uint8_t dest_svc;
uint8_t dest_domain;
uint16_t dest_port;
uint32_t token;
uint32_t opcode;
};
#define APR_HDR_LEN(hdr_len) ((hdr_len)/4)
#define APR_PKT_SIZE(hdr_len, payload_len) ((hdr_len) + (payload_len))
#define APR_HDR_FIELD(msg_type, hdr_len, ver)\
(((msg_type & 0x3) << 8) | ((hdr_len & 0xF) << 4) | (ver & 0xF))
#define APR_HDR_SIZE sizeof(struct apr_hdr)
/* Version */
#define APR_PKT_VER 0x0
/* Command and Response Types */
#define APR_MSG_TYPE_EVENT 0x0
#define APR_MSG_TYPE_CMD_RSP 0x1
#define APR_MSG_TYPE_SEQ_CMD 0x2
#define APR_MSG_TYPE_NSEQ_CMD 0x3
#define APR_MSG_TYPE_MAX 0x04
/* APR Basic Response Message */
#define APR_BASIC_RSP_RESULT 0x000110E8
#define APR_RSP_ACCEPTED 0x000100BE
/* Domain IDs */
#define APR_DOMAIN_SIM 0x1
#define APR_DOMAIN_PC 0x2
#define APR_DOMAIN_MODEM 0x3
#define APR_DOMAIN_ADSP 0x4
#define APR_DOMAIN_APPS 0x5
#define APR_DOMAIN_MAX 0x6
/* ADSP service IDs */
#define APR_SVC_TEST_CLIENT 0x2
#define APR_SVC_ADSP_CORE 0x3
#define APR_SVC_AFE 0x4
#define APR_SVC_VSM 0x5
#define APR_SVC_VPM 0x6
#define APR_SVC_ASM 0x7
#define APR_SVC_ADM 0x8
#define APR_SVC_ADSP_MVM 0x09
#define APR_SVC_ADSP_CVS 0x0A
#define APR_SVC_ADSP_CVP 0x0B
#define APR_SVC_USM 0x0C
#define APR_SVC_LSM 0x0D
#define APR_SVC_VIDC 0x16
#define APR_SVC_MAX 0x17
/* Modem Service IDs */
#define APR_SVC_MVS 0x3
#define APR_SVC_MVM 0x4
#define APR_SVC_CVS 0x5
#define APR_SVC_CVP 0x6
#define APR_SVC_SRD 0x7
/* APR Port IDs */
#define APR_MAX_PORTS 0x80
#define APR_NAME_MAX 0x40
#define RESET_EVENTS 0x000130D7
#define LPASS_RESTART_EVENT 0x1000
#define LPASS_RESTART_READY 0x1001
struct apr_client_data {
uint16_t reset_event;
uint16_t reset_proc;
uint16_t payload_size;
uint16_t hdr_len;
uint16_t msg_type;
uint16_t src;
uint16_t dest_svc;
uint16_t src_port;
uint16_t dest_port;
uint32_t token;
uint32_t opcode;
void *payload;
};
typedef int32_t (*apr_fn)(struct apr_client_data *data, void *priv);
struct apr_svc {
uint16_t id;
uint16_t dest_id;
uint16_t client_id;
uint16_t dest_domain;
uint8_t rvd;
uint8_t port_cnt;
uint8_t svc_cnt;
uint8_t need_reset;
apr_fn port_fn[APR_MAX_PORTS];
void *port_priv[APR_MAX_PORTS];
apr_fn fn;
void *priv;
struct mutex m_lock;
spinlock_t w_lock;
uint8_t pkt_owner;
#ifdef CONFIG_MSM_QDSP6_APRV2_VM
uint16_t vm_dest_svc;
uint32_t vm_handle;
#endif
};
struct apr_client {
uint8_t id;
uint8_t svc_cnt;
uint8_t rvd;
struct mutex m_lock;
struct apr_svc_ch_dev *handle;
struct apr_svc svc[APR_SVC_MAX];
};
struct apr_rx_intents {
int num_of_intents;
uint32_t size;
};
struct apr_pkt_cfg {
uint8_t pkt_owner;
struct apr_rx_intents intents;
};
int apr_load_adsp_image(void);
struct apr_client *apr_get_client(int dest_id, int client_id);
int apr_wait_for_device_up(int dest_id);
int apr_get_svc(const char *svc_name, int dest_id, int *client_id,
int *svc_idx, int *svc_id);
void apr_cb_func(void *buf, int len, void *priv);
struct apr_svc *apr_register(char *dest, char *svc_name, apr_fn svc_fn,
uint32_t src_port, void *priv);
inline int apr_fill_hdr(void *handle, uint32_t *buf, uint16_t src_port,
uint16_t msg_type, uint16_t dest_port,
uint32_t token, uint32_t opcode, uint16_t len);
int apr_send_pkt(void *handle, uint32_t *buf);
int apr_deregister(void *handle);
void subsys_notif_register(char *client_name, int domain,
struct notifier_block *nb);
void subsys_notif_deregister(char *client_name);
int apr_get_dest_id(char *dest);
uint16_t apr_get_data_src(struct apr_hdr *hdr);
void change_q6_state(int state);
void q6audio_dsp_not_responding(void);
void apr_reset(void *handle);
enum apr_subsys_state apr_get_subsys_state(void);
enum apr_subsys_state apr_get_modem_state(void);
void apr_set_modem_state(enum apr_subsys_state state);
enum apr_subsys_state apr_get_q6_state(void);
int apr_set_q6_state(enum apr_subsys_state state);
void apr_set_subsys_state(void);
const char *apr_get_lpass_subsys_name(void);
uint16_t apr_get_reset_domain(uint16_t proc);
int apr_start_rx_rt(void *handle);
int apr_end_rx_rt(void *handle);
void apr_register_adsp_state_cb(void *adsp_cb, void *client_handle);
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016-2017, 2019 The Linux Foundation. All rights reserved.
*/
#ifndef __APRV2_VM_H__
#define __APRV2_VM_H__
#define APRV2_VM_MAX_DNS_SIZE (31)
/* Includes NULL character. */
#define APRV2_VM_PKT_SERVICE_ID_MASK (0x00FF)
/* Bitmask of the service ID field. */
/* Packet Structure Definition */
struct aprv2_vm_packet_t {
uint32_t header;
uint16_t src_addr;
uint16_t src_port;
uint16_t dst_addr;
uint16_t dst_port;
uint32_t token;
uint32_t opcode;
};
/**
* In order to send command/event via MM HAB, the following buffer
* format shall be followed, where the buffer is provided to the
* HAB send API.
* |-----cmd_id or evt_id -----| <- 32 bit, e.g. APRV2_VM_CMDID_REGISTER
* |-----cmd payload ----------| e.g. aprv2_vm_cmd_register_t
* | ... |
*
* In order to receive a command response or event ack, the following
* buffer format shall be followed, where the buffer is provided to
* the HAB receive API.
* |-----cmd response ---------| e.g. aprv2_vm_cmd_register_rsp_t
* | ... |
*/
/* Registers a service with the backend APR driver. */
#define APRV2_VM_CMDID_REGISTER (0x00000001)
struct aprv2_vm_cmd_register_t {
uint32_t name_size;
/**< The service name string size in bytes. */
char name[APRV2_VM_MAX_DNS_SIZE];
/**<
* The service name string to register.
*
* A NULL name means the service does not have a name.
*/
uint16_t addr;
/**<
* The address to register.
*
* A zero value means to auto-generate a free dynamic address.
* A non-zero value means to directly use the statically assigned address.
*/
};
struct aprv2_vm_cmd_register_rsp_t {
int32_t status;
/**< The status of registration. */
uint32_t handle;
/**< The registered service handle. */
uint16_t addr;
/**< The actual registered address. */
};
#define APRV2_VM_CMDID_DEREGISTER (0x00000002)
struct aprv2_vm_cmd_deregister_t {
uint32_t handle;
/**< The registered service handle. */
};
struct aprv2_vm_cmd_deregister_rsp_t {
int32_t status;
/**< The status of de-registration. */
};
#define APRV2_VM_CMDID_ASYNC_SEND (0x00000003)
struct aprv2_vm_cmd_async_send_t {
uint32_t handle;
/**< The registered service handle. */
struct aprv2_vm_packet_t pkt_header;
/**< The packet header. */
/* The apr packet payload follows */
};
struct aprv2_vm_cmd_async_send_rsp_t {
int32_t status;
/**< The status of send. */
};
#define APRV2_VM_EVT_RX_PKT_AVAILABLE (0x00000004)
struct aprv2_vm_evt_rx_pkt_available_t {
struct aprv2_vm_packet_t pkt_header;
/**< The packet header. */
/* The apr packet payload follows */
};
struct aprv2_vm_ack_rx_pkt_available_t {
int32_t status;
};
#endif /* __APRV2_VM_H__ */

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/* Copyright (c) 2011-2017, 2019-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2018, Linaro Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __QCOM_GPR_H_
#define __QCOM_GPR_H_
#include <linux/spinlock.h>
#include <linux/device.h>
#include "soc/audio_mod_devicetable.h"
#include <bindings/qcom,gpr.h>
extern struct bus_type gprbus;
enum gpr_subsys_state {
GPR_SUBSYS_DOWN,
GPR_SUBSYS_UP,
GPR_SUBSYS_LOADED,
};
struct gpr_q6 {
//void *pil;
atomic_t q6_state;
atomic_t modem_state;
struct mutex lock;
};
/* Version */
#define GPR_PKT_VER 0x0
/*
* Header format
* Bits 3-0 : version
* Bits 7-4 : header_size
* Bits 31-8 : packet_size
*/
#define GPR_PKT_INIT_PORT_V ( ( uint32_t ) 0 )
#define GPR_PKT_INIT_RESERVED_V ( ( uint16_t ) 0 )
#define GPR_PKT_INIT_DOMAIN_ID_V ( ( uint8_t ) 0 )
#define GPR_IDS_DOMAIN_ID_MODEM_V ( 1 ) /**< Modem domain. */
#define GPR_IDS_DOMAIN_ID_ADSP_V ( 2 ) /**< aDSP domain. */
#define GPR_IDS_DOMAIN_ID_APPS_V ( 3 ) /**< Application domain. */
/* V2.0 header size in number of 32-bit words. */
#define GPR_PKT_HEADER_WORD_SIZE_V ( ( sizeof( struct gpr_pkt ) + 3 ) >> 2 )
/* V2.0 header size in number of bytes. */
#define GPR_PKT_HEADER_BYTE_SIZE_V ( GPR_PKT_HEADER_WORD_SIZE_V << 2 )
/* Undefined value for where a valid GUID is expected. */
#define GPR_UNDEFINED_ID_V ( ( uint32_t ) 0xFFFFFFFF )
#define GPR_PKT_INIT_CLIENT_DATA_V ( ( uint8_t ) 0 )
/***********************************************************/
/** GPRv2 Packet Bitfield Macros ***/
/***********************************************************/
/* Bitmask and bit shift of the version field. */
#define GPR_PKT_VERSION_MASK ( 0x0000000F )
#define GPR_PKT_VERSION_SHFT ( 0 )
/* Bitmask and bit shift of the header size field. */
#define GPR_PKT_HEADER_SIZE_MASK ( 0x000000F0 )
#define GPR_PKT_HEADER_SIZE_SHFT ( 4 )
/* Bitmask and bit shift of the reserved field.
* Includes 4 reserved bits from client data field */
#define GPR_PKT_RESERVED_MASK ( 0xFFF00000 )
#define GPR_PKT_RESERVED_SHFT ( 20 )
/* Bitmask and bit shift of the packet size field. */
#define GPR_PKT_PACKET_SIZE_MASK ( 0xFFFFFF00 )
#define GPR_PKT_PACKET_SIZE_SHFT ( 8 )
/**********************************************************************/
/** Packet Helper Macros ***/
/**********************************************************************/
/* Gets the value of a field, including the specified mask and shift. */
#define GPR_GET_BITMASK( mask, shift, value ) \
( ( ( value ) & ( mask ) ) >> ( shift ) )
/* Sets a value in a field with a specified mask and shift. */
#define GPR_SET_BITMASK( mask, shift, value ) \
( ( ( value ) << ( shift ) ) & ( mask ) )
/* Gets the value of a field. */
#define GPR_GET_FIELD( field, value ) \
GPR_GET_BITMASK( ( field##_MASK ), ( field##_SHFT ), ( value ) )
/* Sets a value in a field. */
#define GPR_SET_FIELD( field, value ) \
GPR_SET_BITMASK( ( field##_MASK ), ( field##_SHFT ), ( value ) )
/* Returns an 8-bit aligned pointer to a base address pointer plus an
offset, in bytes.*/
#define GPR_PTR_END_OF( base_ptr, offset ) \
( ( ( uint8_t* ) base_ptr ) + ( offset ) )
/** Given the packet header, returns the packet's current size in bytes.
The current packet byte size is the sum of the base packet structure and
the used portion of the payload.
*/
#define GPR_PKT_GET_PACKET_BYTE_SIZE( header ) \
( GPR_GET_FIELD( GPR_PKT_PACKET_SIZE, header ) )
/* Given the packet header, returns the header's current size in bytes. */
#define GPR_PKT_GET_HEADER_BYTE_SIZE( header ) \
( GPR_GET_FIELD( GPR_PKT_HEADER_SIZE, header ) << 2 )
/** Given the packet header, returns the payload's current size in bytes.
The current payload byte size is the difference between the packet size and
the header size.
*/
#define GPR_PKT_GET_PAYLOAD_BYTE_SIZE( header ) \
( GPR_PKT_GET_PACKET_BYTE_SIZE( header ) - \
GPR_PKT_GET_HEADER_BYTE_SIZE( header ) )
/** Given the packet, returns a pointer to the beginning of the packet's
payload. */
#define GPR_PKT_GET_PAYLOAD( type, packet_ptr ) \
( ( type* ) GPR_PTR_END_OF( packet_ptr, \
GPR_PKT_GET_HEADER_BYTE_SIZE( \
( ( struct gpr_hdr* ) packet_ptr )->header ) ) )
#define GPR_HDR_FIELD(msg_type, hdr_len, ver)\
(((msg_type & 0x3) << 8) | ((hdr_len & 0xF) << 4) | (ver & 0xF))
#define GPR_HDR_SIZE sizeof(struct gpr_hdr)
#define GPR_SEQ_CMD_HDR_FIELD GPR_HDR_FIELD(GPR_MSG_TYPE_SEQ_CMD, \
GPR_HDR_LEN(GPR_HDR_SIZE), \
GPR_PKT_VER)
/**********************************************************************/
/** SPF GUID definitions ***/
/**********************************************************************/
/* An empty macro to mark non-GUIDs so that GUID script doesn't mistake
the ID for a GUID */
#define MM_NON_GUID(x) x
/* GUID owner is QTI. */
#define MM_GUID_OWNER_QTI 0x0
/* GUID owner is not-QTI. */
#define MM_GUID_OWNER_NON_QTI 0x1
/* Mask and Shift for Owner */
#define MM_GUID_OWNER_MASK MM_NON_GUID(0xF0000000)
#define MM_GUID_OWNER_SHIFT 28
/************************************************/
/* GUID types ***/
/************************************************/
/* Reserved */
#define MM_GUID_TYPE_RESERVED 0x0
/* Control commands */
#define MM_GUID_TYPE_CONTROL_CMD 0x1
/* Responses of control commands */
#define MM_GUID_TYPE_CONTROL_CMD_RSP 0x2
/* Control events */
#define MM_GUID_TYPE_CONTROL_EVENT 0x3
/* Data commands */
#define MM_GUID_TYPE_DATA_CMD 0x4
/* Data command responses */
#define MM_GUID_TYPE_DATA_CMD_RSP 0x5
/* Data events */
#define MM_GUID_TYPE_DATA_EVENT 0x6
/* Module-id */
#define MM_GUID_TYPE_MODULE_ID 0x7
/* Module's param & event-id */
#define MM_GUID_TYPE_PARAM_EVENT_ID 0x8
/* Media format-id. */
#define MM_GUID_TYPE_FORMAT_ID 0x9
/* CAPI */
#define MM_GUID_TYPE_CAPI 0xA
/* MAX */
#define MM_GUID_TYPE_MAX 0xB
/** Rest are reserved */
/* Zero is an invalid ID.
* To be used like NULL value for pointers */
#define MM_GUID_INVALID 0
/* Mask and shift for GUID type */
#define MM_GUID_TYPE_MASK MM_NON_GUID(0x0F000000)
#define MM_GUID_TYPE_SHIFT 24
struct gpr_hdr {
uint32_t header;
uint8_t dst_domain_id;
uint8_t src_domain_id;
uint8_t client_data;
uint8_t reserved;
uint32_t src_port;
uint32_t dst_port;
uint32_t token;
uint32_t opcode;
} __packed;
struct gpr_pkt {
struct gpr_hdr hdr;
DECLARE_FLEX_ARRAY(uint8_t, payload);
};
#define GPR_IBASIC_RSP_RESULT 0x02001005
/* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */
#define GPR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF)
#define GPR_SVC_MINOR_VERSION(v) (v & 0xFF)
struct gpr_device {
struct device dev;
uint16_t svc_id;
uint16_t domain_id;
uint32_t version;
char name[GPR_NAME_SIZE];
spinlock_t lock;
struct list_head node;
};
#define to_gpr_device(d) container_of(d, struct gpr_device, dev)
struct gpr_driver {
int (*probe)(struct gpr_device *sl);
int (*remove)(struct gpr_device *sl);
int (*callback)(struct gpr_device *a,
void *d);
struct device_driver driver;
const struct gpr_device_id *id_table;
};
#define to_gpr_driver(d) container_of(d, struct gpr_driver, driver)
/*
* use a macro to avoid include chaining to get THIS_MODULE
*/
#define gpr_driver_register(drv) __gpr_driver_register(drv, THIS_MODULE)
int __gpr_driver_register(struct gpr_driver *drv, struct module *owner);
void gpr_driver_unregister(struct gpr_driver *drv);
/**
* module_gpr_driver() - Helper macro for registering a gprbus driver
* @__gprbus_driver: gprbus_driver struct
*
* Helper macro for gprbus drivers which do not do anything special in
* module init/exit. This eliminates a lot of boilerplate. Each module
* may only use this macro once, and calling it replaces module_init()
* and module_exit()
*/
#define module_gpr_driver(__gpr_driver) \
module_driver(__gpr_driver, gpr_driver_register, \
gpr_driver_unregister)
int gpr_send_pkt(struct gpr_device *adev, struct gpr_pkt *pkt);
enum gpr_subsys_state gpr_get_modem_state(void);
enum gpr_subsys_state gpr_get_q6_state(void);
#endif /* __QCOM_GPR_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
#ifndef AUDIO_MOD_DEVICETABLE_H
#define AUDIO_MOD_DEVICETABLE_H
#include <linux/mod_devicetable.h>
/* soundwire */
#define SOUNDWIRE_NAME_SIZE 32
#define SOUNDWIRE_MODULE_PREFIX "swr:"
struct swr_device_id {
char name[SOUNDWIRE_NAME_SIZE];
kernel_ulong_t driver_data; /* Data private to the driver */
};
/* gpr */
#define GPR_NAME_SIZE 32
#define GPR_MODULE_PREFIX "gpr:"
struct gpr_device_id {
char name[GPR_NAME_SIZE];
__u32 domain_id;
__u32 svc_id;
__u32 svc_version;
kernel_ulong_t driver_data; /* Data private to the driver */
};
#endif /* AUDIO_MOD_DEVICETABLE_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#ifndef _SND_EVENT_H_
#define _SND_EVENT_H_
enum {
SND_EVENT_DOWN = 0,
SND_EVENT_UP,
};
struct snd_event_clients;
struct snd_event_ops {
int (*enable)(struct device *dev, void *data);
void (*disable)(struct device *dev, void *data);
};
#ifdef CONFIG_SND_EVENT
int snd_event_client_register(struct device *dev,
const struct snd_event_ops *snd_ev_ops,
void *data);
int snd_event_client_deregister(struct device *dev);
int snd_event_master_register(struct device *dev,
const struct snd_event_ops *ops,
struct snd_event_clients *clients,
void *data);
int snd_event_master_deregister(struct device *dev);
int snd_event_notify(struct device *dev, unsigned int state);
void snd_event_mstr_add_client(struct snd_event_clients **snd_clients,
int (*compare)(struct device *, void *),
void *data);
static inline bool is_snd_event_fwk_enabled(void)
{
return 1;
}
#else
static inline int snd_event_client_register(struct device *dev,
const struct snd_event_ops *snd_ev_ops,
void *data)
{
return 0;
}
static inline int snd_event_client_deregister(struct device *dev)
{
return 0;
}
static inline int snd_event_master_register(struct device *dev,
const struct snd_event_ops *ops,
struct snd_event_clients *clients,
void *data)
{
return 0;
}
static inline int snd_event_master_deregister(struct device *dev)
{
return 0;
}
static inline int snd_event_notify(struct device *dev, unsigned int state)
{
return 0;
}
static inline void snd_event_mstr_add_client(struct snd_event_clients **snd_clients,
int (*compare)(struct device *, void *),
void *data)
{
return;
}
static inline bool is_snd_event_fwk_enabled(void)
{
return 0;
}
#endif /* CONFIG_SND_EVENT */
#endif /* _SND_EVENT_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _LINUX_SOUNDWIRE_H
#define _LINUX_SOUNDWIRE_H
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#include "audio_mod_devicetable.h"
enum {
SWR_UC0 = 0,
SWR_UC1,
SWR_UC2,
SWR_UC3,
SWR_UC_MAX,
};
#define SWR_CLK_RATE_24KHZ 24000
#define SWR_CLK_RATE_48KHZ 48000
#define SWR_CLK_RATE_0P3MHZ 300000
#define SWR_CLK_RATE_0P6MHZ 600000
#define SWR_CLK_RATE_1P2MHZ 1200000
#define SWR_CLK_RATE_2P4MHZ 2400000
#define SWR_CLK_RATE_4P8MHZ 4800000
#define SWR_CLK_RATE_9P6MHZ 9600000
#define SWR_CLK_RATE_11P2896MHZ 11289600
#define SWR_CLK_RATE_12P288MHZ 12288000
extern struct bus_type soundwire_type;
struct swr_device;
/* Soundwire supports max. of 8 channels per port */
#define SWR_MAX_CHANNEL_NUM 8
/* Soundwire supports max. of 14 ports on each device */
#define SWR_MAX_DEV_PORT_NUM 14
/* Maximum number of slave devices that a master can control */
#define SWR_MAX_DEV_NUM 11
/* Maximum number of ports on master so that it can accommodate all the port
* configurations of all devices
*/
#define SWR_MAX_MSTR_PORT_NUM (SWR_MAX_DEV_NUM * SWR_MAX_DEV_PORT_NUM)
/* SWR slave port params count */
#define SWR_PORT_PARAMS 2
/* Regmap support for soundwire interface */
struct regmap *__devm_regmap_init_swr(struct swr_device *dev,
const struct regmap_config *config,
struct lock_class_key *lock_key,
const char *lock_name);
/**
* regmap_init_swr(): Initialise register map
*
* @swr: Device that will be interacted with
* @config: Configuration for register map
*
* The return value will be an ERR_PTR() on error or a valid pointer to
* a struct regmap.
*/
#define regmap_init_swr(swr, config) \
__regmap_lockdep_wrapper(__regmap_init_swr, #config, \
swr, config)
/**
* devm_regmap_init_swr(): Initialise managed register map
*
* @swr: Device that will be interacted with
* @config: Configuration for register map
*
* The return value will be an ERR_PTR() on error or a valid pointer
* to a struct regmap. The regmap will be automatically freed by the
* device management code.
*/
#define devm_regmap_init_swr(swr, config) \
__regmap_lockdep_wrapper(__devm_regmap_init_swr, #config, \
swr, config)
/* Indicates soundwire devices group information */
enum {
SWR_GROUP_NONE = 0,
SWR_GROUP_12 = 12,
SWR_GROUP_13 = 13,
SWR_BROADCAST = 15,
};
/*
* struct swr_port_info - represents new soundwire frame shape
* with full data ports
* @list: link with other soundwire port info nodes
* @dev_num: logical device number of the soundwire slave device
* @port_en: flag indicates whether the port is enabled
* @slave_port_id: logical port number of the soundwire slave device
* @offset1: sample offset indicating the offset of the channel
* from the start of the frame
* @offset2: channel offset indicating offset between to channels
* @hstart: start offset for subframe window.
* @hstop: start offset for subframe window.
* @master_port_id: logical port number of corresponding soundwire master device
* @blk_grp_count: grouping count for n.o of channels.
* @blk_pack_mode: packing mode for channels in each port.
* @sinterval: sample interval indicates spacing from one sample
* event to the next
* @ch_en: channels enabled in a port.
* @req_ch: channels requested to be enabled in a port.
* @num_ch: number of channels enabled in a port
* @ch_rate: sampling rate of the channel with which data will be
* transferred
*
* Soundwire frame shape is created based on swr_port_info struct
* parameters.
*/
struct swr_port_info {
u8 dev_num;
u8 port_en;
u8 slave_port_id;
u8 offset1;
u8 offset2;
u16 sinterval;
struct list_head list;
u8 master_port_id;
u8 hstart;
u8 hstop;
u8 blk_grp_count;
u8 blk_pack_mode;
u8 word_length;
u8 lane_ctrl;
u8 ch_en;
u8 req_ch;
u8 num_ch;
u32 ch_rate;
u32 req_ch_rate;
};
struct swr_port_params {
u32 offset1;
u32 lane_ctrl;
};
struct swr_dev_frame_config {
struct swr_port_params *pp;
};
/*
* struct swr_params - represent transfer of data from soundwire slave
* to soundwire master
* @tid: transaction ID to track each transaction
* @dev_num: logical device number of the soundwire slave device
* @num_port: number of ports that needs to be configured
* @port_id: array of logical port numbers of the soundwire slave device
* @num_ch: array of number of channels enabled
* @ch_rate: array of sampling rate of different channels that need to
* be configured
* @ch_en: array of channels mask for all the ports
* @port_type: the required master port type
*/
struct swr_params {
u8 tid;
u8 dev_num;
u8 num_port;
u8 port_id[SWR_MAX_DEV_PORT_NUM];
u8 num_ch[SWR_MAX_DEV_PORT_NUM];
u32 ch_rate[SWR_MAX_DEV_PORT_NUM];
u8 ch_en[SWR_MAX_DEV_PORT_NUM];
u8 port_type[SWR_MAX_DEV_PORT_NUM];
};
/*
* struct swr_reg - struct to handle soundwire slave register read/writes
* @tid: transaction id for reg read/writes
* @dev_id: logical device number of the soundwire slave device
* @regaddr: 16 bit regaddr of soundwire slave
* @buf: value to be written/read to/from regaddr
* @len: length of the buffer buf
*/
struct swr_reg {
u8 tid;
u8 dev_id;
u32 regaddr;
u32 *buf;
u32 len;
};
/*
* struct swr_master - Interface to the soundwire master controller
* @dev: device interface to this driver
* @list: link with other soundwire master controllers
* @bus_num: board/SoC specific identifier for a soundwire master
* @mlock: mutex protecting master data structures
* @devices: list of devices on this master
* @port: logical port numbers of the soundwire master. This array
* can hold maximum master ports which is equal to number of slave
* devices multiplied by number of ports in each slave device
* @port_txn: table of port config transactions with transaction id
* @reg_txn: table of register transactions with transaction id
* @last_tid: size of table port_txn (can't grow beyond 256 since
* tid is 8 bits)
* @num_port: number of active ports on soundwire master
* @gr_sid: slave id used by the group for write operations
* @connect_port: callback for configuration of soundwire port(s)
* @disconnect_port: callback for disable of soundwire port(s)
* @read: callback for soundwire slave register read
* @write: callback for soundwire slave register write
* @get_logical_dev_num: callback to get soundwire slave logical
* device number
* @port_en_mask: bit mask of active ports on soundwire master
*/
struct swr_master {
struct device dev;
struct list_head list;
unsigned int bus_num;
struct mutex mlock;
struct list_head devices;
struct swr_port_info port[SWR_MAX_MSTR_PORT_NUM];
struct swr_params **port_txn;
struct swr_reg **reg_txn;
u8 last_tid;
u8 num_port;
u8 num_dev;
u8 gr_sid;
int (*connect_port)(struct swr_master *mstr, struct swr_params *txn);
int (*disconnect_port)(struct swr_master *mstr, struct swr_params *txn);
int (*read)(struct swr_master *mstr, u8 dev_num, u16 reg_addr,
void *buf, u32 len);
int (*write)(struct swr_master *mstr, u8 dev_num, u16 reg_addr,
const void *buf);
int (*bulk_write)(struct swr_master *master, u8 dev_num, void *reg,
const void *buf, size_t len);
int (*get_logical_dev_num)(struct swr_master *mstr, u64 dev_id,
u8 *dev_num);
int (*init_port_params)(struct swr_master *mstr, u32 dev_num,
u32 num_ports, struct swr_dev_frame_config *uc_arr);
int (*slvdev_datapath_control)(struct swr_master *mstr, bool enable);
bool (*remove_from_group)(struct swr_master *mstr);
void (*device_wakeup_vote)(struct swr_master *mstr);
void (*device_wakeup_unvote)(struct swr_master *mstr);
u16 port_en_mask;
};
static inline struct swr_master *to_swr_master(struct device *dev)
{
return dev ? container_of(dev, struct swr_master, dev) : NULL;
}
/*
* struct swr_device - represent a soundwire slave device
* @name: indicates the name of the device, defined in devicetree
* binding under soundwire slave device node as a compatible field.
* @master: soundwire master managing the bus hosting this device
* @driver: Device's driver. Pointer to access routines
* @dev_list: list of devices on a controller
* @dev_num: logical device number of the soundwire slave device
* @dev: driver model representation of the device
* @addr: represents "ea-addr" which is unique-id of soundwire slave
* device
* @group_id: group id supported by the slave device
* @slave_irq: irq handle of slave to be invoked by master
* during slave interrupt
*/
struct swr_device {
char name[SOUNDWIRE_NAME_SIZE];
struct swr_master *master;
struct swr_driver *driver;
struct list_head dev_list;
u8 dev_num;
struct device dev;
u64 addr;
u8 group_id;
bool paging_support;
struct irq_domain *slave_irq;
bool slave_irq_pending;
bool clk_scale_initialized;
u8 g_scp1_val; /* used for v1.2 or class devices */
u8 g_scp2_val; /* used for v1.2 or class devices */
};
static inline struct swr_device *to_swr_device(struct device *dev)
{
return dev ? container_of(dev, struct swr_device, dev) : NULL;
}
/*
* struct swr_driver - Manage soundwire slave device driver
* @probe: binds this driver to soundwire device
* @remove: unbinds this driver from soundwire device
* @shutdown: standard shutdown callback used during power down/halt
* @suspend: standard suspend callback used during system suspend
* @resume: standard resume callback used during system resume
* @driver: soundwire device drivers should initialize name and
* owner field of this structure
* @id_table: list of soundwire devices supported by this driver
*/
struct swr_driver {
int (*probe)(struct swr_device *swr);
int (*remove)(struct swr_device *swr);
void (*shutdown)(struct swr_device *swr);
int (*suspend)(struct swr_device *swr, pm_message_t pmesg);
int (*resume)(struct swr_device *swr);
int (*device_up)(struct swr_device *swr);
int (*device_down)(struct swr_device *swr);
int (*reset_device)(struct swr_device *swr);
struct device_driver driver;
const struct swr_device_id *id_table;
};
static inline struct swr_driver *to_swr_driver(struct device_driver *drv)
{
return drv ? container_of(drv, struct swr_driver, driver) : NULL;
}
/*
* struct swr_boardinfo - Declare board info for soundwire device bringup
* @name: name to initialize swr_device.name
* @bus_num: identifies which soundwire master parents the soundwire
* slave_device
* @addr: represents "ea-addr" of soundwire slave device
* @of_node: pointer to OpenFirmware device node
* @swr_slave: device to be registered with soundwire
*/
struct swr_boardinfo {
char name[SOUNDWIRE_NAME_SIZE];
int bus_num;
u64 addr;
struct device_node *of_node;
struct swr_device *swr_slave;
};
static inline void *swr_get_ctrl_data(const struct swr_master *master)
{
return master ? dev_get_drvdata(&master->dev) : NULL;
}
static inline void swr_set_ctrl_data(struct swr_master *master, void *data)
{
dev_set_drvdata(&master->dev, data);
}
static inline void *swr_get_dev_data(const struct swr_device *dev)
{
return dev ? dev_get_drvdata(&dev->dev) : NULL;
}
static inline void swr_set_dev_data(struct swr_device *dev, void *data)
{
dev_set_drvdata(&dev->dev, data);
}
extern int swr_startup_devices(struct swr_device *swr_dev);
extern struct swr_device *swr_new_device(struct swr_master *master,
struct swr_boardinfo const *info);
extern int of_register_swr_devices(struct swr_master *master);
extern void swr_port_response(struct swr_master *mstr, u8 tid);
extern int swr_get_logical_dev_num(struct swr_device *dev, u64 dev_id,
u8 *dev_num);
extern int swr_init_port_params(struct swr_device *dev,
u32 num_ports, struct swr_dev_frame_config *pp);
extern int swr_read(struct swr_device *dev, u8 dev_num, u16 reg_addr,
void *buf, u32 len);
extern int swr_write(struct swr_device *dev, u8 dev_num, u16 reg_addr,
const void *buf);
extern int swr_bulk_write(struct swr_device *dev, u8 dev_num, void *reg_addr,
const void *buf, size_t len);
extern int swr_connect_port(struct swr_device *dev, u8 *port_id, u8 num_port,
u8 *ch_mask, u32 *ch_rate, u8 *num_ch,
u8 *port_type);
extern int swr_disconnect_port(struct swr_device *dev,
u8 *port_id, u8 num_port, u8 *ch_mask,
u8 *port_type);
extern int swr_set_device_group(struct swr_device *swr_dev, u8 id);
extern int swr_driver_register(struct swr_driver *drv);
extern void swr_driver_unregister(struct swr_driver *drv);
extern int swr_add_device(struct swr_master *master,
struct swr_device *swrdev);
extern void swr_remove_device(struct swr_device *swr);
extern void swr_master_add_boarddevices(struct swr_master *master);
extern void swr_unregister_master(struct swr_master *master);
extern int swr_register_master(struct swr_master *master);
extern int swr_device_up(struct swr_device *swr_dev);
extern int swr_device_down(struct swr_device *swr_dev);
extern int swr_reset_device(struct swr_device *swr_dev);
extern int swr_slvdev_datapath_control(struct swr_device *swr_dev, u8 dev_num,
bool enable);
extern int swr_remove_from_group(struct swr_device *dev, u8 dev_num);
extern void swr_remove_device(struct swr_device *swr_dev);
extern struct swr_device *get_matching_swr_slave_device(struct device_node *np);
extern int swr_device_wakeup_vote(struct swr_device *dev);
extern int swr_device_wakeup_unvote(struct swr_device *dev);
#endif /* _LINUX_SOUNDWIRE_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015, 2017-2021 The Linux Foundation. All rights reserved.
*/
#ifndef _LINUX_SWR_COMMON_H
#define _LINUX_SWR_COMMON_H
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/bitops.h>
struct port_params {
u16 si;
u8 off1;
u8 off2;
u8 hstart;/* head start */
u8 hstop; /* head stop */
u8 wd_len;/* word length */
u8 bp_mode; /* block pack mode */
u8 bgp_ctrl;/* block group control */
u8 lane_ctrl;/* lane to be used */
u8 dir; /* master port dir: OUT = 0 IN = 1 */
u8 stream_type; /* PDM = 0, PCM = 1 */
};
struct swrm_port_config {
u32 size;
u32 uc;
void *params;
};
struct swr_mstr_port_map {
u32 id;
u32 uc;
struct port_params *swr_port_params;
};
#define SWR_MSTR_PORT_LEN 13 /* Number of master ports */
#endif /* _LINUX_SWR_COMMON_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015, 2017-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _LINUX_SWR_WCD_H
#define _LINUX_SWR_WCD_H
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/bitops.h>
enum {
SWR_CH_MAP,
SWR_DEVICE_DOWN,
SWR_DEVICE_UP,
SWR_SUBSYS_RESTART,
SWR_SET_NUM_RX_CH,
SWR_CLK_FREQ,
SWR_DEVICE_SSR_DOWN,
SWR_DEVICE_SSR_UP,
SWR_REGISTER_WAKE_IRQ,
SWR_SET_PORT_MAP,
SWR_REQ_CLK_SWITCH,
SWR_REGISTER_WAKEUP,
SWR_DEREGISTER_WAKEUP,
};
struct swr_mstr_port {
int num_port;
u8 *port;
};
#define MCLK_FREQ 9600000
#define MCLK_FREQ_LP 600000
#define MCLK_FREQ_NATIVE 11289600
#define MCLK_FREQ_12288 12288000
#if (IS_ENABLED(CONFIG_SOUNDWIRE_WCD_CTRL) || \
IS_ENABLED(CONFIG_SOUNDWIRE_MSTR_CTRL))
extern int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data);
#else /* CONFIG_SOUNDWIRE_WCD_CTRL */
static inline int swrm_wcd_notify(struct platform_device *pdev, u32 id,
void *data)
{
return 0;
}
#endif /* CONFIG_SOUNDWIRE_WCD_CTRL */
#endif /* _LINUX_SWR_WCD_H */

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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __WCD_SPI_AC_H__
#define __WCD_SPI_AC_H__
#include <linux/types.h>
#include <linux/bitops.h>
enum wcd_spi_acc_req {
WCD_SPI_ACCESS_REQUEST,
WCD_SPI_ACCESS_RELEASE,
WCD_SPI_ACCESS_MAX,
};
#define WCD_SPI_AC_DATA_TRANSFER BIT(0)
#define WCD_SPI_AC_CONCURRENCY BIT(1)
#define WCD_SPI_AC_REMOTE_DOWN BIT(2)
#define WCD_SPI_AC_SVC_OFFLINE BIT(3)
#define WCD_SPI_AC_UNINITIALIZED BIT(4)
#if IS_ENABLED(CONFIG_WCD_SPI_AC)
int wcd_spi_access_ctl(struct device *dev,
enum wcd_spi_acc_req req,
u32 reason);
#else
int wcd_spi_access_ctl(struct device *dev,
enum wcd_spi_acc_req req,
u32 reason)
{
return 0;
}
#endif /* end of CONFIG_WCD_SPI_AC */
#endif /* end of __WCD_SPI_AC_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
*
* Copyright (C) 2008 Google, Inc.
* Copyright (c) 2012, 2014, 2017, 2020, 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _UAPI_LINUX_MSM_AUDIO_H
#define _UAPI_LINUX_MSM_AUDIO_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define AUDIO_IOCTL_MAGIC 'a'
#define IOCTL_MAP_PHYS_ADDR _IOW(AUDIO_IOCTL_MAGIC, 97, int)
#define IOCTL_UNMAP_PHYS_ADDR _IOW(AUDIO_IOCTL_MAGIC, 98, int)
#define IOCTL_MAP_HYP_ASSIGN _IOW(AUDIO_IOCTL_MAGIC, 109, int)
#define IOCTL_UNMAP_HYP_ASSIGN _IOW(AUDIO_IOCTL_MAGIC, 110, int)
#define IOCTL_MAP_HYP_ASSIGN_V2 _IOW(AUDIO_IOCTL_MAGIC, 111, struct msm_mdf_data)
#define IOCTL_UNMAP_HYP_ASSIGN_V2 _IOW(AUDIO_IOCTL_MAGIC, 112, struct msm_mdf_data)
#define AUDIO_MAX_COMMON_IOCTL_NUM 113
/* ss_masks is generated from sys_ids
* for id in sys_ids
* ss_masks |= 1 << (id - 1)
*/
struct msm_mdf_data {
__u64 ss_masks;
__u32 mem_fd;
__u32 reserved;
};
#endif

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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */
#ifndef _UAPI_MSM_AUDIO_CALIBRATION_H
#define _UAPI_MSM_AUDIO_CALIBRATION_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define CAL_IOCTL_MAGIC 'a'
#define AUDIO_ALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
200, void *)
#define AUDIO_DEALLOCATE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
201, void *)
#define AUDIO_PREPARE_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
202, void *)
#define AUDIO_SET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
203, void *)
#define AUDIO_GET_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
204, void *)
#define AUDIO_POST_CALIBRATION _IOWR(CAL_IOCTL_MAGIC, \
205, void *)
/* For Real-Time Audio Calibration */
#define AUDIO_GET_RTAC_ADM_INFO _IOR(CAL_IOCTL_MAGIC, \
207, void *)
#define AUDIO_GET_RTAC_VOICE_INFO _IOR(CAL_IOCTL_MAGIC, \
208, void *)
#define AUDIO_GET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \
209, void *)
#define AUDIO_SET_RTAC_ADM_CAL _IOWR(CAL_IOCTL_MAGIC, \
210, void *)
#define AUDIO_GET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \
211, void *)
#define AUDIO_SET_RTAC_ASM_CAL _IOWR(CAL_IOCTL_MAGIC, \
212, void *)
#define AUDIO_GET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \
213, void *)
#define AUDIO_SET_RTAC_CVS_CAL _IOWR(CAL_IOCTL_MAGIC, \
214, void *)
#define AUDIO_GET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \
215, void *)
#define AUDIO_SET_RTAC_CVP_CAL _IOWR(CAL_IOCTL_MAGIC, \
216, void *)
#define AUDIO_GET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \
217, void *)
#define AUDIO_SET_RTAC_AFE_CAL _IOWR(CAL_IOCTL_MAGIC, \
218, void *)
enum {
CVP_VOC_RX_TOPOLOGY_CAL_TYPE = 0,
CVP_VOC_TX_TOPOLOGY_CAL_TYPE,
CVP_VOCPROC_STATIC_CAL_TYPE,
CVP_VOCPROC_DYNAMIC_CAL_TYPE,
CVS_VOCSTRM_STATIC_CAL_TYPE,
CVP_VOCDEV_CFG_CAL_TYPE,
CVP_VOCPROC_STATIC_COL_CAL_TYPE,
CVP_VOCPROC_DYNAMIC_COL_CAL_TYPE,
CVS_VOCSTRM_STATIC_COL_CAL_TYPE,
ADM_TOPOLOGY_CAL_TYPE,
ADM_CUST_TOPOLOGY_CAL_TYPE,
ADM_AUDPROC_CAL_TYPE,
ADM_AUDVOL_CAL_TYPE,
ASM_TOPOLOGY_CAL_TYPE,
ASM_CUST_TOPOLOGY_CAL_TYPE,
ASM_AUDSTRM_CAL_TYPE,
AFE_COMMON_RX_CAL_TYPE,
AFE_COMMON_TX_CAL_TYPE,
AFE_ANC_CAL_TYPE,
AFE_AANC_CAL_TYPE,
AFE_FB_SPKR_PROT_CAL_TYPE,
AFE_HW_DELAY_CAL_TYPE,
AFE_SIDETONE_CAL_TYPE,
AFE_TOPOLOGY_CAL_TYPE,
AFE_CUST_TOPOLOGY_CAL_TYPE,
LSM_CUST_TOPOLOGY_CAL_TYPE,
LSM_TOPOLOGY_CAL_TYPE,
LSM_CAL_TYPE,
ADM_RTAC_INFO_CAL_TYPE,
VOICE_RTAC_INFO_CAL_TYPE,
ADM_RTAC_APR_CAL_TYPE,
ASM_RTAC_APR_CAL_TYPE,
VOICE_RTAC_APR_CAL_TYPE,
MAD_CAL_TYPE,
ULP_AFE_CAL_TYPE,
ULP_LSM_CAL_TYPE,
DTS_EAGLE_CAL_TYPE,
AUDIO_CORE_METAINFO_CAL_TYPE,
SRS_TRUMEDIA_CAL_TYPE,
CORE_CUSTOM_TOPOLOGIES_CAL_TYPE,
ADM_RTAC_AUDVOL_CAL_TYPE,
ULP_LSM_TOPOLOGY_ID_CAL_TYPE,
AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE,
AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE,
AFE_SIDETONE_IIR_CAL_TYPE,
AFE_LSM_TOPOLOGY_CAL_TYPE,
AFE_LSM_TX_CAL_TYPE,
ADM_LSM_TOPOLOGY_CAL_TYPE,
ADM_LSM_AUDPROC_CAL_TYPE,
ADM_LSM_AUDPROC_PERSISTENT_CAL_TYPE,
ADM_AUDPROC_PERSISTENT_CAL_TYPE,
AFE_FB_SPKR_PROT_V4_EX_VI_CAL_TYPE,
MAX_CAL_TYPES,
};
#define AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE AFE_FB_SPKR_PROT_TH_VI_CAL_TYPE
#define AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE AFE_FB_SPKR_PROT_EX_VI_CAL_TYPE
#define AFE_FB_SPKR_PROT_V4_EX_VI_CAL_TYPE AFE_FB_SPKR_PROT_V4_EX_VI_CAL_TYPE
#define AFE_SIDETONE_IIR_CAL_TYPE AFE_SIDETONE_IIR_CAL_TYPE
#define AFE_LSM_TOPOLOGY_CAL_TYPE AFE_LSM_TOPOLOGY_CAL_TYPE
#define AFE_LSM_TX_CAL_TYPE AFE_LSM_TX_CAL_TYPE
#define ADM_LSM_TOPOLOGY_CAL_TYPE ADM_LSM_TOPOLOGY_CAL_TYPE
#define ADM_LSM_AUDPROC_CAL_TYPE ADM_LSM_AUDPROC_CAL_TYPE
#define ADM_LSM_AUDPROC_PERSISTENT_CAL_TYPE ADM_LSM_AUDPROC_PERSISTENT_CAL_TYPE
#define ADM_AUDPROC_PERSISTENT_CAL_TYPE ADM_AUDPROC_PERSISTENT_CAL_TYPE
#define LSM_CAL_TYPES
#define TOPOLOGY_SPECIFIC_CHANNEL_INFO
#define MSM_SPKR_PROT_SPV3
#define MSM_SPKR_PROT_SPV4
#define MSM_CMA_MEM_ALLOC
enum {
VERSION_0_0,
};
enum {
PER_VOCODER_CAL_BIT_MASK = 0x10000,
};
#define MAX_IOCTL_CMD_SIZE 512
/* common structures */
struct audio_cal_header {
__s32 data_size;
__s32 version;
__s32 cal_type;
__s32 cal_type_size;
};
struct audio_cal_type_header {
__s32 version;
__s32 buffer_number;
};
struct audio_cal_data {
/* Size of cal data at mem_handle allocation or at vaddr */
__s32 cal_size;
/* If mem_handle if shared memory is used*/
__s32 mem_handle;
#ifdef MSM_CMA_MEM_ALLOC
/* cma allocation flag if cma heap memory is used */
__u32 cma_mem;
#endif
};
/* AUDIO_ALLOCATE_CALIBRATION */
struct audio_cal_type_alloc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_alloc {
struct audio_cal_header hdr;
struct audio_cal_type_alloc cal_type;
};
/* AUDIO_DEALLOCATE_CALIBRATION */
struct audio_cal_type_dealloc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_dealloc {
struct audio_cal_header hdr;
struct audio_cal_type_dealloc cal_type;
};
/* AUDIO_PREPARE_CALIBRATION */
struct audio_cal_type_prepare {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_prepare {
struct audio_cal_header hdr;
struct audio_cal_type_prepare cal_type;
};
/* AUDIO_POST_CALIBRATION */
struct audio_cal_type_post {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_post {
struct audio_cal_header hdr;
struct audio_cal_type_post cal_type;
};
/*AUDIO_CORE_META_INFO */
struct audio_cal_info_metainfo {
__u32 nKey;
};
/* Cal info types */
enum {
RX_DEVICE,
TX_DEVICE,
MAX_PATH_TYPE
};
struct audio_cal_info_adm_top {
__s32 topology;
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 app_type;
__s32 sample_rate;
};
struct audio_cal_info_audproc {
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 app_type;
__s32 sample_rate;
};
struct audio_cal_info_audvol {
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 app_type;
__s32 vol_index;
};
struct audio_cal_info_afe {
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 sample_rate;
};
struct audio_cal_info_afe_top {
__s32 topology;
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 sample_rate;
};
struct audio_cal_info_asm_top {
__s32 topology;
__s32 app_type;
};
struct audio_cal_info_audstrm {
__s32 app_type;
};
struct audio_cal_info_aanc {
__s32 acdb_id;
};
#define MAX_HW_DELAY_ENTRIES 25
struct audio_cal_hw_delay_entry {
__u32 sample_rate;
__u32 delay_usec;
};
struct audio_cal_hw_delay_data {
__u32 num_entries;
struct audio_cal_hw_delay_entry entry[MAX_HW_DELAY_ENTRIES];
};
struct audio_cal_info_hw_delay {
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 property_type;
struct audio_cal_hw_delay_data data;
};
enum msm_spkr_prot_states {
MSM_SPKR_PROT_CALIBRATED,
MSM_SPKR_PROT_CALIBRATION_IN_PROGRESS,
MSM_SPKR_PROT_DISABLED,
MSM_SPKR_PROT_NOT_CALIBRATED,
MSM_SPKR_PROT_PRE_CALIBRATED,
MSM_SPKR_PROT_IN_FTM_MODE,
MSM_SPKR_PROT_IN_V_VALI_MODE
};
#define MSM_SPKR_PROT_IN_FTM_MODE MSM_SPKR_PROT_IN_FTM_MODE
#define MSM_SPKR_PROT_IN_V_VALI_MODE MSM_SPKR_PROT_IN_V_VALI_MODE
enum msm_spkr_count {
SP_V2_SPKR_1,
SP_V2_SPKR_2,
SP_V2_NUM_MAX_SPKRS
};
struct audio_cal_info_spk_prot_cfg {
__s32 r0[SP_V2_NUM_MAX_SPKRS];
__s32 t0[SP_V2_NUM_MAX_SPKRS];
__u32 quick_calib_flag;
__u32 mode;
/*
* 0 - Start spk prot
* 1 - Start calib
* 2 - Disable spk prot
*/
#ifdef MSM_SPKR_PROT_SPV3
__u32 sp_version;
__s32 limiter_th[SP_V2_NUM_MAX_SPKRS];
#endif
};
struct audio_cal_info_sp_th_vi_ftm_cfg {
/*
* mode should be first param, add new params later to this.
* we use this mode(first 4 bytes) to differentiate
* whether it is TH_VI FTM or v-validation.
*/
__u32 mode;
/*
* 0 - normal running mode
* 1 - Calibration
* 2 - FTM mode
*/
__u32 wait_time[SP_V2_NUM_MAX_SPKRS];
__u32 ftm_time[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_th_vi_v_vali_cfg {
/*
* mode should be first param, add new params later to this.
* we use this mode(first 4 bytes) to differentiate
* whether it is TH_VI FTM or v-validation.
*/
__u32 mode;
/*
* 0 - normal running mode
* 1 - Calibration
* 2 - FTM mode
* 3 - V-Validation mode
*/
__u32 wait_time[SP_V2_NUM_MAX_SPKRS];
__u32 vali_time[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_ex_vi_ftm_cfg {
__u32 wait_time[SP_V2_NUM_MAX_SPKRS];
__u32 ftm_time[SP_V2_NUM_MAX_SPKRS];
__u32 mode;
/*
* 0 - normal running mode
* 2 - FTM mode
*/
};
struct audio_cal_info_sp_ex_vi_param {
__s32 freq_q20[SP_V2_NUM_MAX_SPKRS];
__s32 resis_q24[SP_V2_NUM_MAX_SPKRS];
__s32 qmct_q24[SP_V2_NUM_MAX_SPKRS];
__s32 status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_v4_ex_vi_param {
__s32 ftm_re_q24[SP_V2_NUM_MAX_SPKRS];
__s32 ftm_Bl_q24[SP_V2_NUM_MAX_SPKRS];
__s32 ftm_Rms_q24[SP_V2_NUM_MAX_SPKRS];
__s32 ftm_Kms_q24[SP_V2_NUM_MAX_SPKRS];
__s32 ftm_freq_q20[SP_V2_NUM_MAX_SPKRS];
__s32 ftm_Qms_q24[SP_V2_NUM_MAX_SPKRS];
__u32 status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_th_vi_param {
/*
* mode should be first param, add new params later to this.
* we use this mode(first 4 bytes) to differentiate
* whether it is TH_VI FTM or v-validation.
*/
__u32 mode;
__s32 r_dc_q24[SP_V2_NUM_MAX_SPKRS];
__s32 temp_q22[SP_V2_NUM_MAX_SPKRS];
__s32 status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_sp_th_vi_v_vali_param {
/*
* mode should be first param, add new params later to this.
* we use this mode(first 4 bytes) to differentiate
* whether it is TH_VI FTM or v-validation.
*/
__u32 mode;
__u32 vrms_q24[SP_V2_NUM_MAX_SPKRS];
__s32 status[SP_V2_NUM_MAX_SPKRS];
};
struct audio_cal_info_msm_spk_prot_status {
__s32 r0[SP_V2_NUM_MAX_SPKRS];
__s32 status;
};
struct audio_cal_info_sidetone {
__u16 enable;
__u16 gain;
__s32 tx_acdb_id;
__s32 rx_acdb_id;
__s32 mid;
__s32 pid;
};
#define MAX_SIDETONE_IIR_DATA_SIZE 224
#define MAX_NO_IIR_FILTER_STAGE 10
struct audio_cal_info_sidetone_iir {
__u16 iir_enable;
__u16 num_biquad_stages;
__u16 pregain;
__s32 tx_acdb_id;
__s32 rx_acdb_id;
__s32 mid;
__s32 pid;
__u8 iir_config[MAX_SIDETONE_IIR_DATA_SIZE];
};
struct audio_cal_info_lsm_top {
__s32 topology;
__s32 acdb_id;
__s32 app_type;
};
struct audio_cal_info_lsm {
__s32 acdb_id;
/* RX_DEVICE or TX_DEVICE */
__s32 path;
__s32 app_type;
};
#define VSS_NUM_CHANNELS_MAX 32
struct audio_cal_info_voc_top {
__s32 topology;
__s32 acdb_id;
#ifdef TOPOLOGY_SPECIFIC_CHANNEL_INFO
__u32 num_channels;
__u8 channel_mapping[VSS_NUM_CHANNELS_MAX];
#endif
};
struct audio_cal_info_vocproc {
__s32 tx_acdb_id;
__s32 rx_acdb_id;
__s32 tx_sample_rate;
__s32 rx_sample_rate;
};
enum {
DEFAULT_FEATURE_SET,
VOL_BOOST_FEATURE_SET,
};
struct audio_cal_info_vocvol {
__s32 tx_acdb_id;
__s32 rx_acdb_id;
/* DEFAULT_ or VOL_BOOST_FEATURE_SET */
__s32 feature_set;
};
struct audio_cal_info_vocdev_cfg {
__s32 tx_acdb_id;
__s32 rx_acdb_id;
};
#define MAX_VOICE_COLUMNS 20
union audio_cal_col_na {
__u8 val8;
__u16 val16;
__u32 val32;
__u64 val64;
} __packed;
struct audio_cal_col {
__u32 id;
__u32 type;
union audio_cal_col_na na_value;
} __packed;
struct audio_cal_col_data {
__u32 num_columns;
struct audio_cal_col column[MAX_VOICE_COLUMNS];
} __packed;
struct audio_cal_info_voc_col {
__s32 table_id;
__s32 tx_acdb_id;
__s32 rx_acdb_id;
struct audio_cal_col_data data;
};
/* AUDIO_SET_CALIBRATION & */
struct audio_cal_type_basic {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
};
struct audio_cal_basic {
struct audio_cal_header hdr;
struct audio_cal_type_basic cal_type;
};
struct audio_cal_type_adm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_adm_top cal_info;
};
struct audio_cal_adm_top {
struct audio_cal_header hdr;
struct audio_cal_type_adm_top cal_type;
};
struct audio_cal_type_metainfo {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_metainfo cal_info;
};
struct audio_core_metainfo {
struct audio_cal_header hdr;
struct audio_cal_type_metainfo cal_type;
};
struct audio_cal_type_audproc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audproc cal_info;
};
struct audio_cal_audproc {
struct audio_cal_header hdr;
struct audio_cal_type_audproc cal_type;
};
struct audio_cal_type_audvol {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audvol cal_info;
};
struct audio_cal_audvol {
struct audio_cal_header hdr;
struct audio_cal_type_audvol cal_type;
};
struct audio_cal_type_asm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_asm_top cal_info;
};
struct audio_cal_asm_top {
struct audio_cal_header hdr;
struct audio_cal_type_asm_top cal_type;
};
struct audio_cal_type_audstrm {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_audstrm cal_info;
};
struct audio_cal_audstrm {
struct audio_cal_header hdr;
struct audio_cal_type_audstrm cal_type;
};
struct audio_cal_type_afe {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_afe cal_info;
};
struct audio_cal_afe {
struct audio_cal_header hdr;
struct audio_cal_type_afe cal_type;
};
struct audio_cal_type_afe_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_afe_top cal_info;
};
struct audio_cal_afe_top {
struct audio_cal_header hdr;
struct audio_cal_type_afe_top cal_type;
};
struct audio_cal_type_aanc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_aanc cal_info;
};
struct audio_cal_aanc {
struct audio_cal_header hdr;
struct audio_cal_type_aanc cal_type;
};
struct audio_cal_type_fb_spk_prot_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_spk_prot_cfg cal_info;
};
struct audio_cal_fb_spk_prot_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_fb_spk_prot_cfg cal_type;
};
struct audio_cal_type_sp_th_vi_ftm_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_ftm_cfg cal_info;
};
struct audio_cal_sp_th_vi_ftm_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_ftm_cfg cal_type;
};
struct audio_cal_type_sp_th_vi_v_vali_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_v_vali_cfg cal_info;
};
struct audio_cal_sp_th_vi_v_vali_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_v_vali_cfg cal_type;
};
struct audio_cal_type_sp_ex_vi_ftm_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_ex_vi_ftm_cfg cal_info;
};
struct audio_cal_sp_ex_vi_ftm_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_sp_ex_vi_ftm_cfg cal_type;
};
struct audio_cal_type_hw_delay {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_hw_delay cal_info;
};
struct audio_cal_hw_delay {
struct audio_cal_header hdr;
struct audio_cal_type_hw_delay cal_type;
};
struct audio_cal_type_sidetone {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sidetone cal_info;
};
struct audio_cal_sidetone {
struct audio_cal_header hdr;
struct audio_cal_type_sidetone cal_type;
};
struct audio_cal_type_sidetone_iir {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sidetone_iir cal_info;
};
struct audio_cal_sidetone_iir {
struct audio_cal_header hdr;
struct audio_cal_type_sidetone_iir cal_type;
};
struct audio_cal_type_lsm_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_lsm_top cal_info;
};
struct audio_cal_lsm_top {
struct audio_cal_header hdr;
struct audio_cal_type_lsm_top cal_type;
};
struct audio_cal_type_lsm {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_lsm cal_info;
};
struct audio_cal_lsm {
struct audio_cal_header hdr;
struct audio_cal_type_lsm cal_type;
};
struct audio_cal_type_voc_top {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_voc_top cal_info;
};
struct audio_cal_voc_top {
struct audio_cal_header hdr;
struct audio_cal_type_voc_top cal_type;
};
struct audio_cal_type_vocproc {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocproc cal_info;
};
struct audio_cal_vocproc {
struct audio_cal_header hdr;
struct audio_cal_type_vocproc cal_type;
};
struct audio_cal_type_vocvol {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocvol cal_info;
};
struct audio_cal_vocvol {
struct audio_cal_header hdr;
struct audio_cal_type_vocvol cal_type;
};
struct audio_cal_type_vocdev_cfg {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_vocdev_cfg cal_info;
};
struct audio_cal_vocdev_cfg {
struct audio_cal_header hdr;
struct audio_cal_type_vocdev_cfg cal_type;
};
struct audio_cal_type_voc_col {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_voc_col cal_info;
};
struct audio_cal_voc_col {
struct audio_cal_header hdr;
struct audio_cal_type_voc_col cal_type;
};
/* AUDIO_GET_CALIBRATION */
struct audio_cal_type_fb_spk_prot_status {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_msm_spk_prot_status cal_info;
};
struct audio_cal_fb_spk_prot_status {
struct audio_cal_header hdr;
struct audio_cal_type_fb_spk_prot_status cal_type;
};
struct audio_cal_type_sp_th_vi_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_param cal_info;
};
struct audio_cal_sp_th_vi_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_param cal_type;
};
struct audio_cal_type_sp_th_vi_v_vali_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_th_vi_v_vali_param cal_info;
};
struct audio_cal_sp_th_vi_v_vali_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_th_vi_v_vali_param cal_type;
};
struct audio_cal_type_sp_ex_vi_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_ex_vi_param cal_info;
};
struct audio_cal_sp_ex_vi_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_ex_vi_param cal_type;
};
struct audio_cal_type_sp_v4_ex_vi_param {
struct audio_cal_type_header cal_hdr;
struct audio_cal_data cal_data;
struct audio_cal_info_sp_v4_ex_vi_param cal_info;
};
struct audio_cal_sp_v4_ex_vi_param {
struct audio_cal_header hdr;
struct audio_cal_type_sp_v4_ex_vi_param cal_type;
};
#endif /* _UAPI_MSM_AUDIO_CALIBRATION_H */

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@@ -0,0 +1,367 @@
#ifndef _AUDIO_EFFECTS_H
#define _AUDIO_EFFECTS_H
#include <linux/types.h>
/** AUDIO EFFECTS **/
/* CONFIG GET/SET */
#define AUDIO_EFFECTS_CONFIG_CACHE 0
#define AUDIO_EFFECTS_CONFIG_SET 1
#define AUDIO_EFFECTS_CONFIG_GET 2
/* CONFIG HEADER */
/*
* MODULE_ID,
* DEVICE,
* NUM_COMMANDS,
* COMMAND_ID_1,
* AUDIO_EFFECTS_CONFIG_CACHE/SET/GET,
* OFFSET_1,
* LENGTH_1,
* VALUES_1,
* ...,
* ...,
* COMMAND_ID_2,
* AUDIO_EFFECTS_CONFIG_CACHE/SET/GET,
* OFFSET_2,
* LENGTH_2,
* VALUES_2,
* ...,
* ...,
* COMMAND_ID_3,
* ...
*/
/* CONFIG PARAM IDs */
#define VIRTUALIZER_MODULE 0x00001000
#define VIRTUALIZER_ENABLE 0x00001001
#define VIRTUALIZER_STRENGTH 0x00001002
#define VIRTUALIZER_OUT_TYPE 0x00001003
#define VIRTUALIZER_GAIN_ADJUST 0x00001004
#define VIRTUALIZER_ENABLE_PARAM_LEN 1
#define VIRTUALIZER_STRENGTH_PARAM_LEN 1
#define VIRTUALIZER_OUT_TYPE_PARAM_LEN 1
#define VIRTUALIZER_GAIN_ADJUST_PARAM_LEN 1
#define REVERB_MODULE 0x00002000
#define REVERB_ENABLE 0x00002001
#define REVERB_MODE 0x00002002
#define REVERB_PRESET 0x00002003
#define REVERB_WET_MIX 0x00002004
#define REVERB_GAIN_ADJUST 0x00002005
#define REVERB_ROOM_LEVEL 0x00002006
#define REVERB_ROOM_HF_LEVEL 0x00002007
#define REVERB_DECAY_TIME 0x00002008
#define REVERB_DECAY_HF_RATIO 0x00002009
#define REVERB_REFLECTIONS_LEVEL 0x0000200a
#define REVERB_REFLECTIONS_DELAY 0x0000200b
#define REVERB_LEVEL 0x0000200c
#define REVERB_DELAY 0x0000200d
#define REVERB_DIFFUSION 0x0000200e
#define REVERB_DENSITY 0x0000200f
#define REVERB_ENABLE_PARAM_LEN 1
#define REVERB_MODE_PARAM_LEN 1
#define REVERB_PRESET_PARAM_LEN 1
#define REVERB_WET_MIX_PARAM_LEN 1
#define REVERB_GAIN_ADJUST_PARAM_LEN 1
#define REVERB_ROOM_LEVEL_PARAM_LEN 1
#define REVERB_ROOM_HF_LEVEL_PARAM_LEN 1
#define REVERB_DECAY_TIME_PARAM_LEN 1
#define REVERB_DECAY_HF_RATIO_PARAM_LEN 1
#define REVERB_REFLECTIONS_LEVEL_PARAM_LEN 1
#define REVERB_REFLECTIONS_DELAY_PARAM_LEN 1
#define REVERB_LEVEL_PARAM_LEN 1
#define REVERB_DELAY_PARAM_LEN 1
#define REVERB_DIFFUSION_PARAM_LEN 1
#define REVERB_DENSITY_PARAM_LEN 1
#define BASS_BOOST_MODULE 0x00003000
#define BASS_BOOST_ENABLE 0x00003001
#define BASS_BOOST_MODE 0x00003002
#define BASS_BOOST_STRENGTH 0x00003003
#define BASS_BOOST_ENABLE_PARAM_LEN 1
#define BASS_BOOST_MODE_PARAM_LEN 1
#define BASS_BOOST_STRENGTH_PARAM_LEN 1
#define EQ_MODULE 0x00004000
#define EQ_ENABLE 0x00004001
#define EQ_CONFIG 0x00004002
#define EQ_NUM_BANDS 0x00004003
#define EQ_BAND_LEVELS 0x00004004
#define EQ_BAND_LEVEL_RANGE 0x00004005
#define EQ_BAND_FREQS 0x00004006
#define EQ_SINGLE_BAND_FREQ_RANGE 0x00004007
#define EQ_SINGLE_BAND_FREQ 0x00004008
#define EQ_BAND_INDEX 0x00004009
#define EQ_PRESET_ID 0x0000400a
#define EQ_NUM_PRESETS 0x0000400b
#define EQ_PRESET_NAME 0x0000400c
#define EQ_ENABLE_PARAM_LEN 1
#define EQ_CONFIG_PARAM_LEN 3
#define EQ_CONFIG_PER_BAND_PARAM_LEN 5
#define EQ_NUM_BANDS_PARAM_LEN 1
#define EQ_BAND_LEVELS_PARAM_LEN 13
#define EQ_BAND_LEVEL_RANGE_PARAM_LEN 2
#define EQ_BAND_FREQS_PARAM_LEN 13
#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN 2
#define EQ_SINGLE_BAND_FREQ_PARAM_LEN 1
#define EQ_BAND_INDEX_PARAM_LEN 1
#define EQ_PRESET_ID_PARAM_LEN 1
#define EQ_NUM_PRESETS_PARAM_LEN 1
#define EQ_PRESET_NAME_PARAM_LEN 32
#define EQ_TYPE_NONE 0
#define EQ_BASS_BOOST 1
#define EQ_BASS_CUT 2
#define EQ_TREBLE_BOOST 3
#define EQ_TREBLE_CUT 4
#define EQ_BAND_BOOST 5
#define EQ_BAND_CUT 6
#define SOFT_VOLUME_MODULE 0x00006000
#define SOFT_VOLUME_ENABLE 0x00006001
#define SOFT_VOLUME_GAIN_2CH 0x00006002
#define SOFT_VOLUME_GAIN_MASTER 0x00006003
#define SOFT_VOLUME_ENABLE_PARAM_LEN 1
#define SOFT_VOLUME_GAIN_2CH_PARAM_LEN 2
#define SOFT_VOLUME_GAIN_MASTER_PARAM_LEN 1
#define SOFT_VOLUME2_MODULE 0x00007000
#define SOFT_VOLUME2_ENABLE 0x00007001
#define SOFT_VOLUME2_GAIN_2CH 0x00007002
#define SOFT_VOLUME2_GAIN_MASTER 0x00007003
#define SOFT_VOLUME2_ENABLE_PARAM_LEN SOFT_VOLUME_ENABLE_PARAM_LEN
#define SOFT_VOLUME2_GAIN_2CH_PARAM_LEN SOFT_VOLUME_GAIN_2CH_PARAM_LEN
#define SOFT_VOLUME2_GAIN_MASTER_PARAM_LEN \
SOFT_VOLUME_GAIN_MASTER_PARAM_LEN
#define PBE_CONF_MODULE_ID 0x00010C2A
#define PBE_CONF_PARAM_ID 0x00010C49
#define PBE_MODULE 0x00008000
#define PBE_ENABLE 0x00008001
#define PBE_CONFIG 0x00008002
#define PBE_ENABLE_PARAM_LEN 1
#define PBE_CONFIG_PARAM_LEN 28
/* Command Payload length and size for Non-IID commands */
#define COMMAND_PAYLOAD_LEN 3
#define COMMAND_PAYLOAD_SZ (COMMAND_PAYLOAD_LEN * sizeof(__u32))
/* Command Payload length and size for IID commands */
#define COMMAND_IID_PAYLOAD_LEN 4
#define COMMAND_IID_PAYLOAD_SZ (COMMAND_IID_PAYLOAD_LEN * sizeof(__u32))
#define MAX_INBAND_PARAM_SZ 4096
#define Q27_UNITY (1 << 27)
#define Q8_UNITY (1 << 8)
#define CUSTOM_OPENSL_PRESET 18
#define VIRTUALIZER_ENABLE_PARAM_SZ \
(VIRTUALIZER_ENABLE_PARAM_LEN*sizeof(__u32))
#define VIRTUALIZER_STRENGTH_PARAM_SZ \
(VIRTUALIZER_STRENGTH_PARAM_LEN*sizeof(__u32))
#define VIRTUALIZER_OUT_TYPE_PARAM_SZ \
(VIRTUALIZER_OUT_TYPE_PARAM_LEN*sizeof(__u32))
#define VIRTUALIZER_GAIN_ADJUST_PARAM_SZ \
(VIRTUALIZER_GAIN_ADJUST_PARAM_LEN*sizeof(__u32))
struct virtualizer_params {
__u32 device;
__u32 enable_flag;
__u32 strength;
__u32 out_type;
__s32 gain_adjust;
};
#define NUM_OSL_REVERB_PRESETS_SUPPORTED 6
#define REVERB_ENABLE_PARAM_SZ \
(REVERB_ENABLE_PARAM_LEN*sizeof(__u32))
#define REVERB_MODE_PARAM_SZ \
(REVERB_MODE_PARAM_LEN*sizeof(__u32))
#define REVERB_PRESET_PARAM_SZ \
(REVERB_PRESET_PARAM_LEN*sizeof(__u32))
#define REVERB_WET_MIX_PARAM_SZ \
(REVERB_WET_MIX_PARAM_LEN*sizeof(__u32))
#define REVERB_GAIN_ADJUST_PARAM_SZ \
(REVERB_GAIN_ADJUST_PARAM_LEN*sizeof(__u32))
#define REVERB_ROOM_LEVEL_PARAM_SZ \
(REVERB_ROOM_LEVEL_PARAM_LEN*sizeof(__u32))
#define REVERB_ROOM_HF_LEVEL_PARAM_SZ \
(REVERB_ROOM_HF_LEVEL_PARAM_LEN*sizeof(__u32))
#define REVERB_DECAY_TIME_PARAM_SZ \
(REVERB_DECAY_TIME_PARAM_LEN*sizeof(__u32))
#define REVERB_DECAY_HF_RATIO_PARAM_SZ \
(REVERB_DECAY_HF_RATIO_PARAM_LEN*sizeof(__u32))
#define REVERB_REFLECTIONS_LEVEL_PARAM_SZ \
(REVERB_REFLECTIONS_LEVEL_PARAM_LEN*sizeof(__u32))
#define REVERB_REFLECTIONS_DELAY_PARAM_SZ \
(REVERB_REFLECTIONS_DELAY_PARAM_LEN*sizeof(__u32))
#define REVERB_LEVEL_PARAM_SZ \
(REVERB_LEVEL_PARAM_LEN*sizeof(__u32))
#define REVERB_DELAY_PARAM_SZ \
(REVERB_DELAY_PARAM_LEN*sizeof(__u32))
#define REVERB_DIFFUSION_PARAM_SZ \
(REVERB_DIFFUSION_PARAM_LEN*sizeof(__u32))
#define REVERB_DENSITY_PARAM_SZ \
(REVERB_DENSITY_PARAM_LEN*sizeof(__u32))
struct reverb_params {
__u32 device;
__u32 enable_flag;
__u32 mode;
__u32 preset;
__u32 wet_mix;
__s32 gain_adjust;
__s32 room_level;
__s32 room_hf_level;
__u32 decay_time;
__u32 decay_hf_ratio;
__s32 reflections_level;
__u32 reflections_delay;
__s32 level;
__u32 delay;
__u32 diffusion;
__u32 density;
};
#define BASS_BOOST_ENABLE_PARAM_SZ \
(BASS_BOOST_ENABLE_PARAM_LEN*sizeof(__u32))
#define BASS_BOOST_MODE_PARAM_SZ \
(BASS_BOOST_MODE_PARAM_LEN*sizeof(__u32))
#define BASS_BOOST_STRENGTH_PARAM_SZ \
(BASS_BOOST_STRENGTH_PARAM_LEN*sizeof(__u32))
struct bass_boost_params {
__u32 device;
__u32 enable_flag;
__u32 mode;
__u32 strength;
};
#define MAX_EQ_BANDS 12
#define MAX_OSL_EQ_BANDS 5
#define EQ_ENABLE_PARAM_SZ \
(EQ_ENABLE_PARAM_LEN*sizeof(__u32))
#define EQ_CONFIG_PARAM_SZ \
(EQ_CONFIG_PARAM_LEN*sizeof(__u32))
#define EQ_CONFIG_PER_BAND_PARAM_SZ \
(EQ_CONFIG_PER_BAND_PARAM_LEN*sizeof(__u32))
#define EQ_CONFIG_PARAM_MAX_LEN (EQ_CONFIG_PARAM_LEN+\
MAX_EQ_BANDS*EQ_CONFIG_PER_BAND_PARAM_LEN)
#define EQ_CONFIG_PARAM_MAX_SZ \
(EQ_CONFIG_PARAM_MAX_LEN*sizeof(__u32))
#define EQ_NUM_BANDS_PARAM_SZ \
(EQ_NUM_BANDS_PARAM_LEN*sizeof(__u32))
#define EQ_BAND_LEVELS_PARAM_SZ \
(EQ_BAND_LEVELS_PARAM_LEN*sizeof(__u32))
#define EQ_BAND_LEVEL_RANGE_PARAM_SZ \
(EQ_BAND_LEVEL_RANGE_PARAM_LEN*sizeof(__u32))
#define EQ_BAND_FREQS_PARAM_SZ \
(EQ_BAND_FREQS_PARAM_LEN*sizeof(__u32))
#define EQ_SINGLE_BAND_FREQ_RANGE_PARAM_SZ \
(EQ_SINGLE_BAND_FREQ_RANGE_PARAM_LEN*sizeof(__u32))
#define EQ_SINGLE_BAND_FREQ_PARAM_SZ \
(EQ_SINGLE_BAND_FREQ_PARAM_LEN*sizeof(__u32))
#define EQ_BAND_INDEX_PARAM_SZ \
(EQ_BAND_INDEX_PARAM_LEN*sizeof(__u32))
#define EQ_PRESET_ID_PARAM_SZ \
(EQ_PRESET_ID_PARAM_LEN*sizeof(__u32))
#define EQ_NUM_PRESETS_PARAM_SZ \
(EQ_NUM_PRESETS_PARAM_LEN*sizeof(__u8))
struct eq_config_t {
__s32 eq_pregain;
__s32 preset_id;
__u32 num_bands;
};
struct eq_per_band_config_t {
__s32 band_idx;
__u32 filter_type;
__u32 freq_millihertz;
__s32 gain_millibels;
__u32 quality_factor;
};
struct eq_per_band_freq_range_t {
__u32 band_index;
__u32 min_freq_millihertz;
__u32 max_freq_millihertz;
};
struct eq_params {
__u32 device;
__u32 enable_flag;
struct eq_config_t config;
struct eq_per_band_config_t per_band_cfg[MAX_EQ_BANDS];
struct eq_per_band_freq_range_t per_band_freq_range[MAX_EQ_BANDS];
__u32 band_index;
__u32 freq_millihertz;
};
#define PBE_ENABLE_PARAM_SZ \
(PBE_ENABLE_PARAM_LEN*sizeof(__u32))
#define PBE_CONFIG_PARAM_SZ \
(PBE_CONFIG_PARAM_LEN*sizeof(__u16))
struct pbe_config_t {
__s16 real_bass_mix;
__s16 bass_color_control;
__u16 main_chain_delay;
__u16 xover_filter_order;
__u16 bandpass_filter_order;
__s16 drc_delay;
__u16 rms_tav;
__s16 exp_threshold;
__u16 exp_slope;
__s16 comp_threshold;
__u16 comp_slope;
__u16 makeup_gain;
__u32 comp_attack;
__u32 comp_release;
__u32 exp_attack;
__u32 exp_release;
__s16 limiter_bass_threshold;
__s16 limiter_high_threshold;
__s16 limiter_bass_makeup_gain;
__s16 limiter_high_makeup_gain;
__s16 limiter_bass_gc;
__s16 limiter_high_gc;
__s16 limiter_delay;
__u16 reserved;
/* place holder for filter coeffs to be followed */
__s32 p1LowPassCoeffs[5*2];
__s32 p1HighPassCoeffs[5*2];
__s32 p1BandPassCoeffs[5*3];
__s32 p1BassShelfCoeffs[5];
__s32 p1TrebleShelfCoeffs[5];
} __packed;
struct pbe_params {
__u32 device;
__u32 enable_flag;
__u32 cfg_len;
struct pbe_config_t config;
};
#define SOFT_VOLUME_ENABLE_PARAM_SZ \
(SOFT_VOLUME_ENABLE_PARAM_LEN*sizeof(__u32))
#define SOFT_VOLUME_GAIN_MASTER_PARAM_SZ \
(SOFT_VOLUME_GAIN_MASTER_PARAM_LEN*sizeof(__u32))
#define SOFT_VOLUME_GAIN_2CH_PARAM_SZ \
(SOFT_VOLUME_GAIN_2CH_PARAM_LEN*sizeof(__u16))
struct soft_volume_params {
__u32 device;
__u32 enable_flag;
__u32 master_gain;
__u32 left_gain;
__u32 right_gain;
};
struct msm_nt_eff_all_config {
struct bass_boost_params bass_boost;
struct pbe_params pbe;
struct virtualizer_params virtualizer;
struct reverb_params reverb;
struct eq_params equalizer;
struct soft_volume_params saplus_vol;
struct soft_volume_params topo_switch_vol;
};
#endif /*_MSM_AUDIO_EFFECTS_H*/

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qcom/opensource/audio-kernel/include/uapi/audio/sound/audio_slimslave.h Normal file
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#ifndef __AUDIO_SLIMSLAVE_H__
#define __AUDIO_SLIMSLAVE_H__
#include <linux/types.h>
#include <linux/ioctl.h>
#define AUDIO_SLIMSLAVE_IOCTL_NAME "audio_slimslave"
#define AUDIO_SLIMSLAVE_MAGIC 'S'
#define AUDIO_SLIMSLAVE_IOCTL_UNVOTE _IO(AUDIO_SLIMSLAVE_MAGIC, 0x00)
#define AUDIO_SLIMSLAVE_IOCTL_VOTE _IO(AUDIO_SLIMSLAVE_MAGIC, 0x01)
enum {
AUDIO_SLIMSLAVE_UNVOTE,
AUDIO_SLIMSLAVE_VOTE
};
#endif

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qcom/opensource/audio-kernel/include/uapi/audio/sound/devdep_params.h Normal file
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#ifndef _DEV_DEP_H
#define _DEV_DEP_H
#include <linux/types.h>
struct dolby_param_data {
__s32 version;
__s32 device_id;
__s32 be_id;
__s32 param_id;
__s32 length;
__s32 __user *data;
};
struct dolby_param_license {
__s32 dmid;
__s32 license_key;
};
#define SNDRV_DEVDEP_DAP_IOCTL_SET_PARAM\
_IOWR('U', 0x10, struct dolby_param_data)
#define SNDRV_DEVDEP_DAP_IOCTL_GET_PARAM\
_IOR('U', 0x11, struct dolby_param_data)
#define SNDRV_DEVDEP_DAP_IOCTL_DAP_COMMAND\
_IOWR('U', 0x13, struct dolby_param_data)
#define SNDRV_DEVDEP_DAP_IOCTL_DAP_LICENSE\
_IOWR('U', 0x14, struct dolby_param_license)
#define SNDRV_DEVDEP_DAP_IOCTL_GET_VISUALIZER\
_IOR('U', 0x15, struct dolby_param_data)
#define DTS_EAGLE_MODULE 0x00005000
#define DTS_EAGLE_MODULE_ENABLE 0x00005001
#define EAGLE_DRIVER_ID 0xF2
#define DTS_EAGLE_IOCTL_GET_CACHE_SIZE _IOR(EAGLE_DRIVER_ID, 0, int)
#define DTS_EAGLE_IOCTL_SET_CACHE_SIZE _IOW(EAGLE_DRIVER_ID, 1, int)
#define DTS_EAGLE_IOCTL_GET_PARAM _IOR(EAGLE_DRIVER_ID, 2, void*)
#define DTS_EAGLE_IOCTL_SET_PARAM _IOW(EAGLE_DRIVER_ID, 3, void*)
#define DTS_EAGLE_IOCTL_SET_CACHE_BLOCK _IOW(EAGLE_DRIVER_ID, 4, void*)
#define DTS_EAGLE_IOCTL_SET_ACTIVE_DEVICE _IOW(EAGLE_DRIVER_ID, 5, void*)
#define DTS_EAGLE_IOCTL_GET_LICENSE _IOR(EAGLE_DRIVER_ID, 6, void*)
#define DTS_EAGLE_IOCTL_SET_LICENSE _IOW(EAGLE_DRIVER_ID, 7, void*)
#define DTS_EAGLE_IOCTL_SEND_LICENSE _IOW(EAGLE_DRIVER_ID, 8, int)
#define DTS_EAGLE_IOCTL_SET_VOLUME_COMMANDS _IOW(EAGLE_DRIVER_ID, 9, void*)
#define DTS_EAGLE_FLAG_IOCTL_PRE (1<<30)
#define DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE (1<<31)
#define DTS_EAGLE_FLAG_IOCTL_GETFROMCORE DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE
#define DTS_EAGLE_FLAG_IOCTL_MASK (~(DTS_EAGLE_FLAG_IOCTL_PRE | \
DTS_EAGLE_FLAG_IOCTL_JUSTSETCACHE))
#define DTS_EAGLE_FLAG_ALSA_GET (1<<31)
struct dts_eagle_param_desc {
__u32 id;
__u32 size;
__s32 offset;
__u32 device;
} __packed;
#define HWDEP_FE_BASE 3000 /*unique base for FE hw dep nodes*/
struct snd_pcm_mmap_fd {
__s32 dir;
__s32 fd;
__s32 size;
__s32 actual_size;
};
struct snd_pcm_prsnt_position {
__u64 timestamp;
__u64 frames;
__s32 clock_id;
};
#define SNDRV_PCM_IOCTL_MMAP_DATA_FD _IOWR('U', 0xd2, struct snd_pcm_mmap_fd)
#define SNDRV_PCM_IOCTL_DSP_POSITION\
_IOWR('U', 0xd3, struct snd_pcm_prsnt_position)
#endif

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qcom/opensource/audio-kernel/include/uapi/audio/sound/lsm_params.h Normal file
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#ifndef _UAPI_LSM_PARAMS_H__
#define _UAPI_LSM_PARAMS_H__
#define LSM_POLLING_ENABLE_SUPPORT
#define LSM_EVENT_TIMESTAMP_MODE_SUPPORT
#include <linux/types.h>
#define SNDRV_LSM_VERSION SNDRV_PROTOCOL_VERSION(0, 3, 2)
#define LSM_MAX_STAGES_PER_SESSION 2
#define LSM_STAGE_INDEX_FIRST 0
#define LSM_OUT_FORMAT_PCM (0)
#define LSM_OUT_FORMAT_ADPCM (1 << 0)
#define LSM_OUT_DATA_RAW (0)
#define LSM_OUT_DATA_PACKED (1)
#define LSM_OUT_DATA_EVENTS_DISABLED (0)
#define LSM_OUT_DATA_EVENTS_ENABLED (1)
#define LSM_OUT_TRANSFER_MODE_RT (0)
#define LSM_OUT_TRANSFER_MODE_FTRT (1)
#define LSM_ENDPOINT_DETECT_THRESHOLD (0)
#define LSM_OPERATION_MODE (1)
#define LSM_GAIN (2)
#define LSM_MIN_CONFIDENCE_LEVELS (3)
#define LSM_REG_SND_MODEL (4)
#define LSM_DEREG_SND_MODEL (5)
#define LSM_CUSTOM_PARAMS (6)
#define LSM_POLLING_ENABLE (7)
#define LSM_DET_EVENT_TYPE (8)
#define LSM_LAB_CONTROL (9)
#define LSM_REG_MULTI_SND_MODEL (10)
#define LSM_DEREG_MULTI_SND_MODEL (11)
#define LSM_MULTI_SND_MODEL_CONFIDENCE_LEVELS (12)
#define LSM_GET_CUSTOM_PARAMS (13)
#define LSM_PARAMS_MAX (LSM_GET_CUSTOM_PARAMS + 1)
#define LSM_EVENT_NON_TIME_STAMP_MODE (0)
#define LSM_EVENT_TIME_STAMP_MODE (1)
#define LSM_DET_EVENT_TYPE_LEGACY (0)
#define LSM_DET_EVENT_TYPE_GENERIC (1)
/* Valid sample rates for input hw_params */
#define LSM_INPUT_SAMPLE_RATE_16K 16000
#define LSM_INPUT_SAMPLE_RATE_48K 48000
/* Valid bit-widths for input hw_params */
#define LSM_INPUT_BIT_WIDTH_16 16
#define LSM_INPUT_BIT_WIDTH_24 24
/* Min and Max channels for input hw_params */
#define LSM_INPUT_NUM_CHANNELS_MIN 1
#define LSM_INPUT_NUM_CHANNELS_MAX 9
enum lsm_app_id {
LSM_VOICE_WAKEUP_APP_ID = 1,
LSM_VOICE_WAKEUP_APP_ID_V2 = 2,
};
enum lsm_detection_mode {
LSM_MODE_KEYWORD_ONLY_DETECTION = 1,
LSM_MODE_USER_KEYWORD_DETECTION
};
enum lsm_vw_status {
LSM_VOICE_WAKEUP_STATUS_RUNNING = 1,
LSM_VOICE_WAKEUP_STATUS_DETECTED,
LSM_VOICE_WAKEUP_STATUS_END_SPEECH,
LSM_VOICE_WAKEUP_STATUS_REJECTED
};
/*
* Data for LSM_ENDPOINT_DETECT_THRESHOLD param_type
* @epd_begin: Begin threshold
* @epd_end: End threshold
*/
struct snd_lsm_ep_det_thres {
__u32 epd_begin;
__u32 epd_end;
};
/*
* Data for LSM_OPERATION_MODE param_type
* @mode: The detection mode to be used
* @detect_failure: Setting to enable failure detections.
*/
struct snd_lsm_detect_mode {
enum lsm_detection_mode mode;
_Bool detect_failure;
};
/*
* Data for LSM_GAIN param_type
* @gain: The gain to be applied on LSM
*/
struct snd_lsm_gain {
__u16 gain;
};
/*
* Data for LSM_POLLING_ENABLE param_type
* @poll_en: Polling enable or disable
*/
struct snd_lsm_poll_enable {
_Bool poll_en;
};
/*
* Data for LSM_DET_EVENT_TYPE param_type
* @event_type: LSM_DET_EVENT_TYPE_LEGACY or LSM_DET_EVENT_TYPE_GENERIC
* @mode: Type of information in detection event payload
*/
struct snd_lsm_det_event_type {
__u32 event_type;
__u32 mode;
};
struct snd_lsm_sound_model_v2 {
__u8 __user *data;
__u8 *confidence_level;
__u32 data_size;
enum lsm_detection_mode detection_mode;
__u8 num_confidence_levels;
_Bool detect_failure;
};
struct snd_lsm_session_data {
enum lsm_app_id app_id;
};
/*
* Stage info for multi-stage session
* @app_type: acdb app_type to be used to map topology/cal for the stage
* @lpi_enable: low power island mode applicable for the stage
*/
struct snd_lsm_stage_info {
__u32 app_type;
__u32 lpi_enable;
};
/*
* Session info for multi-stage session
* @app_id: VoiceWakeup engine id, this is now used to just validate input arg
* @num_stages: number of detection stages to be used
* @stage_info: stage info for each of the stage being used, ordered by index
*/
struct snd_lsm_session_data_v2 {
enum lsm_app_id app_id;
__u32 num_stages;
struct snd_lsm_stage_info stage_info[LSM_MAX_STAGES_PER_SESSION];
};
/*
* Data for LSM_LAB_CONTROL param_type
* @enable: lab enable or disable
*/
struct snd_lsm_lab_control {
__u32 enable;
};
struct snd_lsm_event_status {
__u16 status;
__u16 payload_size;
__u8 payload[0];
};
struct snd_lsm_event_status_v3 {
__u32 timestamp_lsw;
__u32 timestamp_msw;
__u16 status;
__u16 payload_size;
__u8 payload[0];
};
struct snd_lsm_detection_params {
__u8 *conf_level;
enum lsm_detection_mode detect_mode;
__u8 num_confidence_levels;
_Bool detect_failure;
_Bool poll_enable;
};
/*
* Param info for each parameter type
* @module_id: Module to which parameter is to be set
* @param_id: Parameter that is to be set
* @param_size: size (in number of bytes) for the data
* in param_data.
* For confidence levels, this is num_conf_levels
* For REG_SND_MODEL, this is size of sound model
* For CUSTOM_PARAMS, this is size of the entire blob of data
* @param_data: Data for the parameter.
* For some param_types this is a structure defined, ex: LSM_GAIN
* For CONFIDENCE_LEVELS, this is array of confidence levels
* For REG_SND_MODEL, this is the sound model data
* For CUSTOM_PARAMS, this is the blob of custom data.
* @param_type: Parameter type as defined in values upto LSM_PARAMS_MAX
*/
struct lsm_params_info {
__u32 module_id;
__u32 param_id;
__u32 param_size;
__u8 __user *param_data;
__u32 param_type;
};
/*
* Param info(version 2) for each parameter type
*
* Existing member variables:
* @module_id: Module to which parameter is to be set
* @param_id: Parameter that is to be set
* @param_size: size (in number of bytes) for the data
* in param_data.
* For confidence levels, this is num_conf_levels
* For REG_SND_MODEL, this is size of sound model
* For CUSTOM_PARAMS, this is size of the entire blob of data
* @param_data: Data for the parameter.
* For some param_types this is a structure defined, ex: LSM_GAIN
* For CONFIDENCE_LEVELS, this is array of confidence levels
* For REG_SND_MODEL, this is the sound model data
* For CUSTOM_PARAMS, this is the blob of custom data.
* @param_type: Parameter type as defined in values upto LSM_PARAMS_MAX
*
* Member variables applicable only to V2:
* @instance_id: instance id of the param to which parameter is to be set
* @stage_idx: detection stage for which the param is applicable
* @model_id: an unique number to identify sound models in DSP
*/
struct lsm_params_info_v2 {
__u32 module_id;
__u32 param_id;
__u32 param_size;
__u8 __user *param_data;
__u32 param_type;
__u16 instance_id;
__u16 stage_idx;
__u32 model_id;
};
/*
* Data passed to the SET_PARAM_V2 IOCTL
* @num_params: Number of params that are to be set
* should not be greater than LSM_PARAMS_MAX
* @params: Points to an array of lsm_params_info
* Each entry points to one parameter to set
* @data_size: size (in bytes) for params
* should be equal to
* num_params * sizeof(struct lsm_parms_info)
*/
struct snd_lsm_module_params {
__u8 __user *params;
__u32 num_params;
__u32 data_size;
};
/*
* Data passed to LSM_OUT_FORMAT_CFG IOCTL
* @format: The media format enum
* @packing: indicates the packing method used for data path
* @events: indicates whether data path events need to be enabled
* @transfer_mode: indicates whether FTRT mode or RT mode.
*/
struct snd_lsm_output_format_cfg {
__u8 format;
__u8 packing;
__u8 events;
__u8 mode;
};
/*
* Data passed to SNDRV_LSM_SET_INPUT_HW_PARAMS ioctl
*
* @sample_rate: Sample rate of input to lsm.
* valid values are 16000 and 48000
* @bit_width: Bit width of audio samples input to lsm.
* valid values are 16 and 24
* @num_channels: Number of channels input to lsm.
* valid values are range from 1 to 16
*/
struct snd_lsm_input_hw_params {
__u32 sample_rate;
__u16 bit_width;
__u16 num_channels;
} __packed;
/*
* Param get info for each parameter type
* add "for SNDRV_LSM_GET_MODULE_PARAMS ioctl"
* Existing member variables:
* @module_id: Module to which parameter is to be set
* @instance_id: instance id of the param to which parameter is to be set
* @param_id: Parameter that is to be set
* @param_size: size of requested param
* @param_type: Parameter type as defined in values upto LSM_PARAMS_MAX
* @stage_idx: detection stage for which the param is applicable
* @payload: memory where requested param info will be populated
*/
struct lsm_params_get_info {
__u32 module_id;
__u16 instance_id;
__u16 reserved;
__u32 param_id;
__u32 param_size;
__u32 param_type;
__u16 stage_idx;
__u8 payload[0];
} __packed;
#define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int)
#define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status)
#define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int)
#define SNDRV_LSM_START _IOW('U', 0x04, int)
#define SNDRV_LSM_STOP _IOW('U', 0x05, int)
#define SNDRV_LSM_SET_SESSION_DATA _IOW('U', 0x06, struct snd_lsm_session_data)
#define SNDRV_LSM_REG_SND_MODEL_V2 _IOW('U', 0x07,\
struct snd_lsm_sound_model_v2)
#define SNDRV_LSM_LAB_CONTROL _IOW('U', 0x08, __u32)
#define SNDRV_LSM_STOP_LAB _IO('U', 0x09)
#define SNDRV_LSM_SET_PARAMS _IOW('U', 0x0A, \
struct snd_lsm_detection_params)
#define SNDRV_LSM_SET_MODULE_PARAMS _IOW('U', 0x0B, \
struct snd_lsm_module_params)
#define SNDRV_LSM_OUT_FORMAT_CFG _IOW('U', 0x0C, \
struct snd_lsm_output_format_cfg)
#define SNDRV_LSM_SET_PORT _IO('U', 0x0D)
#define SNDRV_LSM_SET_FWK_MODE_CONFIG _IOW('U', 0x0E, __u32)
#define SNDRV_LSM_EVENT_STATUS_V3 _IOW('U', 0x0F, \
struct snd_lsm_event_status_v3)
#define SNDRV_LSM_GENERIC_DET_EVENT _IOW('U', 0x10, struct snd_lsm_event_status)
#define SNDRV_LSM_SET_INPUT_HW_PARAMS _IOW('U', 0x11, \
struct snd_lsm_input_hw_params)
#define SNDRV_LSM_SET_SESSION_DATA_V2 _IOW('U', 0x12, \
struct snd_lsm_session_data_v2)
#define SNDRV_LSM_SET_MODULE_PARAMS_V2 _IOW('U', 0x13, \
struct snd_lsm_module_params)
#define SNDRV_LSM_GET_MODULE_PARAMS _IOWR('U', 0x14, \
struct lsm_params_get_info)
#endif

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qcom/opensource/audio-kernel/include/uapi/audio/sound/msmcal-hwdep.h Normal file
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#ifndef _CALIB_HWDEP_H
#define _CALIB_HWDEP_H
#include <linux/types.h>
#define WCD9XXX_CODEC_HWDEP_NODE 1000
#define AQT1000_CODEC_HWDEP_NODE 1001
#define Q6AFE_HWDEP_NODE 1002
enum wcd_cal_type {
WCD9XXX_MIN_CAL,
WCD9XXX_ANC_CAL = WCD9XXX_MIN_CAL,
WCD9XXX_MAD_CAL,
WCD9XXX_MBHC_CAL,
WCD9XXX_VBAT_CAL,
WCD9XXX_MAX_CAL,
};
struct wcdcal_ioctl_buffer {
__u32 size;
__u8 __user *buffer;
enum wcd_cal_type cal_type;
};
#define SNDRV_CTL_IOCTL_HWDEP_CAL_TYPE \
_IOW('U', 0x1, struct wcdcal_ioctl_buffer)
enum q6afe_cal_type {
Q6AFE_MIN_CAL,
Q6AFE_VAD_CORE_CAL = Q6AFE_MIN_CAL,
Q6AFE_MAX_CAL,
};
struct q6afecal_ioctl_buffer {
__u32 size;
__u8 __user *buffer;
enum q6afe_cal_type cal_type;
};
#define SNDRV_IOCTL_HWDEP_VAD_CAL_TYPE \
_IOW('U', 0x1, struct q6afecal_ioctl_buffer)
#endif /*_CALIB_HWDEP_H*/

13
qcom/opensource/audio-kernel/include/uapi/audio/sound/voice_params.h Normal file
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#ifndef __VOICE_PARAMS_H__
#define __VOICE_PARAMS_H__
#include <linux/types.h>
enum voice_lch_mode {
VOICE_LCH_START = 1,
VOICE_LCH_STOP
};
#define SNDRV_VOICE_IOCTL_LCH _IOW('U', 0x00, enum voice_lch_mode)
#endif

60
qcom/opensource/audio-kernel/include/uapi/audio/sound/wcd-dsp-glink.h Normal file
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#ifndef _WCD_DSP_GLINK_H
#define _WCD_DSP_GLINK_H
#include <linux/types.h>
#define WDSP_CH_NAME_MAX_LEN 50
enum {
WDSP_REG_PKT = 1,
WDSP_CMD_PKT,
WDSP_READY_PKT,
};
#define WDSP_READY_PKT WDSP_READY_PKT
/*
* struct wdsp_reg_pkt - Glink channel information structure format
* @no_of_channels: Number of glink channels to open
* @payload[0]: Dynamic array contains all the glink channels information
*/
struct wdsp_reg_pkt {
__u8 no_of_channels;
__u8 payload[0];
};
/*
* struct wdsp_cmd_pkt - WDSP command packet format
* @ch_name: Name of the glink channel
* @payload_size: Size of the payload
* @payload[0]: Actual data payload
*/
struct wdsp_cmd_pkt {
char ch_name[WDSP_CH_NAME_MAX_LEN];
__u32 payload_size;
__u8 payload[0];
};
/*
* struct wdsp_write_pkt - Format that userspace send the data to driver.
* @pkt_type: Type of the packet(REG or CMD PKT)
* @payload[0]: Payload is either cmd or reg pkt structure based on pkt type
*/
struct wdsp_write_pkt {
__u8 pkt_type;
__u8 payload[0];
};
/*
* struct wdsp_glink_ch_cfg - Defines the glink channel configuration.
* @ch_name: Name of the glink channel
* @latency_in_us: Latency specified in micro seconds for QOS
* @no_of_intents: Number of intents prequeued
* @intents_size[0]: Dynamic array to specify size of each intent
*/
struct wdsp_glink_ch_cfg {
char name[WDSP_CH_NAME_MAX_LEN];
__u32 latency_in_us;
__u32 no_of_intents;
__u32 intents_size[0];
};
#endif /* _WCD_DSP_GLINK_H */