samsung_sm8750/android_kernel_samsung_sm8750-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

replace common qcom sources with samsung ones

Browse Source
This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
Download Patch File Download Diff File Expand all files Collapse all files

377
qcom/opensource/wlan/fw-api/fw/htt.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -265,11 +265,9 @@
* 3.135 Add HTT_HOST4_TO_FW_RXBUF_RING def.
* 3.136 Add htt_ext_present flag in htt_tx_tcl_global_seq_metadata.
* 3.137 Add more HTT_SDWF_MSDUQ_CFG_IND_ERROR codes.
* 3.138 Add T2H MLO_LATENCY_REQ, H2T _RESP msg defs.
* 3.139 Add CLASS_INFO_IDX field in MLO_R_PEER_MAP msg.
*/
#define HTT_CURRENT_VERSION_MAJOR 3
#define HTT_CURRENT_VERSION_MINOR 139
#define HTT_CURRENT_VERSION_MINOR 137
#define HTT_NUM_TX_FRAG_DESC 1024
@@ -837,15 +835,6 @@ typedef enum {
HTT_STATS_TXBF_OFDMA_BE_PARBW_TAG = 201, /* htt_stats_txbf_ofdma_be_parbw_tlv */
HTT_STATS_RX_PDEV_RSSI_HIST_TAG = 202, /* htt_stats_rx_pdev_rssi_hist_tlv */
HTT_STATS_TX_VDEV_NSS_TAG = 203, /* htt_stats_tx_vdev_nss_tlv */
HTT_STATS_PDEV_SPECTRAL_TAG = 204, /* htt_stats_pdev_spectral_tlv */
HTT_STATS_PDEV_RTT_DELAY_TAG = 205, /* htt_stats_pdev_rtt_delay_tlv */
HTT_STATS_PDEV_AOA_TAG = 206, /* htt_stats_pdev_aoa_tlv */
HTT_STATS_PDEV_FTM_TPCCAL_TAG = 207, /* htt_stats_pdev_ftm_tpccal_tlv */
HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG = 208, /* htt_stats_pdev_ulmumimo_grp_stats_tlv */
HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG = 209, /* htt_stats_pdev_ulmumimo_denylist_stats_tlv */
HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG = 210, /* htt_stats_pdev_ulmumimo_seq_term_stats_tlv */
HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG = 211, /* htt_stats_pdev_ulmumimo_hist_ineligibility_tlv */
HTT_STATS_PHY_PAPRD_PB_TAG = 212, /* htt_stats_phy_paprd_pb_tlv */
HTT_STATS_MAX_TAG,
} htt_stats_tlv_tag_t;
@@ -920,7 +909,6 @@ enum htt_h2t_msg_type {
HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25,
HTT_H2T_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP = 0x26,
HTT_H2T_MSG_TYPE_SDWF_MSDUQ_RECFG_REQ = 0x27,
HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP = 0x28,
/* keep this last */
HTT_H2T_NUM_MSGS
@@ -11503,89 +11491,6 @@ PREPACK struct htt_h2t_sdwf_msduq_recfg_req {
((_var) |= ((_val) << HTT_H2T_SDWF_MSDUQ_RECFG_REQUEST_COOKIE_S)); \
} while (0)
/**
* @brief host -> target report MLO latency stats to FW periodically
*
* MSG_TYPE => HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP
*
* @details
*
* |31 24|23 16|15 8|7 0|
* |----------------+----------------+----------------+----------------|
* | avg latency ms | vdev id | msg type |
* |----------------+----------------+----------------+----------------|
* | num of tx MSDUs | avg latency jitter ms |
* |-------------------------------------------------------------------|
*
* @details
* struct htt_h2t_mlo_latency_stats:
*
* The message is interpreted as follows:
* dword0 - b'7:0 - msg_type: Identifies mlo latency stats to fw
* This will be set to 0x28
* (HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP)
* b'15:8 - vdev id : Indicate which vdev in the pdev is chosen
* as primary
* b'31:16 - avg latency ms: Indicate average MLO latency in a period
* dword1 - b'15:0 - min jitter ms: Indicate avg jitter of MLO latency in a
* period
* b'31:16 - num of tx packet : Indicate how many MSDUs are sent in a
* period
*/
/* HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_RESP */
PREPACK struct htt_h2t_mlo_latency_stats {
A_UINT32 msg_type: 8, /* bits 7:0 */
vdev_id: 8, /* bits 15:8 */
avg_latency_ms: 16; /* bits 31:16 */
A_UINT32 avg_jitter_ms: 16, /* bits 15:0 */
num_of_tx_pkt: 16; /* bits 31:16 */
} POSTPACK;
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_M 0x0000FF00
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_S 8
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_GET(_var) \
(((_var) & HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_M) >> \
HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_S)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID, _val); \
((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_VDEV_ID_S)); \
} while (0)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_M 0xFFFF0000
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_S 16
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_GET(_var) \
(((_var) & HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_M) >> \
HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_S)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS, _val); \
((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_LATENCY_MS_S)); \
} while (0)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_M 0x0000FFFF
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_S 0
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_GET(_var) \
(((_var) & HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_M) >> \
HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_S)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS, _val); \
((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_AVG_JITTER_MS_S)); \
} while (0)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_M 0xFFFF0000
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_S 16
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_GET(_var) \
(((_var) & HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_M) >> \
HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_S)
#define HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT, _val); \
((_var) |= ((_val) << HTT_H2T_MSG_TYPE_MLO_LATENCY_STATS_NUM_OF_TX_PKT_S)); \
} while (0)
/*=== target -> host messages ===============================================*/
@@ -11660,7 +11565,6 @@ enum htt_t2h_msg_type {
HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a,
HTT_T2H_MSG_TYPE_TX_LCE_SUPER_RULE_SETUP_DONE = 0x3b,
HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND = 0x3c,
HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ = 0x3d,
HTT_T2H_MSG_TYPE_TEST,
@@ -14263,11 +14167,11 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* | VALID_MASK |(4bits) | SET_NUM | HW peer ID / AST index |
* | (8bits) | | (4bits) | |
* |-----------------+--------+--+--+--+--------------------------------------|
* | RESERVED |C|E |O | | |
* | (12bits) |I|A |A |NH| on-Chip PMAC_RXPCU AST index |
* | |V|V |V | | |
* | RESERVED |E |O | | |
* | (13bits) |A |A |NH| on-Chip PMAC_RXPCU AST index |
* | |V |V | | |
* |-----------------+--------------------+-----------------------------------|
* | HTT_MSDU_IDX_ | CLASSIFY_INFO_IDX | |
* | HTT_MSDU_IDX_ | RESERVED | |
* | VALID_MASK_EXT | (8bits) | EXT AST index |
* | (8bits) | | |
* |-----------------+--------------------+-----------------------------------|
@@ -14277,13 +14181,11 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* |--------------------------------------------------------------------------|
*
* Where:
* CIV = CLASSIFY_INFO_IDX_VALID flag, for CLASSIFY_INFO_IDX
* EAV = EXT_AST_VALID flag, for "EXT AST index"
* OAV = ONCHIP_AST_VALID flag, for "on-Chip PMAC_RXPCU AST index"
* NH = Next Hop
* The following field definitions describe the format of the rx peer map v3
* messages sent from the target to the host.
* dword 0:
* - MSG_TYPE
* Bits 7:0
* Purpose: identifies this as a peer map v3 message
@@ -14294,12 +14196,10 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* - SW_PEER_ID
* Bits 31:16
* Purpose: The peer ID (index) that WAL has allocated for this peer.
* dword 1:
* - MAC_ADDR_L32
* Bits 31:0
* Purpose: Identifies which peer node the peer ID is for.
* Value: lower 4 bytes of peer node's MAC address
* dword 2:
* - MAC_ADDR_U16
* Bits 15:0
* Purpose: Identifies which peer node the peer ID is for.
@@ -14308,7 +14208,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* Bits 31:16
* Purpose: The multicast peer ID (index)
* Value: set to HTT_INVALID_PEER if not valid
* dword 3:
* - HW_PEER_ID / AST_INDEX
* Bits 15:0
* Purpose: Identifies the HW peer ID corresponding to the peer MAC
@@ -14328,7 +14227,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* - HTT_MSDU_IDX_VALID_MASK
* Bits 31:24
* Purpose: Shows MSDU indexes valid mask for AST_INDEX
* dword 4:
* - ONCHIP_AST_IDX / RESERVED
* Bits 15:0
* Purpose: This field is valid only when split AST feature is enabled.
@@ -14336,38 +14234,28 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* If valid, identifies the HW peer ID corresponding to the peer MAC
* address, this ast_idx is used for LMAC modules for RXPCU.
* - NEXT_HOP
* Bit 16
* Bits 16
* Purpose: Flag indicates next_hop AST entry used for WDS
* (Wireless Distribution System).
* - ONCHIP_AST_VALID
* Bit 17
* Bits 17
* Purpose: Flag indicates valid data behind of the ONCHIP_AST_IDX field
* - EXT_AST_VALID
* Bit 18
* Bits 18
* Purpose: Flag indicates valid data behind of the EXT_AST_INDEX field
* - CLASSIFY_INFO_IDX_VALID
* Bit 19
* Purpose: If set, indicates that the CLASSIFY_INFO_IDX field is valid;
* else, ignore CLASSIFY_INFO_IDX
* dword 5:
* - EXT_AST_INDEX
* Bits 15:0
* Purpose: This field describes Extended AST index
* Valid if EXT_AST_VALID flag set
* - CLASSIFY_INFO_IDX
* Bits 23:16
* Purpose: assists TCL-L Block in Boron family of chips to
* start finding the flow from the corresponding
* entry in the FLOW LOOK UP TABLE
* - HTT_MSDU_IDX_VALID_MASK_EXT
* Bits 31:24
* Purpose: Shows MSDU indexes valid mask for EXT_AST_INDEX
*/
/* dword 0 */
#define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00
#define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8
#define HTT_RX_PEER_MAP_V3_SW_PEER_ID_M 0xffff0000
#define HTT_RX_PEER_MAP_V3_SW_PEER_ID_S 16
#define HTT_RX_PEER_MAP_V3_VDEV_ID_M 0x0000ff00
#define HTT_RX_PEER_MAP_V3_VDEV_ID_S 8
/* dword 1 */
#define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_M 0xffffffff
#define HTT_RX_PEER_MAP_V3_MAC_ADDR_L32_S 0
@@ -14377,30 +14265,26 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
#define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_M 0xffff0000
#define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_S 16
/* dword 3 */
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_M 0xff000000
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_S 24
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_M 0x000f0000
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_S 16
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_S 0
/* dword 4 */
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_M 0x00080000
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_S 19
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M 0x00040000
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S 18
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_M 0x00020000
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_S 17
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_M 0x00010000
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_S 16
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_S 0
/* dword 5 */
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_M 0x00ff0000
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_S 16
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M 0xff000000
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S 24
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M 0x0000ffff
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S 0
#define HTT_RX_PEER_MAP_V3_VDEV_ID_SET(word, value) \
do { \
@@ -14482,14 +14366,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_GET(word) \
(((word) & HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_S)
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG, value); \
(word) |= (value) << HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_S; \
} while (0)
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_GET(word) \
(((word) & HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_M) >> HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_S)
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_EXT_AST_IDX, value); \
@@ -14498,14 +14374,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_GET(word) \
(((word) & HTT_RX_PEER_MAP_V3_EXT_AST_IDX_M) >> HTT_RX_PEER_MAP_V3_EXT_AST_IDX_S)
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX, value); \
(word) |= (value) << HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_S; \
} while (0)
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_GET(word) \
(((word) & HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_M) >> HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_S)
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST, value); \
@@ -14514,19 +14382,17 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_GET(word) \
(((word) & HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_M) >> HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_S)
#define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */
#define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_VALID_FLAG_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */
#define HTT_RX_PEER_MAP_V3_CLASSIFY_INFO_IDX_OFFSET 20 /* bytes */
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */
#define HTT_RX_PEER_MAP_V3_MAC_ADDR_OFFSET 4 /* bytes */
#define HTT_RX_PEER_MAP_V3_MULTICAST_SW_PEER_ID_OFFSET 8 /* bytes */
#define HTT_RX_PEER_MAP_V3_HW_PEER_ID_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_CACHE_SET_NUM_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_AST_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V3_ON_CHIP_PMAC_RXPCU_AST_IDX_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_NEXT_HOP_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_ONCHIP_AST_VALID_FLAG_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_EXT_AST_VALID_FLAG_OFFSET 16 /* bytes */
#define HTT_RX_PEER_MAP_V3_EXT_AST_IDX_OFFSET 20 /* bytes */
#define HTT_RX_PEER_MAP_V3_MSDU_IDX_VM_EXT_AST_OFFSET 20 /* bytes */
#define HTT_RX_PEER_MAP_V3_BYTES 32
@@ -14663,41 +14529,40 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* with, so that the host can use that MLO peer ID to determine which peer
* transmitted the rx frame.
*
* |31 |29 27|26|25|24|23 20|19 17|16|15 8|7 0|
* |--------------------------------------------------------------------------|
* |RSVD | PRC | NUMLINK| MLO peer ID | msg type |
* |--------------------------------------------------------------------------|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
* |--------------------------------------------------------------------------|
* | RSVD_25_31 |CV| CLASS_INFO_IDX | MAC addr 5 | MAC addr 4 |
* |--------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 |
* |--------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 |
* |--------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 |
* |--------------------------------------------------------------------------|
* |RSVD |
* |--------------------------------------------------------------------------|
* |RSVD |
* |--------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |--------------------------------------------------------------------------|
* |RSVD_27_31 | CHIPID | VDEVID | SW peer ID |
* |--------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |--------------------------------------------------------------------------|
* |RSVD_27_31 | CHIPID | VDEVID | SW peer ID |
* |--------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |--------------------------------------------------------------------------|
* |RSVD_27_31 | CHIPID | VDEVID | SW peer ID |
* |--------------------------------------------------------------------------|
* |31 |29 27|26 24|23 20|19 17|16|15 8|7 0|
* |-------------------------------------------------------------------------|
* |RSVD | PRC |NUMLINK| MLO peer ID | msg type |
* |-------------------------------------------------------------------------|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
* |-------------------------------------------------------------------------|
* | RSVD_16_31 | MAC addr 5 | MAC addr 4 |
* |-------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 0 |
* |-------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 1 |
* |-------------------------------------------------------------------------|
* |CACHE_SET_NUM| TIDMASK |CHIPID|V| Primary TCL AST IDX 2 |
* |-------------------------------------------------------------------------|
* |RSVD |
* |-------------------------------------------------------------------------|
* |RSVD |
* |-------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |-------------------------------------------------------------------------|
* |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
* |-------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |-------------------------------------------------------------------------|
* |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
* |-------------------------------------------------------------------------|
* | htt_tlv_hdr_t |
* |-------------------------------------------------------------------------|
* |RSVD_27_31 |CHIPID| VDEVID | SW peer ID |
* |-------------------------------------------------------------------------|
*
* Where:
* PRC - Primary REO CHIPID - 3 Bits Bit24,25,26
* NUMLINK - NUM_LOGICAL_LINKS - 3 Bits Bit27,28,29
* CV - CLASSIFY_INFO_IDX_VALID - 1 Bit Bit24
* V (valid) - 1 Bit Bit17
* CHIPID - 3 Bits
* TIDMASK - 8 Bits
@@ -14737,16 +14602,6 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
* Purpose: Identifies which peer node the peer ID is for.
* Value: upper 2 bytes of peer node's MAC address
*
* - CLASS_INFO_IDX
* Bits 23:16
* Purpose: Classify info index assists TCL-L Block in certain families of
* WLAN chips to start finding the flow from the corresponding
* entry in the FLOW LOOK UP TABLE in MLO case
* - CV (CLASS_INFO_IDX_VALID)
* Bit 24
* Purpose: if set indicates that the CLASS_INFO_IDX is valid,
* else ignore the value reported
*
* - PRIMARY_TCL_AST_IDX
* Bits 15:0
* Purpose: Primary TCL AST index for this peer.
@@ -14818,11 +14673,6 @@ typedef enum {
#define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_M 0x0000ffff
#define HTT_RX_MLO_PEER_MAP_MAC_ADDR_U16_S 0
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M 0x00ff0000
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S 16
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M 0x01000000
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S 24
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_M 0x0000ffff
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_S 0
#define HTT_RX_MLO_PEER_MAP_AST_INDEX_VALID_FLAG_M 0x00010000
@@ -14871,30 +14721,6 @@ typedef enum {
#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \
(((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S)
#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID, value); \
(word) |= (value) << HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S; \
} while (0)
#define HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_GET(word) \
(((word) & HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_M) >> HTT_RX_MLO_PEER_PRIMARY_REO_CHIP_ID_S)
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX, value); \
(word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S; \
} while (0)
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_GET(word) \
(((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_S)
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG, value); \
(word) |= (value) << HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S; \
} while (0)
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_GET(word) \
(((word) & HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_M) >> HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_S)
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX, value); \
@@ -14977,8 +14803,6 @@ typedef enum {
#define HTT_RX_MLO_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_OFFSET 8 /* bytes */
#define HTT_RX_MLO_PEER_MAP_CLASSIFY_INFO_IDX_VALID_FLAG_OFFSET 8 /* bytes */
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_0_OFFSET 12 /* bytes */
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_1_OFFSET 16 /* bytes */
#define HTT_RX_MLO_PEER_MAP_PRIMARY_AST_INDEX_2_OFFSET 20 /* bytes */
@@ -15462,7 +15286,7 @@ typedef enum {
} while (0)
#define HTT_RX_ADDBA_EXTN_WIN_SIZE_GET(word) \
(((word) & HTT_RX_ADDBA_EXTN_WIN_SIZE_M) >> HTT_RX_ADDBA_EXTN_WIN_SIZE_S)
(((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S)
#define HTT_RX_ADDBA_EXTN_BYTES 8
@@ -23424,73 +23248,6 @@ PREPACK struct htt_t2h_sdwf_msduq_cfg_ind {
((_var) |= ((_val) << HTT_T2H_MSG_TYPE_SDWF_MSDUQ_CFG_IND_REQUEST_COOKIE_S)); \
} while (0)
/**
* @brief target -> host request for MLO latency stats
*
* MSG_TYPE => HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ
*
* @details
*
* |31 24|23 16| 15 |14 8|7 0|
* |----------------+----------------+------+---------+----------------|
* | periodic interval |enable| vdev id | msg type |
* |-------------------------------------------------------------------|
*
* @details
* struct htt_t2h_mlo_latency_req_t:
*
* The message is interpreted as follows:
* dword0 - b'7:0 - msg_type: Identifies a request for MLO latency stats
* This will be set to 0x3d
* (HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ)
* b'14:8 - vdev id : Indicate which vdev in the pdev is chosen
* as primary
* b'15 - enable: Indicate if request of MLO latency stats is
* enabled
* b'31:16 - periodic interval: Indicate the interval in ms of
* reporting MLO latency stats
*/
/* HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ */
PREPACK struct htt_t2h_mlo_latency_req_t {
A_UINT32 msg_type: 8, /* bits 7:0 */
vdev_id: 7, /* bits 14:8 */
enable: 1, /* bits 15 */
periodic_intvl: 16; /* bits 31:16 */
} POSTPACK;
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_M 0x00007F00
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_S 8
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_GET(_var) \
(((_var) & HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_M) >> \
HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_S)
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID, _val); \
((_var) |= ((_val) << HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_VDEV_ID_S)); \
} while (0)
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_M 0x00008000
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_S 15
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_GET(_var) \
(((_var) & HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_M) >> \
HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_S)
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE, _val); \
((_var) |= ((_val) << HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_ENABLE_S)); \
} while (0)
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_M 0xFFFF0000
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_S 16
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_GET(_var) \
(((_var) & HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_M) >> \
HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_S)
#define HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL, _val); \
((_var) |= ((_val) << HTT_T2H_MSG_TYPE_MLO_LATENCY_REQ_PERIODIC_INTVL_S)); \
} while (0)
#endif

4
qcom/opensource/wlan/fw-api/fw/htt_ppdu_stats.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -922,8 +922,6 @@ typedef struct {
* part of existing DL/UL data sequence
*/
A_UINT32 is_combined_ul_bsrp_trigger;
/* Flag to indicate if the channel chosen is 320_1 / 320_2 */
A_UINT32 chan_type_320mhz;
} htt_ppdu_stats_common_tlv;
#define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff

727
qcom/opensource/wlan/fw-api/fw/htt_stats.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -786,57 +786,6 @@ enum htt_dbg_ext_stats_type {
*/
HTT_DBG_EXT_STATS_TX_VDEV_NSS = 69,
/** HTT_DBG_EXT_STATS_PDEV_RTT_DELAY
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_pdev_rtt_delay_tlv
*/
HTT_DBG_EXT_STATS_PDEV_RTT_DELAY = 70,
/** HTT_DBG_EXT_STATS_PDEV_SPECTRAL
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_pdev_spectral_tlv
*/
HTT_DBG_EXT_STATS_PDEV_SPECTRAL = 71,
/** HTT_DBG_EXT_STATS_PDEV_AOA
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_pdev_aoa_tlv
*/
HTT_DBG_EXT_STATS_PDEV_AOA = 72,
/** HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_pdev_ftm_tpccal_tlv
*/
HTT_DBG_EXT_STATS_PDEV_FTM_TPCCAL = 73,
/** HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_ELIGIBLE
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_pdev_ul_mumimo_grp_stats_tlv
* - htt_stats_pdev_ul_mumimo_denylist_stats_tlv
* - htt_stats_pdev_ul_mumimo_seq_term_stats_tlv
* - htt_stats_pdev_ul_mumimo_hist_ineligibility_tlv
*/
HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_ELIGIBLE = 74,
/** HTT_DBG_EXT_STATS_PAPRD_PB
* PARAMS:
* - No Params
* RESP MSG:
* - htt_stats_phy_paprd_pb_tlv
*/
HTT_DBG_EXT_STATS_PAPRD_PB = 75,
/* keep this last */
HTT_DBG_NUM_EXT_STATS = 256,
@@ -1010,7 +959,6 @@ typedef enum {
#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5
#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10
#define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16
#define HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS 6
#define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250
typedef enum {
@@ -1233,13 +1181,6 @@ typedef struct {
A_UINT32 pdev_up_time_us_high;
/** count of ofdma sequences flushed */
A_UINT32 ofdma_seq_flush;
/* bytes (size of MPDUs) transmitted */
struct {
/* lower 32 bits of the tx_bytes value */
A_UINT32 low_32;
/* upper 32 bits of the tx_bytes value */
A_UINT32 high_32;
} bytes_sent;
} htt_stats_tx_pdev_cmn_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_tx_pdev_cmn_tlv htt_tx_pdev_stats_cmn_tlv;
@@ -2025,22 +1966,6 @@ typedef htt_stats_peer_stats_cmn_tlv htt_peer_stats_cmn_tlv;
#define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff
#define HTT_PEER_DETAILS_SRC_INFO_S 0
#define HTT_PEER_DETAILS_PEER_PS_ENTRY_M 0x000000ff
#define HTT_PEER_DETAILS_PEER_PS_ENTRY_S 0
#define HTT_PEER_DETAILS_PEER_PS_EXIT_M 0x0000ff00
#define HTT_PEER_DETAILS_PEER_PS_EXIT_S 8
#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_M 0x00ff0000
#define HTT_PEER_DETAILS_PEER_PSPOLL_TRIGGER_S 16
#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_M 0xff000000
#define HTT_PEER_DETAILS_PEER_UAPSD_TRIGGER_S 24
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_M 0x000003ff
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_0_S 0
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_M 0x000ffc00
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_1_S 10
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_M 0x3ff00000
#define HTT_PEER_DETAILS_PEER_PS_HISTOGRAM_2_S 20
#define HTT_PEER_DETAILS_SET(word, httsym, val) \
do { \
@@ -2086,34 +2011,6 @@ typedef struct {
rsvd1 : 20; /* [31:12] */
};
};
/* Dword 10 */
union {
A_UINT32 word__peer_ps_entry__peer_ps_exit__peer_pspoll_trigger_received__peer_uapsd_trigger_received;
struct {
A_UINT32 peer_ps_entry : 8, /* [7:0] */
peer_ps_exit : 8, /* [15:8] */
peer_pspoll_trigger_received : 8, /* [23:16] */
peer_uapsd_trigger_received : 8; /* [31:24] */
};
};
/* Dword 11 */
union {
A_UINT32 word__peer_ps_histogram_0__peer_ps_histogram_1__peer_ps_histogram_2;
struct {
/*
* This word holds 3 10-bit histograms of power-save durations:
* bits 9:0 - count of durations < 200 ms
* bits 19:10 - count of durations between 200 to 500 ms
* bits 29:20 - count of durations > 500 ms
*/
A_UINT32 peer_ps_histogram_0 : 10, /* [9:0] */
peer_ps_histogram_1 : 10, /* [19:10] */
peer_ps_histogram_2 : 10, /* [29:20] */
rsvd2 : 2; /* [31:30] */
};
};
} htt_stats_peer_details_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_peer_details_tlv htt_peer_details_tlv;
@@ -2125,21 +2022,6 @@ typedef htt_stats_peer_details_tlv htt_peer_details_tlv;
#define HTT_STATS_PEER_DETAILS_SRC_INFO_GET(word) ((word >> 0) & 0xfff)
#define HTT_STATS_PEER_DETAILS_PEER_PS_ENTRY_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PS_ENTRY)
#define HTT_STATS_PEER_DETAILS_PEER_PS_EXIT_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PS_EXIT)
#define HTT_STATS_PEER_DETAILS_PEER_PSPOLL_TRIGGER_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PSPOLL_TRIGGER)
#define HTT_STATS_PEER_DETAILS_PEER_UAPSD_TRIGGER_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_UAPSD_TRIGGER)
#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_0_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_0)
#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_1_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_1)
#define HTT_STATS_PEER_DETAILS_PEER_PS_HISTOGRAM_2_GET(word) \
HTT_PEER_DETAILS_GET(word, PEER_PS_HISTOGRAM_2)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
A_UINT32 sw_peer_id;
@@ -2937,11 +2819,6 @@ typedef enum {
HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE,
HTT_TX_MUMIMO_GRP_INVALID,
HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS,
HTT_TX_MUMIMO_GRP_INVALID_GRP,
HTT_TX_MUMIMO_GRP_INVALID_TOTAL_NSS_LESS_THAN_GROUP_SIZE,
HTT_TX_MUMIMO_GRP_INSUFFICIENT_CANDIDATES_UL_MU_1SS_RATE,
HTT_TX_MUMIMO_GRP_MU_GRP_NOT_NEEDED,
HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE,
} htt_tx_mumimo_grp_invalid_reason_code_stats;
@@ -4849,19 +4726,6 @@ typedef struct {
A_UINT32 g1_compl_fail;
A_UINT32 g2_success;
A_UINT32 g2_compl_fail;
/* enqueue */
A_UINT32 m1_enq_success;
A_UINT32 m1_enq_fail;
A_UINT32 m2_enq_success;
A_UINT32 m2_enq_fail;
A_UINT32 m3_enq_success;
A_UINT32 m3_enq_fail;
A_UINT32 m4_enq_success;
A_UINT32 m4_enq_fail;
A_UINT32 g1_enq_success;
A_UINT32 g1_enq_fail;
A_UINT32 g2_enq_success;
A_UINT32 g2_enq_fail;
} htt_stats_tx_de_eapol_packets_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_tx_de_eapol_packets_tlv htt_tx_de_eapol_packets_stats_tlv;
@@ -5981,8 +5845,6 @@ typedef struct {
/** tx_ppdu_dur_hist:
* Tx PPDU duration histogram, which holds the tx duration of PPDUs
* under histogram bins of interval 250us
*
* Note that this histogram is extended by tx_ppdu_dur_hist_ext[] below.
*/
A_UINT32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS];
A_UINT32 tx_success_time_us_low;
@@ -5996,11 +5858,6 @@ typedef struct {
* OFDMA PPDUs under histogram bins of interval 250us
*/
A_UINT32 tx_ofdma_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS];
/* tx_ppdu_dur_hist_ext:
* This array extends the PPDU duration histogram contained in the
* tx_ppdu_dur_hist[] array from 4 ms to 5.5 ms.
*/
A_UINT32 tx_ppdu_dur_hist_ext[HTT_PDEV_STATS_PPDU_DUR_HIST_EXT_BINS];
} htt_stats_tx_pdev_ppdu_dur_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_tx_pdev_ppdu_dur_tlv htt_tx_pdev_ppdu_dur_stats_tlv;
@@ -7021,16 +6878,6 @@ typedef struct {
A_UINT32 rx_flush_cnt;
/** Num rx recovery */
A_UINT32 rx_recovery_reset_cnt;
/* Num prom filter disable */
A_UINT32 rx_lwm_prom_filter_dis;
/* Num prom filter enable */
A_UINT32 rx_hwm_prom_filter_en;
struct {
/* lower 32 bits of the rx_bytes value */
A_UINT32 low_32;
/* upper 32 bits of the rx_bytes value */
A_UINT32 high_32;
} bytes_received;
} htt_stats_rx_pdev_fw_stats_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_rx_pdev_fw_stats_tlv htt_rx_pdev_fw_stats_tlv;
@@ -7665,15 +7512,6 @@ typedef struct {
A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
/** number of streams present in uploaded CV Correlation results buffer */
A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
/** Total number of times lookahead sounding done for DL MU */
A_UINT32 lookahead_sounding_dl_cnt;
/** Total number of times lookahead sounding done for DL MU based on number of users */
A_UINT32 lookahead_snd_dl_num_users[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS];
/** Total number of times lookahead sounding done for UL MU */
A_UINT32 lookahead_sounding_ul_cnt;
/** Total number of times lookahead sounding done for UL MU based on number of users */
A_UINT32 lookahead_snd_ul_num_users[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS];
} htt_stats_tx_sounding_stats_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_tx_sounding_stats_tlv htt_tx_sounding_stats_tlv;
@@ -8210,8 +8048,6 @@ typedef struct {
A_UINT32 ru_type; /* refer to htt_stats_ru_type enum */
htt_tx_rate_stats_t per_ru[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS];
htt_tx_rate_stats_t per_tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS];
} htt_stats_per_rate_stats_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_per_rate_stats_tlv htt_tx_rate_stats_per_tlv;
@@ -9052,486 +8888,6 @@ typedef struct {
typedef htt_stats_pktlog_and_htt_ring_stats_tlv
htt_pktlog_and_htt_ring_stats_tlv;
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_SPECTRAL
* TLV_TAGS:
* HTT_STATS_PDEV_SPECTRAL_TAG
*/
#define HTT_STATS_PDEV_SPECTRAL_PCFG_MAX_DET (3)
#define HTT_STATS_PDEV_SPECTRAL_MAX_PCSS_RING_FOR_IPC (3)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
A_UINT32 dbg_num_buf;
A_UINT32 dbg_num_events;
/* HOST_ring_HI */
A_UINT32 host_head_idx;
A_UINT32 host_tail_idx;
A_UINT32 host_shadow_tail_idx;
/* SHADOW_ring_HI */
A_UINT32 in_ring_head_idx;
A_UINT32 in_ring_tail_idx;
A_UINT32 in_ring_shadow_tail_idx;
A_UINT32 in_ring_shadow_head_idx;
/* OUT_ring_HI */
A_UINT32 out_ring_head_idx;
A_UINT32 out_ring_tail_idx;
A_UINT32 out_ring_shadow_tail_idx;
A_UINT32 out_ring_shadow_head_idx;
/* IPC_ring MAX_PCSS_RING_FOR_IPC */
struct {
A_UINT32 head_idx;
A_UINT32 tail_idx;
A_UINT32 shadow_tail_idx;
A_UINT32 shadow_head_idx;
} ipc_rings[HTT_STATS_PDEV_SPECTRAL_MAX_PCSS_RING_FOR_IPC];
/* VREG Counters */
struct {
A_UINT32 scan_priority;
A_UINT32 scan_count;
A_UINT32 scan_period;
A_UINT32 scan_chn_mask;
A_UINT32 scan_ena;
A_UINT32 scan_update_mask;
A_UINT32 scan_ready_intrpt;
A_UINT32 scans_performed;
A_UINT32 intrpts_sent;
A_UINT32 scan_pending_count;
A_UINT32 num_pcss_elem_zero;
A_UINT32 num_in_elem_zero;
A_UINT32 num_out_elem_zero;
A_UINT32 num_elem_moved;
} pcfg_stats_det[HTT_STATS_PDEV_SPECTRAL_PCFG_MAX_DET];
struct {
A_UINT32 scan_no_ipc_buf_avail;
A_UINT32 agile_scan_no_ipc_buf_avail;
A_UINT32 scan_FFT_discard_count;
A_UINT32 scan_recapture_FFT_discard_count;
A_UINT32 scan_recapture_count;
} pcfg_stats_vreg;
} htt_stats_pdev_spectral_tlv;
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_RTT_DELAY
* TLV_TAGS:
* HTT_STATS_PDEV_RTT_DELAY_TAG
*/
#define HTT_STATS_PDEV_RTT_DELAY_NUM_INSTANCES (2)
/* HTT_STATS_PDEV_RTT_DELAY_PKT_BW:
* 0 -> 20 MHz
* 1 -> 40 MHz
* 2 -> 80 MHz
* 3 -> 160 MHz
* 4 -> 320 MHz
* 5: reserved
*/
#define HTT_STATS_PDEV_RTT_DELAY_PKT_BW (6)
/* HTT_STATS_PDEV_RTT_TX_RX_INSTANCES
* idx 0 -> Tx instance
* idx 1 -> Rx instance
*/
#define HTT_STATS_PDEV_RTT_TX_RX_INSTANCES (2)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
struct {
/* base_delay: picosecond units */
A_INT32 base_delay[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES][HTT_STATS_PDEV_RTT_DELAY_PKT_BW];
/* final_delay: picosecond units */
A_INT32 final_delay[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES][HTT_STATS_PDEV_RTT_DELAY_PKT_BW];
A_INT32 per_chan_bias[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES];
A_INT32 off_chan_bias[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES];
A_INT32 chan_bw_bias[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES];
A_UINT32 rtt_11mc_chain_idx[HTT_STATS_PDEV_RTT_TX_RX_INSTANCES];
A_UINT32 chan_freq; /* MHz units */
A_UINT32 bandwidth; /* MHz units */
A_UINT32 vreg_cache;
A_UINT32 rtt_11mc_vreg_set_cnt;
A_UINT32 cfr_vreg_set_cnt;
A_UINT32 cir_vreg_set_cnt;
A_UINT32 digital_block_status;
} rtt_delay[HTT_STATS_PDEV_RTT_DELAY_NUM_INSTANCES];
} htt_stats_pdev_rtt_delay_tlv;
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_AOA
* TLV_TAGS:
* HTT_STATS_PDEV_AOA_TAG
*/
#define HTT_STATS_PDEV_AOA_MAX_HISTOGRAM (10)
#define HTT_STATS_PDEV_AOA_MAX_CHAINS (4)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
A_UINT32 gain_idx[HTT_STATS_PDEV_AOA_MAX_HISTOGRAM];
/* gain table element values:
* 0 -> default gain
* 1 -> low gain
* 2 -> very low gain
*/
A_UINT32 gain_table[HTT_STATS_PDEV_AOA_MAX_HISTOGRAM];
A_UINT32 phase_calculated[HTT_STATS_PDEV_AOA_MAX_HISTOGRAM][HTT_STATS_PDEV_AOA_MAX_CHAINS];
A_INT32 phase_in_degree[HTT_STATS_PDEV_AOA_MAX_HISTOGRAM][HTT_STATS_PDEV_AOA_MAX_CHAINS];
} htt_stats_pdev_aoa_tlv;
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_ULMUMIMO_ELIGIBLE
* TLV_TAGS:
* HTT_STATS_PDEV_UL_MUMIMO_GRP_STATS_TAG
* HTT_STATS_PDEV_UL_MUMIMO_DENYLIST_STATS_TAG
* HTT_STATS_PDEV_UL_MUMIMO_SEQ_TERM_STATS_TAG
* HTT_STATS_PDEV_UL_MUMIMO_HIST_INELIGIBILITY_TAG
*/
typedef enum {
HTT_STATS_CANDIDATE_MU_NOT_COMPATIBLE = 1,
HTT_STATS_CANDIDATE_SKIP_NR_INDEX,
HTT_STATS_CANDIDATE_SKIP_BASIC_CHECKS_INELIGIBLE,
HTT_STATS_CANDIDATE_SKIP_ZERO_NSS,
HTT_STATS_CANDIDATE_SKIP_MCS_THRESHOLD_LIMIT,
HTT_STATS_CANDIDATE_SKIP_POWER_IMBALANCED,
HTT_STATS_CANDIDATE_SKIP_NULL_MU_RC,
HTT_STATS_CANDIDATE_SKIP_CV_CORR_SKIP_PEER,
HTT_STATS_CANDIDATE_SKIP_SEND_BAR_SET_FOR_AC_MUMIMO,
HTT_STATS_CANDIDATE_SKIP_REASON_MAX
} htt_stats_candidate_sched_compatible_code;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Current Pdev id */
A_UINT32 pdev_id;
/* Group eligibility count */
A_UINT32 mu_grp_eligible[HTT_STATS_MAX_MUMIMO_GRP_SZ];
/* Group ineligibility */
A_UINT32 mu_grp_ineligible[HTT_STATS_MAX_MUMIMO_GRP_SZ];
/* Group Invalid reason */
A_UINT32 mu_grp_invalid[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS];
/* mu_grp_candidate_skip:
* Sched_compatibility reason codes as listed by
* htt_stats_candidate_sched_compatible code
*/
A_UINT32 mu_grp_candidate_skip
[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]
[HTT_STATS_CANDIDATE_SKIP_REASON_MAX];
/* Group eligibility count for 1SS grouping */
A_UINT32 mu_grp_eligible_1ss[HTT_STATS_MAX_MUMIMO_GRP_SZ];
/* Group ineligibility fpr 1SS grouping */
A_UINT32 mu_grp_ineligible_1ss[HTT_STATS_MAX_MUMIMO_GRP_SZ];
/* Group Invalid reason for 1SS grouping */
A_UINT32 mu_grp_invalid_1ss[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS];
/* Sched_compatibility reason code for 1SS grouping */
A_UINT32 mu_grp_candidate_skip_1ss
[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]
[HTT_STATS_CANDIDATE_SKIP_REASON_MAX];
} htt_stats_pdev_ulmumimo_grp_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Num of times peer denylisted for MU-MIMO transmission */
A_UINT32 num_peer_denylist_cnt;
/* Num of times peer denylisted due to trigger bitmap failure */
A_UINT32 trig_bitmap_fail_cnt;
/* Num of times peer denylisted due to trigger consecutive failure */
A_UINT32 trig_consecutive_fail_cnt;
} htt_stats_pdev_ulmumimo_denylist_stats_tlv;
#define HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM 10
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Num of times seq terminated for MU-MIMO transmission */
A_UINT32 num_terminate_seq;
/* Num of sequences terminated due to low qdepth */
A_UINT32 num_terminate_low_qdepth;
/* Number of sequences terminated due to sequence inefficient */
A_UINT32 num_terminate_seq_inefficient;
/* Histogram of sequence inefficiency */
A_UINT32 hist_seq_efficiency[HTT_STATS_SEQ_EFFICIENCY_HISTOGRAM];
} htt_stats_pdev_ulmumimo_seq_term_stats_tlv;
#define HTT_STATS_MAX_ULMUMIMO_TRIGGERS 6
#define HTT_STATS_TXOP_HISTOGRAM_BINS 24
#define HTT_STATS_ULMUMIMO_DUR_INTERVAL_US 500
#define HTT_STATS_ULMUMIMO_MIN_PPDU_DUR_US 1000
#define HTT_STATS_MAX_PPDU_DURATION_BINS 10
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Number of ULMUMIMO triggers */
A_UINT32 num_triggers[HTT_STATS_MAX_ULMUMIMO_TRIGGERS];
/* Txop duration history from 0 to 12 ms with interval of 500us */
A_UINT32 txop_history [HTT_STATS_TXOP_HISTOGRAM_BINS];
/* ppdu_duration_hist:
* PPDU Duration History (histogram)
* Num PPDUs from 1 to 6
* 0 to 6 ms with interval of 500us
*/
A_UINT32 ppdu_duration_hist
[HTT_STATS_MAX_ULMUMIMO_TRIGGERS][HTT_STATS_MAX_PPDU_DURATION_BINS];
/* Ineligible Count for ULMUMIMO based on avg qdepth and txtime criteria */
A_UINT32 ineligible_count;
/* history_ineligibility:
* History based ineligibility counter for ULMUMIMO.
* Checks for 8 eligible instances of ULMUMIMO in the past 32 instances.
*/
A_UINT32 history_ineligibility;
} htt_stats_pdev_ulmumimo_hist_ineligibility_tlv;
/* RTT VREG MASK */
#define HTT_STATS_RTT_CHAN_CAPTURE_MASK 0x00000001
#define HTT_STATS_RTT_HW_FAC_MASK 0x00000002
#define HTT_STATS_RTT_11AZ_DELAYED_FEEDBACK_MASK 0x00000004
#define HTT_STATS_RTT_11AZ_DROP_FIRST_LMR_MASK 0x00000008
#define HTT_STATS_RTT_CAPTURE_CFR_MASK 0x00000010
#define HTT_STATS_RTT_CAPTURE_CIR_MASK 0x00000020
#define HTT_STATS_RTT_DET0_REPETITIVE_CHAN_CAPTURE_EN_MASK 0x00000040
#define HTT_STATS_RTT_CAPTURE_SPARE_1_MASK 0x00000080
#define HTT_STATS_RTT_CAPTURE_SPARE_2_MASK 0x00000100
/* RTT Digital block compensation mask */
#define HTT_STATS_RTT_TX_IQCORR_COMP_MASK 0x00000001
#define HTT_STATS_RTT_TX_PREEMP_FIR_COMP_MASK 0x00000002
#define HTT_STATS_RTT_LPC_FILTER_COMP_MASK 0x00000004
#define HTT_STATS_RTT_SM_CFR_COMP_MASK 0x00000008
#define HTT_STATS_RTT_CAL_PDC_DIS_COMP_MASK 0x00000010
#define HTT_STATS_RTT_CAL_PAPRD_COMP_MASK 0x00000020
#define HTT_STATS_RTT_CAL_RXCORR_IQCORR_COMP_MASK 0x00000040
#define HTT_STATS_RTT_CAL_RXCORR_PHASE_COMP_MASK 0x00000080
#define HTT_STATS_RTT_PHYRF_ICI_CORR_COMP_MASK 0x00000100
#define HTT_STATS_RTT_VSRC_PRE_FIR_SEL_COMP_MASK 0x00000200
#define HTT_STATS_RTT_CVSRC_PRE_FIR_SEL2_COMP_MASK 0x00000400
#define HTT_STATS_RTT_CAL_ENABLE_GAINDEPCORR_COMP_MASK 0x00000800
#define HTT_STATS_RTT_CAL_DC_NOTCH_FILTER_COMP_MASK 0x00001000
#define HTT_STATS_RTT_CAL_DET_PATH_COMP_MASK 0x00002000
#define HTT_STATS_RTT_CAL_RXCORR_ADC_DC_COMP_MASK 0x00004000
#define HTT_STATS_RTT_CAL_RXCORR_ADC_GAIN_COMP_MASK 0x00008000
#define HTT_STATS_RTT_CAL_SPUR_FILTER_PRI_DET_COMP_MASK 0x00010000
#define HTT_STATS_RTT_CAL_SPUR_FILTER_PRI_COMP_MASK 0x00020000
#define HTT_STATS_TPCCAL_LAST_IDX_M 0x000000ff
#define HTT_STATS_TPCCAL_LAST_IDX_S 0
#define HTT_STATS_TPCCAL_LAST_IDX_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_LAST_IDX_M) >> \
HTT_STATS_TPCCAL_LAST_IDX_S)
#define HTT_STATS_TPCCAL_STATS_MEASPWR_M 0x0000ffff
#define HTT_STATS_TPCCAL_STATS_MEASPWR_S 0
#define HTT_STATS_TPCCAL_STATS_MEASPWR_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_STATS_MEASPWR_M) >> \
HTT_STATS_TPCCAL_STATS_MEASPWR_S)
#define HTT_STATS_TPCCAL_STATS_PDADC_M 0x000000ff
#define HTT_STATS_TPCCAL_STATS_PDADC_S 0
#define HTT_STATS_TPCCAL_STATS_PDADC_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_STATS_PDADC_M) >> \
HTT_STATS_TPCCAL_STATS_PDADC_S)
#define HTT_STATS_TPCCAL_STATS_CHANNEL_M 0x0000ffff
#define HTT_STATS_TPCCAL_STATS_CHANNEL_S 0
#define HTT_STATS_TPCCAL_STATS_CHANNEL_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_STATS_CHANNEL_M) >> \
HTT_STATS_TPCCAL_STATS_CHANNEL_S)
#define HTT_STATS_TPCCAL_STATS_CHAIN_M 0x00ff0000
#define HTT_STATS_TPCCAL_STATS_CHAIN_S 16
#define HTT_STATS_TPCCAL_STATS_CHAIN_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_STATS_CHAIN_M) >> \
HTT_STATS_TPCCAL_STATS_CHAIN_S)
#define HTT_STATS_TPCCAL_STATS_GAININDEX_M 0xff000000
#define HTT_STATS_TPCCAL_STATS_GAININDEX_S 24
#define HTT_STATS_TPCCAL_STATS_GAININDEX_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_STATS_GAININDEX_M) >> \
HTT_STATS_TPCCAL_STATS_GAININDEX_S)
#define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_M 0x0000ffff
#define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_S 0
#define HTT_STATS_TPCCAL_POSTPROC_CHANNEL_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_POSTPROC_CHANNEL_M) >> \
HTT_STATS_TPCCAL_POSTPROC_CHANNEL_S)
#define HTT_STATS_TPCCAL_POSTPROC_CHAIN_M 0x00ff0000
#define HTT_STATS_TPCCAL_POSTPROC_CHAIN_S 16
#define HTT_STATS_TPCCAL_POSTPROC_CHAIN_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_POSTPROC_CHAIN_M) >> \
HTT_STATS_TPCCAL_POSTPROC_CHAIN_S)
#define HTT_STATS_TPCCAL_POSTPROC_BAND_M 0xff000000
#define HTT_STATS_TPCCAL_POSTPROC_BAND_S 24
#define HTT_STATS_TPCCAL_POSTPROC_BAND_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_POSTPROC_BAND_M) >> \
HTT_STATS_TPCCAL_POSTPROC_BAND_S)
#define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M 0x000000ff
#define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S 0
#define HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_M) >> \
HTT_STATS_TPCCAL_POSTPROC_NUMGAIN_S)
#define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M 0x0000ff00
#define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S 8
#define HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_GET(_var) \
(((_var) & HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_M) >> \
HTT_STATS_TPCCAL_POSTPROC_CALDBSTATUS_S)
/* STATS_TYPE : HTT_DBG_EXT_PDEV_STATS_FTM_TPCCAL
* TLV_TAGS:
* - HTT_STATS_PDEV_FTM_TPCCAL_TAG
*/
#define HTT_MAX_TPCCAL_STATS 25
#define HTT_STATS_TPC_CAL_MAX_NUM_POINTS 64
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* dword__tpccal_last_idx:
* Hold the last updated index for circular buffer of tpccal
* BIT [7 : 0] :- tpcccal_last_idx
* BIT [31 : 8] :- rsvd1
*/
union {
A_UINT32 dword__tpccal_last_idx;
struct {
A_UINT32 tpccal_last_idx:8,
rsvd1:24;
};
};
/*
* Below tpccal_stats struct will have latest values of tpccal data
* of array size HTT_MAX_TPCCAL_STATS.
* If there have been fewer than HTT_MAX_TPCCAL_STATS TPC calibrations,
* the unused elements will be filled with 0x0 values.
*/
struct {
/*
* dword__measPwr:
* BIT [15 : 0] :- measPwr
* BIT [31 : 16] :- rsvd2
*/
union {
A_INT32 dword__measPwr;
struct {
A_INT32 measPwr:16, /* dBm units */
rsvd2:16;
};
};
/*
* dword__channel_chain_gainIndex:
* hold channel chain and gain index values
* BIT [15 : 0] :- channel
* BIT [23 : 16] :- chain
* BIT [24 : 31] :- gainIndex
*/
union {
A_UINT32 dword__channel_chain_gainIndex;
struct {
A_UINT32 channel:16, /* MHz units */
chain:8,
gainIndex:8;
};
};
/*
* dword__pdadc:
* BIT [7 : 0] :- pdadc
* BIT [31 : 8] :- rsvd3
*/
union {
A_UINT32 dword__pdadc;
struct {
A_UINT32 pdadc:8,
rsvd3:24;
};
};
} tpccal_stats[HTT_MAX_TPCCAL_STATS];
/*
* Below tpccal_stats_postproc struct will have required tpccal data
* for failures during postprocessing.
*/
struct {
/*
* calStatus can be intrepreted with the below values:
* TPCCAL_CALDATA (1 << 0)
* TPCCAL_CALINFO (1 << 1)
* TPCCAL_CALERROR (1 << 2)
* bits 6:4 - reserved
* TPCCAL_DONE_MASK (1 << 7)
* bits 15:8 - reserved
* TPCCALRSP_MISCFLAGS_CALERROR_GLUTS_NOT_FILLED (1 << 16)
* TPCCALRSP_MISCFLAGS_CALERROR_PLUT_NON_LINEAR (1 << 17)
* TPCCALRSP_MISCFLAGS_CALERROR_ATTEMPTS_EXCEEDED (1 << 18)
* bits 31:19 - reserved
*/
A_UINT32 calStatus;
/*
* The numgain field specifies how many of the
* HTT_STATS_TPC_CAL_MAX_NUM_POINTS elements in the below arrays
* contain valid data.
*/
A_INT32 measPwr[HTT_STATS_TPC_CAL_MAX_NUM_POINTS]; /* dBm units */
A_UINT32 pdadc[HTT_STATS_TPC_CAL_MAX_NUM_POINTS];
A_UINT32 gainIndex[HTT_STATS_TPC_CAL_MAX_NUM_POINTS];
/*
* dword__channel_chain_band:
* channel, chain, and band values
* BIT [15 : 0] :- channel
* BIT [23 : 16] :- chain
* BIT [31 : 24] :- band
*/
union {
A_UINT32 dword__channel_chain_band;
struct {
A_UINT32 channel:16, /* MHz units */
chain:8,
band:8; /* 0: 2GHz, 1: 5GHz, 2: 6GHz */
};
};
/*
* dword__numgain_caldbStatus:
* numgain and caldbstatus
* BIT [7 : 0] :- numgain
* BIT [15 : 8] :- caldbstatus
* BIT [31 : 16] :- rsvd4
*
* caldbStatus can be interpreted as below
* CALDB_COMPLETED = 0
* CALDB_SKIPPED = 1
* CALDB_INPROGRESS = 2
*/
union {
A_UINT32 dword__numgain_caldbStatus;
struct {
A_UINT32 numgain:8,
caldbStatus:8,
rsvd4:16;
};
};
} tpccal_stats_postproc;
} htt_stats_pdev_ftm_tpccal_tlv;
#define HTT_DLPAGER_STATS_MAX_HIST 10
#define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF
#define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0
@@ -10541,56 +9897,6 @@ typedef struct {
} htt_vdevs_txrx_stats_t;
#endif /* ATH_TARGET */
/* PAPRD and power boost stats and counters */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/** current pdev_id */
A_UINT32 pdev_id;
/** DPD and PowerBoost trigger count */
A_UINT32 total_dpd_cal_count;
A_UINT32 chan_change_dpd_cal_count;
A_UINT32 thermal_dpd_cal_count;
A_UINT32 recovery_dpd_cal_count;
A_UINT32 pb_cal_count;
/** DPD and PowerBoost Fail Count */
A_UINT32 total_dpd_fail_count;
A_UINT32 chan_change_dpd_fail_count;
A_UINT32 thermal_dpd_fail_count;
A_UINT32 recovery_dpd_fail_count;
A_UINT32 pb_fail_count;
/*
* DPD and Power Boost validity status
*
* BIT 0 - DPD_CAL_STATUS
* BIT 1 - PB_CAL_STATUS
*
* CAL_STATUS can be interpreted as below
* CAL_SUCCESS = 1
* CAL_FAIL = 0
*/
union {
A_UINT32 dpd_pb_validity_status;
struct {
A_UINT32 is_dpd_valid:1,
is_pb_valid:1,
rsvd:30;
};
};
/** Last DPD cal time in ms */
A_UINT32 last_dpd_cal_time;
/** Last Power Boost cal time in ms */
A_UINT32 last_pb_cal_time;
/** Power Boost gain per BW and MCS, in 0.25 dB units
* For example, a value of 2 represents a 0.5 dB gain.
*/
A_UINT32 power_boost_gain[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS];
} htt_stats_phy_paprd_pb_tlv;
typedef struct {
union {
A_UINT32 word32;
@@ -11802,37 +11108,8 @@ typedef struct {
* avg_chan_acc_lat_hist[6]: 1000 us <= channel access latency < 1500 us
* avg_chan_acc_lat_hist[7]: 1500 us <= channel access latency < 2000 us
* avg_chan_acc_lat_hist[8]: channel access latency is >= 2000 us
*/
*/
A_UINT32 avg_chan_acc_lat_hist[HTT_MAX_NUM_CHAN_ACC_LAT_INTR];
/** Num of instances where OFDMA NBinWB is selected over MU-MIMO */
A_UINT32 dl_ofdma_nbinwb_selected_over_mu_mimo[HTT_NUM_AC_WMM];
/** Num of instances where OFDMA NBinWB is selected in standalone */
A_UINT32 dl_ofdma_nbinwb_selected_standalone[HTT_NUM_AC_WMM];
/**
* Number of instances where we populated TX mode and candidate lists
* only for DL.
*/
A_UINT32 running_only_dl_scheduler_cnt[HTT_NUM_AC_WMM];
/**
* Number of instances where we populated TX mode and candidate lists
* only for UL.
*/
A_UINT32 running_only_ul_scheduler_cnt[HTT_NUM_AC_WMM];
/**
* Number of instances where we populated TX mode and candidate lists
* additionally for DL after UL.
*/
A_UINT32 running_additional_dl_scheduler_cnt[HTT_NUM_AC_WMM];
/**
* Number of instances where we populated TX mode and candidate lists
* additionally for UL after DL.
*/
A_UINT32 running_additional_ul_scheduler_cnt[HTT_NUM_AC_WMM];
/**
* Number of instances where we populated TX mode and candidate lists
* only for UL BSR TX mode.
*/
A_UINT32 running_ul_scheduler_for_bsrp_cnt[HTT_NUM_AC_WMM];
} htt_stats_pdev_sched_algo_ofdma_stats_tlv;
/* preserve old name alias for new name consistent with the tag name */
typedef htt_stats_pdev_sched_algo_ofdma_stats_tlv

26
qcom/opensource/wlan/fw-api/fw/wlan_defs.h
View File

@@ -161,18 +161,6 @@ typedef enum {
MODE_11BE_EHT40_2G = 32, /* For WIN */
#endif
#if defined(SUPPORT_11BN) && SUPPORT_11BN
MODE_11BN_UHR20 = 33,
MODE_11BN_UHR40 = 34,
MODE_11BN_UHR80 = 35,
MODE_11BN_UHR80_80 = 36,
MODE_11BN_UHR160 = 37,
MODE_11BN_UHR160_160 = 38,
MODE_11BN_UHR320 = 39,
MODE_11BN_UHR20_2G = 40,
MODE_11BN_UHR40_2G = 41,
#endif
/*
* MODE_UNKNOWN should not be used within the host / target interface.
* Thus, it is permissible for MODE_UNKNOWN to be conditionally-defined,
@@ -274,20 +262,6 @@ typedef enum {
((mode) == MODE_11BE_EHT40_2G))
#endif /* SUPPORT_11BE */
#if defined(SUPPORT_11BN) && SUPPORT_11BN
#define IS_MODE_UHR(mode) (((mode) == MODE_11BN_UHR20) || \
((mode) == MODE_11BN_UHR40) || \
((mode) == MODE_11BN_UHR80) || \
((mode) == MODE_11BN_UHR80_80) || \
((mode) == MODE_11BN_UHR160) || \
((mode) == MODE_11BN_UHR160_160)|| \
((mode) == MODE_11BN_UHR320) || \
((mode) == MODE_11BN_UHR20_2G) || \
((mode) == MODE_11BN_UHR40_2G))
#define IS_MODE_UHR_2G(mode) (((mode) == MODE_11BN_UHR20_2G) || \
((mode) == MODE_11BN_UHR40_2G))
#endif /* SUPPORT_11BN */
#define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \
((mode) == MODE_11AC_VHT40_2G) || \
((mode) == MODE_11AC_VHT80_2G))

8
qcom/opensource/wlan/fw-api/fw/wlan_module_ids.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -191,12 +191,8 @@ typedef enum {
WLAN_MODULE_PHYLIB_RRI, /* 0x94 */
WLAN_MODULE_PHYLIB_SSCAN, /* 0x95 */
WLAN_MODULE_PHYLIB_RSVD, /* 0x96 */
WLAN_MODULE_USD, /* 0x97 */
WLAN_MODULE_C2C, /* 0x98 */
WLAN_MODULE_VBSS, /* 0x99 */
WLAN_MODULE_OPT_DATA, /* 0x9a */
WLAN_MODULE_ASD, /* 0x9b */
WLAN_MODULE_ID_MAX,
WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,

15
qcom/opensource/wlan/fw-api/fw/wmi_services.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2011-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -687,19 +687,6 @@ typedef enum {
WMI_SERVICE_USD_SUPPORT = 428, /* Indicates FW supports Unsynchronized Service Discovery */
WMI_SERVICE_THERM_THROT_5_LEVELS = 429, /* Indicates FW support 5 thermal throttling levels */
WMI_SERVICE_PROTECTED_TWT = 430, /* Indicates FW supports protected TWT operation */
WMI_SERVICE_SCAN_CACHE_REPORT_SUPPORT = 431, /* Indicates FW supports for sending scan cache report */
WMI_SERVICE_SCC_TPC_POWER_SUPPORT = 432, /* Indicates FW supports setting TPC power for SCC vdevs */
WMI_SERVICE_DYNAMIC_TWT_MODE_SUPPORT = 433, /* Indicates FW supports Dynamic TWT mode for vdevs */
WMI_SERVICE_SPECTRAL_SPUR_BIN_INFO_SUPPORT = 434, /* Indicates FW supports indicating spur frequency and spectral bin that gets affected due to spur frequency */
WMI_SERVICE_TWT_P2P_GO_CONCURRENCY_SUPPORT = 435, /* Indicates FW supports TWT in P2P GO concurrency mode */
WMI_SERVICE_UMAC_MIGRATION_SUPPORT = 436, /* Indicates that FW supports UMAC migration */
WMI_SERVICE_STA_TWT_STATS_EXT = 437, /* FW supports additional info in TWT stats and ADD COMPLETION Event */
WMI_SERVICE_OPT_DP_DIAG_SUPPORT = 438, /* FW supports diag QDATA feature */
WMI_SERVICE_MLO_ROAM_PARTNER_BRINGUP_FROM_HOST = 439, /* Indicates FW supports new design in which FW expects the host to bringup the partner link during roaming */
WMI_SERVICE_CTRL_PATH_PEER_BA_STATS = 440, /* FW supports retrieving BlockAck stats through WMI_REQUEST_CTRL_PATH_PEER_STAT */
WMI_SERVICE_CTRL_PATH_STA_DAR_STATS_SUPPORT = 441, /* FW supports DAR stats reporting for STA mode */
WMI_SERVICE_APF_DATA_OFFLOAD_SUPPORT_ENABLED = 442, /* Indicates FW support for APFv6 handling offloads and disable QC data offloads */
WMI_SERVICE_PER_VDEV_TWT_RESP_DISABLE_SUPPORT = 443, /* FW supports vdev level TWT responder disable */
WMI_MAX_EXT2_SERVICE

147
qcom/opensource/wlan/fw-api/fw/wmi_tlv_defs.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2010-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -1453,34 +1453,6 @@ typedef enum {
WMITLV_TAG_STRUC_wmi_pdev_power_boost_event_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_power_boost_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_pdev_power_boost_mem_addr_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_c2c_detect_event_fixed_param,
WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_scan_cache_result_event_fixed_param,
WMITLV_TAG_STRUC_wmi_scan_cache_info,
WMITLV_TAG_STRUC_wmi_POWER_BOOST_CAPABILITIES,
WMITLV_TAG_STRUC_wmi_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES,
WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_start_indication_event_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param,
WMITLV_TAG_STRUC_wmi_mlo_link_add_param,
WMITLV_TAG_STRUC_wmi_mlo_link_del_param,
WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cap_evt_fixed_param,
WMITLV_TAG_STRUC_wmi_wifi_radar_ltf_length_capabilities,
WMITLV_TAG_STRUC_wmi_wifi_radar_chain_capabilities,
WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_pdev_conn_stats_struct,
WMITLV_TAG_STRUC_wmi_pdev_sscan_spur_chan_impacted_bin_info,
WMITLV_TAG_STRUC_wmi_ctrl_path_ml_rcfg_stats_struct,
WMITLV_TAG_STRUC_wmi_vdev_vbss_config_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_pn_info,
WMITLV_TAG_STRUC_wmi_vdev_vbss_peer_sn_info,
WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param,
WMITLV_TAG_STRUC_wmi_stats_ext_event_vdev_ext2_t,
WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_partner_link_param,
WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_sta_dar_stats_struct,
WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param,
} WMITLV_TAG_ID;
/*
* IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2037,14 +2009,6 @@ typedef enum {
OP(WMI_USD_SERVICE_CMDID) \
OP(WMI_PDEV_POWER_BOOST_CMDID) \
OP(WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID) \
OP(WMI_GET_SCAN_CACHE_RESULT_CMDID) \
OP(WMI_MLO_LINK_RECONFIG_CMDID) \
OP(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID) \
OP(WMI_SAWF_EZMESH_HOP_COUNT_CMDID) \
OP(WMI_VDEV_VBSS_CONFIG_CMDID) \
OP(WMI_NDP_SET_LATENCY_TPUT_CMDID) \
OP(WMI_MLO_LINK_TTLM_COMPLETE_CMDID) \
OP(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -2374,12 +2338,6 @@ typedef enum {
OP(WMI_MLO_PEER_TID_TO_LINK_MAP_EVENTID) \
OP(WMI_USD_SERVICE_EVENTID) \
OP(WMI_PDEV_POWER_BOOST_EVENTID) \
OP(WMI_C2C_DETECT_EVENTID) \
OP(WMI_SCAN_CACHE_RESULT_EVENTID) \
OP(WMI_MLO_LINK_RECONFIG_START_INDICATION_EVENTID) \
OP(WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID) \
OP(WMI_VDEV_VBSS_CONFIG_EVENTID) \
OP(WMI_OPT_DP_DIAG_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -3647,13 +3605,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_PARAM_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_update_mac_addr_cmd_fixed_param, wmi_vdev_update_mac_addr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_UPDATE_MAC_ADDR_CMDID);
/* VDEV VBSS CONFIG COMMAND */
#define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_cmd_fixed_param, wmi_vdev_vbss_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_CMDID);
/* Pdev suspend Cmd */
#define WMITLV_TABLE_WMI_PDEV_SUSPEND_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_suspend_cmd_fixed_param, wmi_pdev_suspend_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4107,11 +4058,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_REQ_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_cmd_param, wmi_ndp_cmd_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CMDID);
/* NDP Set Latency Tput Cmd */
#define WMITLV_TABLE_WMI_NDP_SET_LATENCY_TPUT_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_set_latency_tput_fixed_param, wmi_ndp_set_latency_tput_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_SET_LATENCY_TPUT_CMDID);
/* RCPI Info Request Cmd */
#define WMITLV_TABLE_WMI_REQUEST_RCPI_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_rcpi_cmd_fixed_param, wmi_request_rcpi_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -5385,23 +5331,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_recommended_links, mlo_peer_recommended_links, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECOMMENDATION_CMDID);
/** WMI cmd to start STA initialized link reconfig */
#define WMITLV_TABLE_WMI_MLO_LINK_RECONFIG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_fixed_param, wmi_mlo_link_reconfig_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_add_param, link_add_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_del_param, link_del_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_CMDID);
/** WMI cmd to notify fw completion of link reconfig */
#define WMITLV_TABLE_WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_complete_fixed_param, wmi_mlo_link_reconfig_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_COMPLETE_CMDID);
/** WMI cmd to notify fw completion of link TTLM negotiation */
#define WMITLV_TABLE_WMI_MLO_LINK_TTLM_COMPLETE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_ttlm_complete_fixed_param, wmi_mlo_link_ttlm_complete_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_TTLM_COMPLETE_CMDID);
/* Mcast ipv4 address filter list cmd */
#define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -5502,8 +5431,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MULTIPLE_PEER_GROUP_CMDID);
/* RTT 11az PASN authentication status cmd */
#define WMITLV_TABLE_WMI_RTT_PASN_AUTH_STATUS_CMD(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_auth_status_cmd_fixed_param, wmi_rtt_pasn_auth_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_auth_status_param, pasn_auth_status_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, cookie, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_auth_status_param, pasn_auth_status_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_AUTH_STATUS_CMD);
/* RTT 11az PASN deauthentication cmd */
@@ -5754,19 +5682,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_boost_mem_addr_cmd_fixed_param, wmi_pdev_power_boost_mem_addr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_MEM_ADDR_CMDID);
/* WMI command to send scan cache result */
#define WMITLV_TABLE_WMI_GET_SCAN_CACHE_RESULT_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_scan_cache_result_cmd_fixed_param, wmi_get_scan_cache_result_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_GET_SCAN_CACHE_RESULT_CMDID);
#define WMITLV_TABLE_WMI_SAWF_EZMESH_HOP_COUNT_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sawf_ezmesh_hop_count_cmd_fixed_param, wmi_sawf_ezmesh_hop_count_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_SAWF_EZMESH_HOP_COUNT_CMDID);
#define WMITLV_TABLE_WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, wmi_bpf_set_supported_offload_bitmap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_BPF_SET_SUPPORTED_OFFLOAD_BITMAP_CMDID);
/************************** TLV definitions of WMI events *******************************/
@@ -5826,11 +5741,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sar_flag_tlv_param, sar_flags, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_POWER_BOOST_CAPABILITIES, power_boost_capabilities, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RSSI_ACCURACY_IMPROVEMENT_CAPABILITIES, rssi_accuracy_improvement_capabilities, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sar_flag_tlv_param, sar_flags, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
@@ -5838,12 +5749,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_fft_size_capabilities, fft_size_caps, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SPECTRAL_CAPABILITIES_EVENTID);
#define WMITLV_TABLE_WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wifi_radar_cap_evt_fixed_param, wmi_pdev_wifi_radar_cap_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_ltf_length_capabilities, wr_ltf_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wifi_radar_chain_capabilities, wr_chain_caps, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WIFI_RADAR_CAPABILITIES_EVENTID);
#define WMITLV_TABLE_WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info_event_fixed_param, wmi_chan_rf_characterization_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_CHAN_RF_CHARACTERIZATION_INFO, wmi_chan_rf_characterization_info, WMITLV_SIZE_VAR)
@@ -6114,8 +6019,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_partner_link_param, partner_link_param, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
/* Roam Synch Event */
@@ -6271,10 +6175,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_READ_DATA_FROM_FLASH_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_DIAG_EVENTID);
#define WMITLV_TABLE_WMI_OPT_DP_DIAG_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_OPT_DP_DIAG_EVENTID);
/* IGTK Offload Event */
#define WMITLV_TABLE_WMI_GTK_OFFLOAD_STATUS_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -6761,8 +6661,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ESTIMATED_LINKSPEED_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_stats_ext_event_fixed_param, wmi_stats_ext_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_partner_link_stats, partner_link_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, partner_link_data, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_stats_ext_event_vdev_ext2_t, stats_ext2_data, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, partner_link_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_STATS_EXT_EVENTID);
#define WMITLV_TABLE_WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID(id,op,buf,len) \
@@ -6990,11 +6889,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REG_CHAN_LIST_CC_EXT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_afc_chan_eirp_power_info, chan_eirp_power_info_array, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_AFC_EVENTID);
/* Indicate LPI AP detect or not to Host */
#define WMITLV_TABLE_WMI_C2C_DETECT_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_c2c_detect_event_fixed_param, wmi_c2c_detect_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_C2C_DETECT_EVENTID);
/* FIPS event */
#define WMITLV_TABLE_WMI_PDEV_FIPS_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_fips_event_fixed_param, wmi_pdev_fips_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -7278,10 +7172,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_rrm_stats_struct, ctrl_path_sta_rrm_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_bcn_tx_stats_struct, ctrl_path_vdev_bcn_tx_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_bcn_tx_stats_struct, ctrl_path_pdev_bcn_tx_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_conn_stats_struct, ctrl_path_pdev_conn_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_ml_rcfg_stats_struct, ctrl_path_ml_rcfg_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_dar_stats_struct, ctrl_path_sta_dar_stats, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pdev_bcn_tx_stats_struct, ctrl_path_pdev_bcn_tx_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
/*
@@ -7544,8 +7435,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SCHED_METHOD_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_sscan_fw_cmd_fixed_param, wmi_pdev_sscan_fw_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_fft_bin_index, fft_bin_index, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_sscan_chan_info, wmi_pdev_sscan_chan_info,chan_info, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_per_detector_info, det_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_spur_chan_impacted_bin_info, spur_chan_impacted_bin_info, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_sscan_per_detector_info, det_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SSCAN_FW_PARAM_EVENTID);
/* Send sscan related event start/stop trigger to host */
@@ -7660,8 +7550,7 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID);
#define WMITLV_TABLE_WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_rtt_pasn_peer_create_req_event_fixed_param, \
wmi_rtt_pasn_peer_create_req_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_create_req_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, cookie, WMITLV_SIZE_VAR)
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rtt_pasn_peer_create_req_param, rtt_pasn_peer_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_RTT_PASN_PEER_CREATE_REQ_EVENTID);
/* RTT 11az PASN peer delete event */
@@ -7795,13 +7684,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID);
/* VDEV VBSS CONFIG EVENT */
#define WMITLV_TABLE_WMI_VDEV_VBSS_CONFIG_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vbss_config_event_fixed_param, wmi_vdev_vbss_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_pn_info, vbss_peer_pn_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vdev_vbss_peer_sn_info, vbss_peer_sn_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_VBSS_CONFIG_EVENTID);
/* link switch event */
#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_REQUEST_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, wmi_mlo_link_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -7863,13 +7745,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_SRNG_REAP_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_peer_tid_to_link_map_event_fixed_param, wmi_mlo_peer_tid_to_link_map_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_EVENTID);
/** Indicate host to start link reconfigure */
#define WMITLV_TABLE_WMI_MLO_LINK_RECONFIG_START_INDICATION_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_reconfig_start_indication_event_fixed_param, wmi_mlo_link_reconfig_start_indication_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_add_param, link_add_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_del_param, link_del_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECONFIG_START_INDICATION_EVENTID);
/* USD Service Event */
#define WMITLV_TABLE_WMI_USD_SERVICE_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_usd_service_event_fixed_param, wmi_usd_service_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -7880,12 +7755,6 @@ WMITLV_CREATE_PARAM_STRUC(WMI_USD_SERVICE_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_power_boost_event_fixed_param, wmi_pdev_power_boost_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_POWER_BOOST_EVENTID);
#define WMITLV_TABLE_WMI_SCAN_CACHE_RESULT_EVENTID(id, op , buf, len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_scan_cache_result_event_fixed_param, wmi_scan_cache_result_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, scan_freq_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_cache_info, scan_cache_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SCAN_CACHE_RESULT_EVENTID);
#ifdef __cplusplus
}

1544
qcom/opensource/wlan/fw-api/fw/wmi_unified.h
View File

File diff suppressed because it is too large Load Diff

4
qcom/opensource/wlan/fw-api/fw/wmi_version.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2012-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -37,7 +37,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
#define __WMI_REVISION_ 1605
#define __WMI_REVISION_ 1526
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work

7
qcom/opensource/wlan/fw-api/hw/kiwi/v1/wcss_seq_hwioreg_umac.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2021,2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -386,11 +386,6 @@
#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0)
#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x3b0)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x3fc)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x400)
#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x404)

7
qcom/opensource/wlan/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -224,11 +224,6 @@
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x4ec)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x4f0)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0
#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x4f4)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x4f8)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x4fc)

7
qcom/opensource/wlan/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@@ -794,11 +794,6 @@
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8
#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x50c)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0
#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510)
#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27

5
qcom/opensource/wlan/fw-api/hw/peach/v2/wcss_seq_hwioreg_umac.h
View File

@@ -797,11 +797,6 @@
#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510)
#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27
#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x50c)
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514)
#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518)
#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524)