samsung_sm8750/android_kernel_samsung_sm8750-modules
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replace common qcom sources with samsung ones

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This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
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12
qcom/opensource/video-driver/driver/variant/common/src/msm_vidc_variant.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/errno.h>
@@ -30,7 +30,7 @@ int __write_register(struct msm_vidc_core *core, u32 reg, u32 value)
return -EINVAL;
}
base_addr = core->register_base_addr;
base_addr = core->resource->register_base_addr;
d_vpr_l("regwrite(%pK + %#x) = %#x\n", base_addr, hwiosymaddr, value);
base_addr += hwiosymaddr;
writel_relaxed(value, base_addr);
@@ -63,7 +63,7 @@ int __write_register_masked(struct msm_vidc_core *core, u32 reg, u32 value,
return -EINVAL;
}
base_addr = core->register_base_addr;
base_addr = core->resource->register_base_addr;
base_addr += reg;
prev_val = readl_relaxed(base_addr);
@@ -95,7 +95,7 @@ int __read_register(struct msm_vidc_core *core, u32 reg, u32 *value)
return -EINVAL;
}
base_addr = core->register_base_addr;
base_addr = core->resource->register_base_addr;
*value = readl_relaxed(base_addr + reg);
/*
@@ -121,7 +121,7 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
return -EINVAL;
}
addr = (u8 *)core->register_base_addr + reg;
addr = (u8 *)core->resource->register_base_addr + reg;
rc = readl_relaxed_poll_timeout(addr, val, ((val & mask) == exp_val), sleep_us, timeout_us);
/*
@@ -131,7 +131,7 @@ int __read_register_with_poll_timeout(struct msm_vidc_core *core, u32 reg,
rmb();
d_vpr_l(
"regread(%pK + %#x) = %#x. rc %d, mask %#x, exp_val %#x, cond %u, sleep %u, timeout %u\n",
core->register_base_addr, reg, val, rc, mask, exp_val,
core->resource->register_base_addr, reg, val, rc, mask, exp_val,
((val & mask) == exp_val), sleep_us, timeout_us);
return rc;

9
qcom/opensource/video-driver/driver/variant/iris3/inc/msm_vidc_power_iris3.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS3_H__
@@ -9,16 +9,11 @@
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
#include "perf_static_model.h"
#define ENABLE_LEGACY_POWER_CALCULATIONS 0
u64 msm_vidc_calc_freq_iris3(struct msm_vidc_inst *inst, u32 data_size);
int msm_vidc_calc_bw_iris3(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
struct vidc_bus_vote_data *vote_data);
#endif
int msm_vidc_calculate_frequency_iris3(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output);
int msm_vidc_calculate_bandwidth_iris3(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output);

30
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_bus_iris3.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kalama_technology.h"
@@ -34,10 +34,10 @@ struct compression_factors {
u32 dpb_cr_y;
u32 ipb_cr_y;
u32 ipb_cr;
} compression_factor_iris3;
} compression_factor;
u32 get_compression_factors_iris3(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
u32 get_compression_factors(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
{
u8 cr_index_entry, cr_index_y, cr_index_c, cr_index_uni;
u32 frame_width;
@@ -268,10 +268,10 @@ static int calculate_bandwidth_decoder_iris3(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris3(&compression_factor_iris3, codec_input);
dpb_compression_factor_y = compression_factor_iris3.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris3.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor_iris3.opb_cf_ycbcr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor.opb_cf_ycbcr;
dpb_ubwc_tile_width_pixels = ubwc_tile_w;
@@ -650,11 +650,11 @@ static int calculate_bandwidth_encoder_iris3(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris3(&compression_factor_iris3, codec_input);
dpb_compression_factor_y = compression_factor_iris3.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris3.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor_iris3.ipb_cr_y;
ipb_compression_factor = compression_factor_iris3.ipb_cr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor.ipb_cr_y;
ipb_compression_factor = compression_factor.ipb_cr;
en_tile_number = (frame_width % en_vertical_tiles_width) ?
((frame_width / en_vertical_tiles_width) + 1) :
@@ -909,8 +909,8 @@ static int calculate_bandwidth_encoder_iris3(
return 0;
}
int msm_vidc_calculate_bandwidth_iris3(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
int msm_vidc_calculate_bandwidth(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
int rc = 0;

10
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_clock_iris3.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "kalama_technology.h"
@@ -147,7 +147,7 @@ static int initialize_encoder_complexity_table(void)
return 0;
}
u32 get_bitrate_entry_iris3(u32 pixle_count)
u32 get_bitrate_entry(u32 pixle_count)
{
u32 bitrate_entry = 0;
@@ -195,7 +195,7 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
u32 pixle_count = codec_input.frame_width *
codec_input.frame_height * codec_input.frame_rate;
u8 bitrate_entry = get_bitrate_entry_iris3(pixle_count); /* TODO EXTRACT */
u8 bitrate_entry = get_bitrate_entry(pixle_count); /* TODO EXTRACT */
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
vsp_hw_min_frequency = frequency_table_kalama[0][1] * input_bitrate_fp * 1000;
@@ -540,8 +540,8 @@ static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
return 0;
}
int msm_vidc_calculate_frequency_iris3(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
int msm_vidc_calculate_frequency(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
int rc = 0;

6
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_iris3.c
View File

@@ -473,7 +473,7 @@ static int __power_off_iris3(struct msm_vidc_core *core)
d_vpr_e("%s: failed to unvote buses\n", __func__);
if (!call_venus_op(core, watchdog, core, core->intr_status))
disable_irq_nosync(core->irq);
disable_irq_nosync(core->resource->irq);
msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__);
@@ -569,7 +569,7 @@ static int __power_on_iris3(struct msm_vidc_core *core)
if (rc)
goto fail_power_on_substate;
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq = core->power.clk_freq ? core->power.clk_freq :
freq_tbl[0].freq;
@@ -586,7 +586,7 @@ static int __power_on_iris3(struct msm_vidc_core *core)
__interrupt_init_iris3(core);
core->intr_status = 0;
enable_irq(core->irq);
enable_irq(core->resource->irq);
return rc;

22
qcom/opensource/video-driver/driver/variant/iris3/src/msm_vidc_power_iris3.c
View File

@@ -9,6 +9,7 @@
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_debug.h"
#include "perf_static_model.h"
#include "msm_vidc_power.h"
static u64 __calculate_decoder(struct vidc_bus_vote_data *d);
@@ -302,7 +303,7 @@ static u64 msm_vidc_calc_freq_iris3_new(struct msm_vidc_inst *inst, u32 data_siz
ret = msm_vidc_init_codec_input_freq(inst, data_size, &codec_input);
if (ret)
return freq;
ret = msm_vidc_calculate_frequency_iris3(codec_input, &codec_output);
ret = msm_vidc_calculate_frequency(codec_input, &codec_output);
if (ret)
return freq;
freq = codec_output.hw_min_freq * 1000000; /* Convert to Hz */
@@ -318,8 +319,9 @@ static u64 msm_vidc_calc_freq_iris3_new(struct msm_vidc_inst *inst, u32 data_siz
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
return freq;
@@ -338,7 +340,7 @@ static int msm_vidc_calc_bw_iris3_new(struct msm_vidc_inst *inst,
ret = msm_vidc_init_codec_input_bus(inst, vidc_data, &codec_input);
if (ret)
return ret;
ret = msm_vidc_calculate_bandwidth_iris3(codec_input, &codec_output);
ret = msm_vidc_calculate_bandwidth(codec_input, &codec_output);
if (ret)
return ret;
@@ -377,7 +379,8 @@ static u64 msm_vidc_calc_freq_iris3_legacy(struct msm_vidc_inst *inst, u32 data_
core = inst->core;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
d_vpr_e("%s: invalid params\n", __func__);
return freq;
}
@@ -513,7 +516,7 @@ static u64 msm_vidc_calc_freq_iris3_legacy(struct msm_vidc_inst *inst, u32 data_
freq_entry = bitrate_entry;
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq_tbl_value = freq_tbl[freq_entry].freq / 1000000;
input_bitrate_mbps = fps * data_size * 8 / (1024 * 1024);
@@ -588,8 +591,9 @@ static u64 msm_vidc_calc_freq_iris3_legacy(struct msm_vidc_inst *inst, u32 data_
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
i_vpr_p(inst, "%s: filled len %d, required freq %llu, fps %u, mbpf %u\n",
@@ -1153,4 +1157,4 @@ int msm_vidc_calc_bw_iris3(struct msm_vidc_inst *inst,
value = msm_vidc_calc_bw_iris3_new(inst, vidc_data);
return value;
}
}

5
qcom/opensource/video-driver/driver/variant/iris33/inc/hfi_buffer_iris33.h
View File

@@ -1309,7 +1309,10 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
if (ltr_count) \
num_ref = num_ref + ltr_count; \
if (_total_hb_layers > 1) { \
num_ref = _total_hb_layers; \
if (codec_standard == HFI_CODEC_ENCODE_HEVC) \
num_ref = (_total_hb_layers); \
else if (codec_standard == HFI_CODEC_ENCODE_AVC) \
num_ref = (1 << (_total_hb_layers - 2)) + 1; \
} \
num_recon = num_ref + 1; \
} while (0)

4
qcom/opensource/video-driver/driver/variant/iris33/inc/msm_vidc_iris33.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _MSM_VIDC_IRIS3_3_H_
@@ -9,7 +9,7 @@
#include "msm_vidc_core.h"
#if defined(CONFIG_MSM_VIDC_PINEAPPLE) || defined(CONFIG_MSM_VIDC_SUN)
#if defined(CONFIG_MSM_VIDC_PINEAPPLE)
int msm_vidc_init_iris33(struct msm_vidc_core *core);
int msm_vidc_adjust_bitrate_boost_iris33(void *instance, struct v4l2_ctrl *ctrl);
#else

7
qcom/opensource/video-driver/driver/variant/iris33/inc/msm_vidc_power_iris33.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS3_3_H__
@@ -9,7 +9,6 @@
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
#include "perf_static_model.h"
#define ENABLE_LEGACY_POWER_CALCULATIONS 0
@@ -19,7 +18,3 @@ int msm_vidc_calc_bw_iris33(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
#endif
int msm_vidc_calculate_frequency_iris33(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output);
int msm_vidc_calculate_bandwidth_iris33(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output);

30
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_bus_iris33.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "perf_static_model.h"
@@ -114,10 +114,10 @@ struct compression_factors {
u32 dpb_cr_y;
u32 ipb_cr_y;
u32 ipb_cr;
} compression_factor_iris33;
} compression_factor;
u32 get_compression_factors_iris33(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
u32 get_compression_factors(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
{
u8 cr_index_entry, cr_index_y, cr_index_c, cr_index_uni;
u32 frame_width;
@@ -359,10 +359,10 @@ static int calculate_bandwidth_decoder_iris33(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris33(&compression_factor_iris33, codec_input);
dpb_compression_factor_y = compression_factor_iris33.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris33.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor_iris33.opb_cf_ycbcr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor.opb_cf_ycbcr;
dpb_ubwc_tile_width_pixels = ubwc_tile_w;
@@ -751,11 +751,11 @@ static int calculate_bandwidth_encoder_iris33(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris33(&compression_factor_iris33, codec_input);
dpb_compression_factor_y = compression_factor_iris33.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris33.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor_iris33.ipb_cr_y;
ipb_compression_factor = compression_factor_iris33.ipb_cr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor.ipb_cr_y;
ipb_compression_factor = compression_factor.ipb_cr;
en_tile_number = (frame_width % en_vertical_tiles_width) ?
((frame_width / en_vertical_tiles_width) + 1) :
@@ -1033,8 +1033,8 @@ static int calculate_bandwidth_encoder_iris33(
return 0;
}
int msm_vidc_calculate_bandwidth_iris33(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
int msm_vidc_calculate_bandwidth(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
int rc = 0;

10
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_clock_iris33.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "perf_static_model.h"
@@ -292,7 +292,7 @@ static int initialize_encoder_complexity_table(void)
return 0;
}
u32 get_bitrate_entry_iris33(u32 pixle_count)
u32 get_bitrate_entry(u32 pixle_count)
{
u32 bitrate_entry = 0;
@@ -342,7 +342,7 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
u32 pixle_count = codec_input.frame_width *
codec_input.frame_height * codec_input.frame_rate;
u8 bitrate_entry = get_bitrate_entry_iris33(pixle_count); /* TODO EXTRACT */
u8 bitrate_entry = get_bitrate_entry(pixle_count); /* TODO EXTRACT */
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
@@ -709,8 +709,8 @@ static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
return 0;
}
int msm_vidc_calculate_frequency_iris33(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
int msm_vidc_calculate_frequency(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
int rc = 0;

348
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_iris33.c
View File

@@ -92,7 +92,6 @@ typedef enum {
#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS_IRIS33 + 0x5C)
#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS_IRIS33 + 0x60)
#define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS_IRIS33 + 0x80)
#define WRAPPER_CORE_POWER_CONTROL (WRAPPER_BASE_OFFS_IRIS33 + 0x84)
#define WRAPPER_CORE_CLOCK_CONFIG_IRIS33 (WRAPPER_BASE_OFFS_IRIS33 + 0x88)
/*
@@ -135,10 +134,6 @@ typedef enum {
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33 (NOC_BASE_OFFS + 0xA038)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33 (NOC_BASE_OFFS + 0xA03C)
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040)
#define VCODEC_NOC_SidebandManager_SenseIn0_Low (NOC_BASE_OFFS + 0x7100)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH (NOC_BASE_OFFS + 0x7104)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH (NOC_BASE_OFFS + 0x710C)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW (NOC_BASE_OFFS + 0x7110)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3508)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3518)
@@ -151,12 +146,6 @@ typedef enum {
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3538)
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P (NOC_BASE_OFFS + 0x353C)
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240)
#define VCODEC_NOC_SidebandManager_SenseIn0_Low_2P (NOC_BASE_OFFS + 0x3300)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P (NOC_BASE_OFFS + 0x3304)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P (NOC_BASE_OFFS + 0x330C)
#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P (NOC_BASE_OFFS + 0x3310)
#define VCODEC_DMA_SPARE_3 0x87B8
static int __interrupt_init_iris33(struct msm_vidc_core *core)
{
@@ -181,22 +170,25 @@ static int __interrupt_init_iris33(struct msm_vidc_core *core)
static int __get_device_region_info(struct msm_vidc_core *core,
u32 *min_dev_addr, u32 *dev_reg_size)
{
struct device_region_set *dev_set;
u32 min_addr, max_addr, count = 0;
int rc = 0;
if (!core->device_region_tbl_count) {
dev_set = &core->resource->device_region_set;
if (!dev_set->count) {
d_vpr_h("%s: device region not available\n", __func__);
return 0;
}
min_addr = 0xFFFFFFFF;
max_addr = 0x0;
for (count = 0; count < core->device_region_tbl_count; count++) {
if (core->device_region_tbl[count].dev_addr > max_addr)
max_addr = core->device_region_tbl[count].dev_addr +
core->device_region_tbl[count].size;
if (core->device_region_tbl[count].dev_addr < min_addr)
min_addr = core->device_region_tbl[count].dev_addr;
for (count = 0; count < dev_set->count; count++) {
if (dev_set->device_region_tbl[count].dev_addr > max_addr)
max_addr = dev_set->device_region_tbl[count].dev_addr +
dev_set->device_region_tbl[count].size;
if (dev_set->device_region_tbl[count].dev_addr < min_addr)
min_addr = dev_set->device_region_tbl[count].dev_addr;
}
if (min_addr == 0xFFFFFFFF || max_addr == 0x0) {
d_vpr_e("%s: invalid device region\n", __func__);
@@ -290,9 +282,8 @@ static bool is_iris33_hw_power_collapsed(struct msm_vidc_core *core)
static int __power_off_iris33_hardware(struct msm_vidc_core *core)
{
int rc = 0, i;
u32 value = 0, count = 0;
u32 value = 0;
bool pwr_collapsed = false;
u32 sense0_low, sense0_high, sense1_high, sense2_low;
/*
* Incase hw power control is enabled, for any error case
@@ -313,10 +304,6 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
}
}
rc = call_res_op(core, gdsc_sw_ctrl, core);
if (rc)
return rc;
/*
* check to make sure core clock branch enabled else
* we cannot read vcodec top idle register
@@ -333,10 +320,6 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
return rc;
}
rc = __write_register_masked(core, VCODEC_DMA_SPARE_3, 0x1, BIT(0));
if (rc)
return rc;
/*
* add MNoC idle check before collapsing MVS0 per HPG update
* poll for NoC DMA idle -> HPG 6.1.1
@@ -355,84 +338,15 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
if (rc)
return rc;
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS,
0x1, 0x1, 200, 2000);
if (rc)
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
while ((!(value & BIT(0))) && (value & BIT(1) || value & BIT(2))) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value);
if (rc)
return rc;
++count;
if (count >= 1000) {
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
break;
}
}
if (count < 1000) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
}
i = 0;
do {
value = 0;
if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33) {
__read_register(core,
VCODEC_NOC_SidebandManager_SenseIn0_Low,
&sense0_low);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH,
&sense0_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH,
&sense1_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW,
&sense2_low);
} else if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33_2P) {
__read_register(core,
VCODEC_NOC_SidebandManager_SenseIn0_Low_2P,
&sense0_low);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P,
&sense0_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P,
&sense1_high);
__read_register(core,
VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P,
&sense2_low);
}
value = ((sense0_low & 0x00008000) ||
(sense0_high & 0x00000800) ||
(sense1_high & 0x00800000) ||
(sense2_low & 0x00002000));
usleep_range(10, 20);
i++;
} while ((value) && (i <= 100));
d_vpr_h("%s: sideband register value = %d\n", __func__, value);
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
/*
* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
@@ -456,13 +370,19 @@ disable_power:
rc = 0;
}
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
return rc;
}
static int __power_off_iris33_controller(struct msm_vidc_core *core)
{
int noc_lpi_status = 0, count = 0;
int rc = 0, value = 0;
int rc = 0;
int value = 0;
/*
* mask fal10_veto QLPAC error since fal10_veto can go 1
@@ -514,11 +434,6 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core)
rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
rc = call_res_op(core, reset_control_assert, core, "video_mvs0_reset");
if (rc)
d_vpr_e("%s: assert video_mvs0_reset failed\n", __func__);
/* set retain mem and peripheral before asset mvs0c reset */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
@@ -532,9 +447,6 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core)
if (rc)
d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
usleep_range(400, 500);
rc = call_res_op(core, reset_control_deassert, core, "video_mvs0_reset");
if (rc)
d_vpr_e("%s: de-assert video_mvs0_reset failed\n", __func__);
rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
@@ -611,12 +523,6 @@ skip_video_xo_reset:
if (rc)
return rc;
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
/* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
@@ -635,141 +541,6 @@ skip_video_xo_reset:
rc = 0;
}
if (!is_core_state(core, MSM_VIDC_CORE_ERROR))
goto power_down;
/* power cycle process to recover from NoC error */
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
if (rc) {
d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
rc = 0;
}
call_res_op(core, gdsc_on, core, "iris-ctl");
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0c_clk");
/* assert and deassert axi and mvs0c resets */
rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
/* set retain mem and peripheral before asset mvs0c reset */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
if (rc)
d_vpr_e("%s: set retain mem failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set retain peripheral failed\n", __func__);
rc = call_res_op(core, reset_control_assert, core, "video_mvs0c_reset");
if (rc)
d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
usleep_range(400, 500);
rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
if (rc)
d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
rc = call_res_op(core, reset_control_deassert, core, "video_mvs0c_reset");
if (rc)
d_vpr_e("%s: de-assert video_mvs0c_reset failed\n", __func__);
/* When the vcodec GDSC is powered on and then moves into HW control. As it moves into HW
* control, vcodec is initiated with power down sequence then driver requests for migrating
* GDSC into sw control, which implies power up sequence for GDSC. Due to b2b switch of
* power off and on for video hardware, it ends up in transient state and hungs eventually.
* So Writing the register explicitly to avoid power off sequence when HW control is set.
*/
writel_relaxed(0x0, (u8 *)core->register_base_addr + WRAPPER_CORE_POWER_CONTROL);
rc = call_res_op(core, gdsc_on, core, "vcodec");
if (rc)
return rc;
rc = call_res_op(core, gdsc_sw_ctrl, core);
if (rc)
return rc;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk");
if (rc)
return rc;
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
if (rc)
return rc;
while ((!(noc_lpi_status & BIT(0))) &&
(noc_lpi_status & BIT(1) || noc_lpi_status & BIT(2))) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x1, BIT(0));
if (rc)
return rc;
usleep_range(10, 20);
rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
if (rc)
return rc;
++count;
if (count >= 1000) {
d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
break;
}
}
if (count < 1000) {
rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
0x0, BIT(0));
if (rc)
return rc;
}
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
rc = 0;
}
rc = call_res_op(core, gdsc_off, core, "vcodec");
if (rc) {
d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
rc = 0;
}
/* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set noretain peripheral failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_MEM);
if (rc)
d_vpr_e("%s: set noretain mem failed\n", __func__);
/* Turn off MVP MVS0C core clock */
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk");
if (rc) {
d_vpr_e("%s: disable unprepare video_cc_mvs0c_clk failed\n", __func__);
rc = 0;
}
power_down:
/* power down process */
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
if (rc) {
@@ -817,7 +588,7 @@ static int __power_off_iris33(struct msm_vidc_core *core)
d_vpr_e("%s: failed to unvote buses\n", __func__);
if (!call_venus_op(core, watchdog, core, core->intr_status))
disable_irq_nosync(core->irq);
disable_irq_nosync(core->resource->irq);
msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__);
@@ -875,27 +646,10 @@ static int __power_on_iris33_hardware(struct msm_vidc_core *core)
{
int rc = 0;
/* When the vcodec GDSC is powered on and then moves into HW control. As it moves into HW
* control, vcodec is initiated with power down sequence then driver requests for migrating
* GDSC into sw control, which implies power up sequence for GDSC. Due to b2b switch of
* power off and on for video hardware, it ends up in transient state and hungs eventually.
* So Writing the register explicitly to avoid power off sequence when HW control is set.
*/
writel_relaxed(0x0, (u8 *)core->register_base_addr + WRAPPER_CORE_POWER_CONTROL);
rc = call_res_op(core, gdsc_on, core, "vcodec");
if (rc)
goto fail_regulator;
/* video controller and hardware powered on successfully */
rc = msm_vidc_change_core_sub_state(core, 0, CORE_SUBSTATE_POWER_ENABLE, __func__);
if (rc)
goto fail_power_on_substate;
rc = call_res_op(core, gdsc_sw_ctrl, core);
if (rc)
goto fail_sw_ctrl;
rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk");
if (rc)
goto fail_clk_controller;
@@ -903,9 +657,6 @@ static int __power_on_iris33_hardware(struct msm_vidc_core *core)
return 0;
fail_clk_controller:
call_res_op(core, gdsc_hw_ctrl, core);
fail_sw_ctrl:
fail_power_on_substate:
call_res_op(core, gdsc_off, core, "vcodec");
fail_regulator:
return rc;
@@ -944,8 +695,12 @@ static int __power_on_iris33(struct msm_vidc_core *core)
d_vpr_e("%s: failed to power on iris33 hardware\n", __func__);
goto fail_power_on_hardware;
}
/* video controller and hardware powered on successfully */
rc = msm_vidc_change_core_sub_state(core, 0, CORE_SUBSTATE_POWER_ENABLE, __func__);
if (rc)
goto fail_power_on_substate;
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq = core->power.clk_freq ? core->power.clk_freq :
freq_tbl[0].freq;
@@ -1039,7 +794,7 @@ static int __power_on_iris33(struct msm_vidc_core *core)
__interrupt_init_iris33(core);
core->intr_status = 0;
enable_irq(core->irq);
enable_irq(core->resource->irq);
return rc;
@@ -1047,6 +802,8 @@ fail_program_noc_regs:
call_res_op(core, reset_control_release, core, "video_xo_reset");
fail_deassert_xo_reset:
fail_assert_xo_reset:
fail_power_on_substate:
__power_off_iris33_hardware(core);
fail_power_on_hardware:
__power_off_iris33_controller(core);
fail_power_on_controller:
@@ -1310,6 +1067,7 @@ static int __noc_error_info_iris33(struct msm_vidc_core *core)
fail_deassert_xo_reset:
fail_assert_xo_reset:
MSM_VIDC_FATAL(true);
return rc;
}
@@ -1400,37 +1158,6 @@ static int __boot_firmware_iris33(struct msm_vidc_core *core)
return rc;
}
static int __switch_gdsc_mode_iris33(struct msm_vidc_core *core, bool sw_mode)
{
int rc;
if (sw_mode) {
rc = __write_register(core, WRAPPER_CORE_POWER_CONTROL, 0x0);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, WRAPPER_CORE_POWER_STATUS,
BIT(1), 0x2, 200, 2000);
if (rc) {
d_vpr_e("%s: Failed to read WRAPPER_CORE_POWER_STATUS register to 0x1\n",
__func__);
return rc;
}
} else {
rc = __write_register(core, WRAPPER_CORE_POWER_CONTROL, 0x1);
if (rc)
return rc;
rc = __read_register_with_poll_timeout(core, WRAPPER_CORE_POWER_STATUS,
BIT(1), 0x0, 200, 2000);
if (rc) {
d_vpr_e("%s: Failed to read WRAPPER_CORE_POWER_STATUS register to 0x0\n",
__func__);
return rc;
}
}
return 0;
}
int msm_vidc_decide_work_mode_iris33(struct msm_vidc_inst *inst)
{
u32 work_mode;
@@ -1645,7 +1372,6 @@ static struct msm_vidc_venus_ops iris33_ops = {
.prepare_pc = __prepare_pc_iris33,
.watchdog = __watchdog_iris33,
.noc_error_info = __noc_error_info_iris33,
.switch_gdsc_mode = __switch_gdsc_mode_iris33,
};
static struct msm_vidc_session_ops msm_session_ops = {

57
qcom/opensource/video-driver/driver/variant/iris33/src/msm_vidc_power_iris33.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_power_iris33.h"
@@ -10,6 +10,7 @@
#include "msm_vidc_core.h"
#include "msm_vidc_platform.h"
#include "msm_vidc_debug.h"
#include "perf_static_model.h"
#include "msm_vidc_power.h"
#define VPP_MIN_FREQ_MARGIN_PERCENT 5 /* to be tuned */
@@ -51,7 +52,6 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
enum msm_vidc_port_type port;
u32 color_fmt, tile_rows_columns = 0;
struct msm_vidc_core *core;
u32 max_rate, frame_rate;
if (is_encode_session(inst)) {
codec_input->decoder_or_encoder = CODEC_ENCODER;
@@ -124,26 +124,13 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
codec_input->linear_opb = is_linear_colorformat(color_fmt);
if (is_decode_session(inst)) {
if (is_decode_session(inst))
codec_input->bitrate_mbps =
(codec_input->frame_rate * data_size * 8) / 1000000;
} else {
frame_rate = msm_vidc_get_frame_rate(inst);
max_rate = inst->max_rate;
else
codec_input->bitrate_mbps =
inst->capabilities[BIT_RATE].value / 1000000;
/*
* In encoding cases, the bitrate should scale with the frame
* rate, especially for HFR cases.
* Otherwise, a lower bitrate may lead to a lower vsp frequency,
* resulting in insufficient performance.
*/
if (frame_rate && max_rate > frame_rate)
codec_input->bitrate_mbps =
codec_input->bitrate_mbps * max_rate / frame_rate;
}
/* av1d commercial tile */
if (inst->codec == MSM_VIDC_AV1 && codec_input->lcu_size == 128) {
tile_rows_columns = inst->power.fw_av1_tile_rows *
@@ -392,25 +379,27 @@ static bool is_vpp_cycles_close_to_freq_corner(struct msm_vidc_core *core,
u32 margin_percent = 0;
int i = 0;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core || !core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
d_vpr_e("%s: invalid params\n", __func__);
return false;
}
vpp_min_freq = vpp_min_freq * 1000000; /* convert to hz */
closest_freq_upper_corner = core->freq_tbl[0].freq;
closest_freq_upper_corner =
core->resource->freq_set.freq_tbl[0].freq;
/* return true if vpp_min_freq is more than max frequency */
if (vpp_min_freq > closest_freq_upper_corner)
return true;
/* get the closest freq corner for vpp_min_freq */
for (i = 0; i < core->freq_tbl_count; i++) {
for (i = 0; i < core->resource->freq_set.count; i++) {
if (vpp_min_freq <=
core->freq_tbl[i].freq) {
core->resource->freq_set.freq_tbl[i].freq) {
closest_freq_upper_corner =
core->freq_tbl[i].freq;
core->resource->freq_set.freq_tbl[i].freq;
} else {
break;
}
@@ -445,7 +434,7 @@ static u64 msm_vidc_calc_freq_iris33_new(struct msm_vidc_inst *inst, u32 data_si
ret = msm_vidc_init_codec_input_freq(inst, data_size, &codec_input);
if (ret)
return freq;
ret = msm_vidc_calculate_frequency_iris33(codec_input, &codec_output);
ret = msm_vidc_calculate_frequency(codec_input, &codec_output);
if (ret)
return freq;
@@ -489,8 +478,9 @@ static u64 msm_vidc_calc_freq_iris33_new(struct msm_vidc_inst *inst, u32 data_si
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
return freq;
@@ -509,7 +499,7 @@ static int msm_vidc_calc_bw_iris33_new(struct msm_vidc_inst *inst,
ret = msm_vidc_init_codec_input_bus(inst, vidc_data, &codec_input);
if (ret)
return ret;
ret = msm_vidc_calculate_bandwidth_iris33(codec_input, &codec_output);
ret = msm_vidc_calculate_bandwidth(codec_input, &codec_output);
if (ret)
return ret;
@@ -548,7 +538,8 @@ u64 msm_vidc_calc_freq_iris33_legacy(struct msm_vidc_inst *inst, u32 data_size)
core = inst->core;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
d_vpr_e("%s: invalid params\n", __func__);
return freq;
}
@@ -684,7 +675,7 @@ u64 msm_vidc_calc_freq_iris33_legacy(struct msm_vidc_inst *inst, u32 data_size)
freq_entry = bitrate_entry;
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq_tbl_value = freq_tbl[freq_entry].freq / 1000000;
input_bitrate_mbps = fps * data_size * 8 / (1024 * 1024);
@@ -767,8 +758,9 @@ u64 msm_vidc_calc_freq_iris33_legacy(struct msm_vidc_inst *inst, u32 data_size)
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
return freq;
@@ -1340,7 +1332,8 @@ int msm_vidc_ring_buf_count_iris33(struct msm_vidc_inst *inst, u32 data_size)
core = inst->core;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
i_vpr_e(inst, "%s: invalid frequency table\n", __func__);
return -EINVAL;
}
@@ -1353,7 +1346,7 @@ int msm_vidc_ring_buf_count_iris33(struct msm_vidc_inst *inst, u32 data_size)
rc = msm_vidc_init_codec_input_freq(inst, data_size, &codec_input);
if (rc)
return rc;
rc = msm_vidc_calculate_frequency_iris33(codec_input, &codec_output);
rc = msm_vidc_calculate_frequency(codec_input, &codec_output);
if (rc)
return rc;

31
qcom/opensource/video-driver/driver/variant/iris35/inc/hfi_buffer_iris35.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __HFI_BUFFER_IRIS3_5__
@@ -1301,14 +1301,12 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
if (ltr_count) \
num_ref = num_ref + ltr_count; \
if (codec_standard == HFI_CODEC_ENCODE_HEVC && \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN || \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN_10)) \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN) \
num_ref = 3; \
if (_total_hb_layers > 1) { \
num_ref = _total_hb_layers; \
if (codec_standard == HFI_CODEC_ENCODE_HEVC && \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN || \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN_10)) \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN) \
num_ref = num_ref * 2; \
} \
num_recon = num_ref + 1; \
@@ -1525,13 +1523,12 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
num_vpp_pipes_enc;\
} \
if ((standard == HFI_CODEC_ENCODE_HEVC) && \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN || \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN_10)) { \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN)) { \
_size = HFI_ALIGN(_size, BUFFER_ALIGNMENT_512_BYTES) * \
HFI_MAX_COL_FRAME_MVHEVC; \
} else { \
_size = HFI_ALIGN(_size, BUFFER_ALIGNMENT_512_BYTES) * \
HFI_MAX_COL_FRAME; \
HFI_MAX_COL_FRAME; \
} \
} while (0)
@@ -1656,8 +1653,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
VENUS_DMA_ALIGNMENT) * num_recon; \
size_colloc_rc = (((mb_width + 7) >> 3) * 16 * 2 * mb_height); \
if ((standard == HFI_CODEC_ENCODE_HEVC) && \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN || \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN_10)) { \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN)) { \
size_colloc_rc = HFI_ALIGN(size_colloc_rc, \
VENUS_DMA_ALIGNMENT) * HFI_MAX_COL_FRAME_MVHEVC; \
} else { \
@@ -1668,12 +1664,16 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
} while (0)
#define HFI_BUFFER_COMV_H264E(_size, frame_width, frame_height, num_recon, profile) \
HFI_BUFFER_COMV_ENC(_size, frame_width, frame_height, 16, \
num_recon, HFI_CODEC_ENCODE_AVC, profile)
do { \
HFI_BUFFER_COMV_ENC(_size, frame_width, frame_height, 16, \
num_recon, HFI_CODEC_ENCODE_AVC, profile); \
} while (0)
#define HFI_BUFFER_COMV_H265E(_size, frame_width, frame_height, num_recon, profile) \
HFI_BUFFER_COMV_ENC(_size, frame_width, frame_height, 32,\
num_recon, HFI_CODEC_ENCODE_HEVC, profile)
do { \
HFI_BUFFER_COMV_ENC(_size, frame_width, frame_height, 32,\
num_recon, HFI_CODEC_ENCODE_HEVC, profile); \
} while (0)
#define HFI_BUFFER_NON_COMV_ENC(_size, frame_width, frame_height, \
num_vpp_pipes_enc, lcu_size, standard, profile) \
@@ -1823,8 +1823,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
if (TotalHBLayers >= 2) { \
numInput = (1 << (TotalHBLayers - 1)) + 2; \
if (codec_standard == HFI_CODEC_ENCODE_HEVC && \
(profile == HFI_H265_PROFILE_MULTIVIEW_MAIN || \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN_10)) \
profile == HFI_H265_PROFILE_MULTIVIEW_MAIN) \
numInput = (((1 << (TotalHBLayers - 1)) * 2) - 1) + 2; \
} \
} while (0)

7
qcom/opensource/video-driver/driver/variant/iris35/inc/msm_vidc_power_iris35.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __H_MSM_VIDC_POWER_IRIS3_5_H__
@@ -9,7 +9,6 @@
#include "msm_vidc_inst.h"
#include "msm_vidc_power.h"
#include "perf_static_model.h"
#define ENABLE_LEGACY_POWER_CALCULATIONS 0
@@ -19,7 +18,3 @@ int msm_vidc_calc_bw_iris35(struct msm_vidc_inst *inst,
struct vidc_bus_vote_data *vote_data);
#endif
int msm_vidc_calculate_frequency_iris35(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output);
int msm_vidc_calculate_bandwidth_iris35(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output);

30
qcom/opensource/video-driver/driver/variant/iris35/src/msm_vidc_bus_iris35.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "perf_static_model.h"
@@ -122,10 +122,10 @@ struct compression_factors {
u32 dpb_cr_y;
u32 ipb_cr_y;
u32 ipb_cr;
} compression_factor_iris35;
} compression_factor;
u32 get_compression_factors_iris35(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
u32 get_compression_factors(struct compression_factors *compression_factor,
struct api_calculation_input codec_input)
{
u8 cr_index_entry, cr_index_y, cr_index_c, cr_index_uni;
u32 frame_width;
@@ -353,10 +353,10 @@ static int calculate_bandwidth_decoder_iris35(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris35(&compression_factor_iris35, codec_input);
dpb_compression_factor_y = compression_factor_iris35.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris35.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor_iris35.opb_cf_ycbcr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
opb_compression_factor_ycbcr = compression_factor.opb_cf_ycbcr;
dpb_ubwc_tile_width_pixels = ubwc_tile_w;
@@ -735,11 +735,11 @@ static int calculate_bandwidth_encoder_iris35(
codec_input.frame_rate * 2 + 999) / 1000 + 999) / 1000;
/* TODO Integrate Compression Ratio returned by FW */
get_compression_factors_iris35(&compression_factor_iris35, codec_input);
dpb_compression_factor_y = compression_factor_iris35.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor_iris35.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor_iris35.ipb_cr_y;
ipb_compression_factor = compression_factor_iris35.ipb_cr;
get_compression_factors(&compression_factor, codec_input);
dpb_compression_factor_y = compression_factor.dpb_cf_y;
dpb_compression_factor_cbcr = compression_factor.dpb_cf_cbcr;
ipb_compression_factor_y = compression_factor.ipb_cr_y;
ipb_compression_factor = compression_factor.ipb_cr;
if (codec_input.hierachical_layer == CODEC_GOP_IPP) {
en_vertical_tiles_width = sun_P_en_vertical_tiles_width;
@@ -1024,8 +1024,8 @@ static int calculate_bandwidth_encoder_iris35(
return 0;
}
int msm_vidc_calculate_bandwidth_iris35(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
int msm_vidc_calculate_bandwidth(struct api_calculation_input codec_input,
struct api_calculation_bw_output *codec_output)
{
int rc = 0;

10
qcom/opensource/video-driver/driver/variant/iris35/src/msm_vidc_clock_iris35.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "perf_static_model.h"
@@ -344,7 +344,7 @@ static int initialize_encoder_complexity_table(void)
return 0;
}
u32 get_bitrate_entry_iris35(u32 pixle_count)
u32 get_bitrate_entry(u32 pixle_count)
{
u32 bitrate_entry = 0;
@@ -392,7 +392,7 @@ static int calculate_vsp_min_freq(struct api_calculation_input codec_input,
u32 pixle_count = codec_input.frame_width *
codec_input.frame_height * codec_input.frame_rate;
u8 bitrate_entry = get_bitrate_entry_iris35(pixle_count); /* TODO EXTRACT */
u8 bitrate_entry = get_bitrate_entry(pixle_count); /* TODO EXTRACT */
input_bitrate_fp = ((u32)(codec_input.bitrate_mbps * 100 + 99)) / 100;
@@ -773,8 +773,8 @@ static int calculate_vpp_min_freq(struct api_calculation_input codec_input,
return 0;
}
int msm_vidc_calculate_frequency_iris35(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
int msm_vidc_calculate_frequency(struct api_calculation_input codec_input,
struct api_calculation_freq_output *codec_output)
{
int rc = 0;

23
qcom/opensource/video-driver/driver/variant/iris35/src/msm_vidc_iris35.c
View File

@@ -206,22 +206,25 @@ static int __clear_interrupt_iris35(struct msm_vidc_core *core)
static int __get_device_region_info(struct msm_vidc_core *core,
u32 *min_dev_addr, u32 *dev_reg_size)
{
struct device_region_set *dev_set;
u32 min_addr, max_addr, count = 0;
int rc = 0;
if (!core->device_region_tbl_count) {
dev_set = &core->resource->device_region_set;
if (!dev_set->count) {
d_vpr_h("%s: device region not available\n", __func__);
return 0;
}
min_addr = 0xFFFFFFFF;
max_addr = 0x0;
for (count = 0; count < core->device_region_tbl_count; count++) {
if (core->device_region_tbl[count].dev_addr > max_addr)
max_addr = core->device_region_tbl[count].dev_addr +
core->device_region_tbl[count].size;
if (core->device_region_tbl[count].dev_addr < min_addr)
min_addr = core->device_region_tbl[count].dev_addr;
for (count = 0; count < dev_set->count; count++) {
if (dev_set->device_region_tbl[count].dev_addr > max_addr)
max_addr = dev_set->device_region_tbl[count].dev_addr +
dev_set->device_region_tbl[count].size;
if (dev_set->device_region_tbl[count].dev_addr < min_addr)
min_addr = dev_set->device_region_tbl[count].dev_addr;
}
if (min_addr == 0xFFFFFFFF || max_addr == 0x0) {
d_vpr_e("%s: invalid device region\n", __func__);
@@ -692,7 +695,7 @@ static int __power_off_iris35(struct msm_vidc_core *core)
d_vpr_e("%s: failed to unvote buses\n", __func__);
if (!call_venus_op(core, watchdog, core, core->intr_status))
disable_irq_nosync(core->irq);
disable_irq_nosync(core->resource->irq);
msm_vidc_change_core_sub_state(core, CORE_SUBSTATE_POWER_ENABLE, 0, __func__);
@@ -809,7 +812,7 @@ static int __power_on_iris35(struct msm_vidc_core *core)
goto fail_power_on_hardware;
}
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq = core->power.clk_freq ? core->power.clk_freq :
freq_tbl[0].freq;
@@ -823,7 +826,7 @@ static int __power_on_iris35(struct msm_vidc_core *core)
__interrupt_init_iris35(core);
core->intr_status = 0;
enable_irq(core->irq);
enable_irq(core->resource->irq);
return rc;

63
qcom/opensource/video-driver/driver/variant/iris35/src/msm_vidc_power_iris35.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "msm_vidc_power_iris35.h"
@@ -9,6 +9,7 @@
#include "msm_vidc_inst.h"
#include "msm_vidc_core.h"
#include "msm_vidc_debug.h"
#include "perf_static_model.h"
#include "msm_vidc_power.h"
#define VPP_MIN_FREQ_MARGIN_PERCENT 5 /* to be tuned */
@@ -49,7 +50,6 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
{
enum msm_vidc_port_type port;
u32 color_fmt, tile_rows_columns = 0;
u32 max_rate, frame_rate;
if (is_encode_session(inst)) {
codec_input->decoder_or_encoder = CODEC_ENCODER;
@@ -122,27 +122,13 @@ static int msm_vidc_init_codec_input_freq(struct msm_vidc_inst *inst, u32 data_s
codec_input->linear_opb = is_linear_colorformat(color_fmt);
if (is_decode_session(inst)) {
if (is_decode_session(inst))
codec_input->bitrate_mbps =
(codec_input->frame_rate * data_size * 8) / 1000000;
} else {
frame_rate = msm_vidc_get_frame_rate(inst);
max_rate = inst->max_rate;
else
codec_input->bitrate_mbps =
inst->capabilities[BIT_RATE].value / 1000000;
/*
* In encoding cases, the bitrate should scale with the frame
* rate, especially for HFR cases.
* Otherwise, a lower bitrate may lead to a lower vsp frequency,
* resulting in insufficient performance.
*/
if (frame_rate && max_rate > frame_rate)
codec_input->bitrate_mbps =
codec_input->bitrate_mbps * max_rate / frame_rate;
}
/* av1d commercial tile */
if (inst->codec == MSM_VIDC_AV1 && codec_input->lcu_size == 128) {
tile_rows_columns = inst->power.fw_av1_tile_rows *
@@ -388,25 +374,30 @@ static bool is_vpp_cycles_close_to_freq_corner(struct msm_vidc_core *core,
u32 margin_percent = 0;
int i = 0;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core || !core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
d_vpr_e("%s: invalid params\n", __func__);
return false;
}
vpp_min_freq = vpp_min_freq * 1000000; /* convert to hz */
closest_freq_upper_corner = core->freq_tbl[0].freq;
closest_freq_upper_corner =
core->resource->freq_set.freq_tbl[0].freq;
/* return true if vpp_min_freq is more than max frequency */
if (vpp_min_freq > closest_freq_upper_corner)
return true;
/* get the closest freq corner for vpp_min_freq */
for (i = 0; i < core->freq_tbl_count; i++) {
if (vpp_min_freq <= core->freq_tbl[i].freq)
closest_freq_upper_corner = core->freq_tbl[i].freq;
else
for (i = 0; i < core->resource->freq_set.count; i++) {
if (vpp_min_freq <=
core->resource->freq_set.freq_tbl[i].freq) {
closest_freq_upper_corner =
core->resource->freq_set.freq_tbl[i].freq;
} else {
break;
}
}
margin_freq = closest_freq_upper_corner - vpp_min_freq;
@@ -438,7 +429,7 @@ static u64 msm_vidc_calc_freq_iris35_new(struct msm_vidc_inst *inst, u32 data_si
ret = msm_vidc_init_codec_input_freq(inst, data_size, &codec_input);
if (ret)
return freq;
ret = msm_vidc_calculate_frequency_iris35(codec_input, &codec_output);
ret = msm_vidc_calculate_frequency(codec_input, &codec_output);
if (ret)
return freq;
@@ -482,8 +473,9 @@ static u64 msm_vidc_calc_freq_iris35_new(struct msm_vidc_inst *inst, u32 data_si
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
return freq;
@@ -502,7 +494,7 @@ static int msm_vidc_calc_bw_iris35_new(struct msm_vidc_inst *inst,
ret = msm_vidc_init_codec_input_bus(inst, vidc_data, &codec_input);
if (ret)
return ret;
ret = msm_vidc_calculate_bandwidth_iris35(codec_input, &codec_output);
ret = msm_vidc_calculate_bandwidth(codec_input, &codec_output);
if (ret)
return ret;
@@ -541,7 +533,8 @@ u64 msm_vidc_calc_freq_iris35_legacy(struct msm_vidc_inst *inst, u32 data_size)
core = inst->core;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
d_vpr_e("%s: invalid params\n", __func__);
return freq;
}
@@ -677,7 +670,7 @@ u64 msm_vidc_calc_freq_iris35_legacy(struct msm_vidc_inst *inst, u32 data_size)
freq_entry = bitrate_entry;
freq_tbl = core->freq_tbl;
freq_tbl = core->resource->freq_set.freq_tbl;
freq_tbl_value = freq_tbl[freq_entry].freq / 1000000;
input_bitrate_mbps = fps * data_size * 8 / (1024 * 1024);
@@ -759,8 +752,9 @@ u64 msm_vidc_calc_freq_iris35_legacy(struct msm_vidc_inst *inst, u32 data_size)
*/
} else {
/* limit to NOM, index 0 is TURBO, index 1 is NOM clock rate */
if (core->freq_tbl_count >= 2 && freq > core->freq_tbl[1].freq)
freq = core->freq_tbl[1].freq;
if (core->resource->freq_set.count >= 2 &&
freq > core->resource->freq_set.freq_tbl[1].freq)
freq = core->resource->freq_set.freq_tbl[1].freq;
}
return freq;
@@ -1332,7 +1326,8 @@ int msm_vidc_ring_buf_count_iris35(struct msm_vidc_inst *inst, u32 data_size)
core = inst->core;
if (!core->freq_tbl || !core->freq_tbl_count) {
if (!core->resource || !core->resource->freq_set.freq_tbl ||
!core->resource->freq_set.count) {
i_vpr_e(inst, "%s: invalid frequency table\n", __func__);
return -EINVAL;
}
@@ -1345,7 +1340,7 @@ int msm_vidc_ring_buf_count_iris35(struct msm_vidc_inst *inst, u32 data_size)
rc = msm_vidc_init_codec_input_freq(inst, data_size, &codec_input);
if (rc)
return rc;
rc = msm_vidc_calculate_frequency_iris35(codec_input, &codec_output);
rc = msm_vidc_calculate_frequency(codec_input, &codec_output);
if (rc)
return rc;