samsung_sm8750/android_kernel_samsung_sm8750-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

replace common qcom sources with samsung ones

Browse Source
This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
qcom/opensource/synx-devicetree/synx/pineapple-synx.dts Normal file
View File

@@ -0,0 +1,16 @@
/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "pineapple-synx.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>, <557 0x20000>, <577 0x10000>, <577 0x20000>;
qcom,board-id = <0 0>;
};

292
qcom/opensource/synx-devicetree/synx/pineapple-synx.dtsi Normal file
View File

@@ -0,0 +1,292 @@
/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <dt-bindings/ipclite-signals.h>
&soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ipcc_compute_l0: qcom,ipcc_compute_l0@443000 {
compatible = "qcom,ipcc";
reg = <0x443000 0x1000>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
ipclite {
compatible = "qcom,ipclite";
memory-region = <&global_sync_mem>;
hwlocks = <&tcsr_mutex 11>;
#address-cells = <1>;
#size-cells = <1>;
major_version = <1>;
minor_version = <0>;
feature_mask_low = <0x0003>;
feature_mask_high = <0x0000>;
ranges;
ipclite_apss: apss {
qcom,remote-pid = <0>;
label = "apss";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_BROADCAST
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cdsp: cdsp {
qcom,remote-pid = <5>;
label = "cdsp";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cvp: cvp {
qcom,remote-pid = <6>;
label = "cvp";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cam: cam {
qcom,remote-pid = <7>;
label = "cam";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
};
};

18
qcom/opensource/synx-devicetree/synx/sun-synx.dts Normal file
View File

@@ -0,0 +1,18 @@
/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sun-synx.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoC";
compatible = "qcom,sun";
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100026a 0x20000>,
<0x100027f 0x10000>, <0x100027f 0x20000>;
qcom,board-id = <0 0>;
};

292
qcom/opensource/synx-devicetree/synx/sun-synx.dtsi Normal file
View File

@@ -0,0 +1,292 @@
/* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <dt-bindings/ipclite-signals.h>
&soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ipcc_compute_l0: qcom,ipcc_compute_l0@443000 {
compatible = "qcom,ipcc";
reg = <0x443000 0x1000>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
ipclite {
compatible = "qcom,ipclite";
memory-region = <&global_sync_mem>;
hwlocks = <&tcsr_mutex 11>;
#address-cells = <1>;
#size-cells = <1>;
major_version = <1>;
minor_version = <0>;
feature_mask_low = <0x0003>;
feature_mask_high = <0x0000>;
ranges;
ipclite_apss: apss {
qcom,remote-pid = <0>;
label = "apss";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_BROADCAST
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cdsp: cdsp {
qcom,remote-pid = <5>;
label = "cdsp";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cvp: cvp {
qcom,remote-pid = <6>;
label = "cvp";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cam: cam {
qcom,remote-pid = <7>;
label = "cam";
ipclite_signal_0 {
index = <0>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_1 {
index = <1>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_2 {
index = <2>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_3 {
index = <3>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CAM
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
};
};