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replace common qcom sources with samsung ones

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This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
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23
qcom/opensource/mmrm-devicetree/sun/sun-mmrm-test.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-sun.h>
#include <dt-bindings/clock/qcom,evacc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include "sun-mmrm-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoC";
compatible = "qcom,sun";
qcom,msm-id = <618 0x10000>, <639 0x10000>,
<618 0x20000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100027f 0x10000>,
<0x100026a 0x20000>, <0x100027f 0x20000>;
qcom,board-id = <0 0>;
};

107
qcom/opensource/mmrm-devicetree/sun/sun-mmrm-test.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,sun-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_camnoc_rt_axi_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_icp_0_clk_src",
"cam_cc_icp_1_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_ofe_clk_src",
"cam_cc_tfe_0_clk_src",
"cam_cc_tfe_1_clk_src",
"cam_cc_tfe_2_clk_src",
"cam_cc_fast_ahb_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_cci_2_clk_src",
"cam_cc_cre_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"eva_cc_mvs0_clk_src",
"disp_cc_mdss_mdp_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_0_CLK_SRC>,
<&camcc CAM_CC_ICP_1_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_OFE_CLK_SRC>,
<&camcc CAM_CC_TFE_0_CLK_SRC>,
<&camcc CAM_CC_TFE_1_CLK_SRC>,
<&camcc CAM_CC_TFE_2_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_CRE_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&evacc EVA_CC_MVS0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
/*
* clock_data : domain, clock-ID,
* rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO,
* num_hw_blocks, hw_drv_instances, num_pwr_states
*/
clock_data =
<0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>,
<0x1 CAM_CC_ICP_0_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
<0x1 CAM_CC_ICP_1_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 1 0 0>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 475000000 575000000 675000000 825000000 825000000 1 0 0>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>,
<0x1 CAM_CC_OFE_CLK_SRC 484000000 586000000 688000000 841000000 841000000 1 0 0>,
<0x1 CAM_CC_TFE_0_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
<0x1 CAM_CC_TFE_1_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
<0x1 CAM_CC_TFE_2_CLK_SRC 480000000 630000000 716000000 833000000 833000000 1 0 0>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CRE_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 0 0>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
<0x1 EVA_CC_MVS0_CLK_SRC 1200000000 1350000000 1500000000 1650000000 1650000000 1 0 0>,
<0x1 DISP_CC_MDSS_MDP_CLK_SRC 207000000 337000000 417000000 532000000 575000000 1 0 0>,
<0x1 VIDEO_CC_MVS0_CLK_SRC 1014000000 1260000000 1332000000 1600000000 1890000000 1 0 0>;
};
};

23
qcom/opensource/mmrm-devicetree/sun/sun-mmrm.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-sun.h>
#include <dt-bindings/clock/qcom,videocc-sun.h>
#include <dt-bindings/clock/qcom,evacc-sun.h>
#include <dt-bindings/clock/qcom,dispcc-sun.h>
#include "sun-mmrm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Sun SoC";
compatible = "qcom,sun";
qcom,msm-id = <618 0x10000>, <639 0x10000>,
<618 0x20000>, <639 0x20000>,
<0x100026a 0x10000>, <0x100027f 0x10000>,
<0x100026a 0x20000>, <0x100027f 0x20000>;
qcom,board-id = <0 0>;
};

54
qcom/opensource/mmrm-devicetree/sun/sun-mmrm.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,sun-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <10000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo";
mm-rail-fact-volt = <37487 41157 44827 47711 50332 52429>;
/* Scaling factors */
scaling-fact-dyn = <39977 48497 57672 66192 74056 81265>;
scaling-fact-leak = <827720 969278 1133118 1283851 1445069 1597768>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3193177 86508 1>,
<0x1 CAM_CC_CSID_CLK_SRC 1285358 55706 3>,
<0x1 CAM_CC_ICP_0_CLK_SRC 253232 17040 1>,
<0x1 CAM_CC_ICP_1_CLK_SRC 253232 17040 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 274531 10028 2>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 50230789 394986 1>,
<0x1 CAM_CC_JPEG_CLK_SRC 551486 17040 4>,
<0x1 CAM_CC_OFE_CLK_SRC 63019221 400622 1>,
<0x1 CAM_CC_TFE_0_CLK_SRC 17560437 241435 1>,
<0x1 CAM_CC_TFE_1_CLK_SRC 17560437 241435 1>,
<0x1 CAM_CC_TFE_2_CLK_SRC 17604543 248120 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6554 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11797 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 0 656 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 0 656 1>,
<0x1 CAM_CC_CCI_2_CLK_SRC 0 656 1>,
<0x1 CAM_CC_CRE_CLK_SRC 65536 1967 1>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33424 10>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 15074 2>,
<0x2 EVA_CC_MVS0_CLK_SRC 47360246 407372 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 21561344 319816 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 29233906 839582 1>;
};
};