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replace common qcom sources with samsung ones

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This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
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20
qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm-test-v2.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-pineapple.h>
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
#include <dt-bindings/clock/qcom,dispcc-pineapple.h>
#include "pineapple-mmrm-test-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple SoC";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x20000>, <577 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

122
qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm-test-v2.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_sfe_2_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_rt_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_csi6phytimer_clk_src",
"cam_cc_csi7phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_cci_2_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"cam_cc_cre_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_SFE_0_CLK_SRC>,
<&camcc CAM_CC_SFE_1_CLK_SRC>,
<&camcc CAM_CC_SFE_2_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CRE_CLK_SRC>,
<&videocc VIDEO_CC_MVS1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
/*
* clock_data : domain, clock-ID,
* rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO,
* num_hw_blocks, hw_drv_instances, num_pwr_states
*/
clock_data =
<0x1 CAM_CC_IFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 3 3 2>,
<0x1 CAM_CC_SFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_SFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_SFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 475000000 575000000 675000000 825000000 825000000 1 0 0>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 785000000 785000000 1 0 0>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 4 0 0>,
<0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 3 2>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 3 2>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1110000000 1350000000 1500000000 1650000000 1650000000 1 0 0>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 402000000 514000000 514000000 1 0 0>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000000 270000000 540000000 810000000 810000000 1 0 0>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 900000000 1140000000 1305000000 1440000000 1600000000 1 0 0>;
};
};

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qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm-test.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-pineapple.h>
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
#include <dt-bindings/clock/qcom,dispcc-pineapple.h>
#include "pineapple-mmrm-test.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple SoC";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>, <577 0x10000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm-test.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
msm_mmrm_test: qcom,mmrm-test {
compatible = "qcom,msm-mmrm-test", "qcom,pineapple-mmrm-test";
status = "disable";
/* Clock info */
clock-names =
"cam_cc_ife_0_clk_src",
"cam_cc_ife_1_clk_src",
"cam_cc_ife_2_clk_src",
"cam_cc_csid_clk_src",
"cam_cc_sfe_0_clk_src",
"cam_cc_sfe_1_clk_src",
"cam_cc_sfe_2_clk_src",
"cam_cc_ipe_nps_clk_src",
"cam_cc_bps_clk_src",
"cam_cc_ife_lite_clk_src",
"cam_cc_jpeg_clk_src",
"cam_cc_camnoc_axi_rt_clk_src",
"cam_cc_ife_lite_csid_clk_src",
"cam_cc_icp_clk_src",
"cam_cc_cphy_rx_clk_src",
"cam_cc_csi0phytimer_clk_src",
"cam_cc_csi1phytimer_clk_src",
"cam_cc_csi2phytimer_clk_src",
"cam_cc_csi3phytimer_clk_src",
"cam_cc_csi4phytimer_clk_src",
"cam_cc_csi5phytimer_clk_src",
"cam_cc_csi6phytimer_clk_src",
"cam_cc_csi7phytimer_clk_src",
"cam_cc_cci_0_clk_src",
"cam_cc_cci_1_clk_src",
"cam_cc_cci_2_clk_src",
"cam_cc_slow_ahb_clk_src",
"cam_cc_fast_ahb_clk_src",
"cam_cc_cre_clk_src",
"video_cc_mvs1_clk_src",
"disp_cc_mdss_mdp_clk_src",
"disp_cc_mdss_dptx0_link_clk_src",
"video_cc_mvs0_clk_src";
clocks =
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_SFE_0_CLK_SRC>,
<&camcc CAM_CC_SFE_1_CLK_SRC>,
<&camcc CAM_CC_SFE_2_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_AXI_RT_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI6PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI7PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CRE_CLK_SRC>,
<&videocc VIDEO_CC_MVS1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
<&videocc VIDEO_CC_MVS0_CLK_SRC>;
/*
* clock_data : domain, clock-ID,
* rate-LOWSVS, rate-SVS, rate-SVS_L1, rate-NOM, rate-TURBO,
* num_hw_blocks, hw_drv_instances, num_pwr_states
*/
clock_data =
<0x1 CAM_CC_IFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 3 3 2>,
<0x1 CAM_CC_SFE_0_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_SFE_1_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_SFE_2_CLK_SRC 466000000 594000000 675000000 785000000 785000000 1 3 2>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 455000000 575000000 675000000 825000000 825000000 1 0 0>,
<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 785000000 785000000 1 0 0>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000 4 0 0>,
<0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 300000000 400000000 400000000 400000000 400000000 1 3 2>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000 2 0 0>,
<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000 1 0 0>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000 10 3 2>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_CCI_2_CLK_SRC 37500000 37500000 37500000 37500000 37500000 1 0 0>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000 1 0 0>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 300000000 300000000 300000000 400000000 400000000 1 0 0>,
<0x1 CAM_CC_CRE_CLK_SRC 200000000 400000000 480000000 600000000 600000000 1 0 0>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000 1 0 0>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 402000000 514000000 514000000 1 0 0>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000000 270000000 540000000 810000000 810000000 1 0 0>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 840000000 1140000000 1305000000 1440000000 1600000000 1 0 0>;
};
};

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qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,camcc-pineapple.h>
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
#include <dt-bindings/clock/qcom,dispcc-pineapple.h>
#include "pineapple-mmrm.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple SoC";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>, <557 0x20000>,
<577 0x10000>, <577 0x20000>;
qcom,board-id = <0 0>; /* required by merge_dtbs.py */
};

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qcom/opensource/mmrm-devicetree/pineapple/pineapple-mmrm.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
msm_mmrm: qcom,mmrm {
compatible = "qcom,msm-mmrm", "qcom,pineapple-mmrm";
status = "okay";
/* MMRM clock threshold */
mmrm-peak-threshold = <10000>;
/* MM Rail info */
mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "noml1", "turbo";
mm-rail-fact-volt = <38929 40633 41944 44237 49349 49349>;
/* Scaling factors */
scaling-fact-dyn = <50856 55706 59638 66847 84804 84804>;
scaling-fact-leak = <831718 890766 938410 1025967 1249903 1249903>;
/* Client info */
mmrm-client-info =
<0x1 CAM_CC_IFE_0_CLK_SRC 25563894 315884 1>,
<0x1 CAM_CC_IFE_1_CLK_SRC 25563894 315884 1>,
<0x1 CAM_CC_IFE_2_CLK_SRC 25563894 315884 1>,
<0x1 CAM_CC_CSID_CLK_SRC 2121415 56165 3>,
<0x1 CAM_CC_SFE_0_CLK_SRC 23995177 352199 1>,
<0x1 CAM_CC_SFE_1_CLK_SRC 23995177 352199 1>,
<0x1 CAM_CC_SFE_2_CLK_SRC 23995177 352199 1>,
<0x1 CAM_CC_IPE_NPS_CLK_SRC 76475209 874251 1>,
<0x1 CAM_CC_BPS_CLK_SRC 39943309 67337 1>,
<0x1 CAM_CC_IFE_LITE_CLK_SRC 1329704 29190 2>,
<0x1 CAM_CC_JPEG_CLK_SRC 778295 18351 4>,
<0x1 CAM_CC_CAMNOC_AXI_RT_CLK_SRC 8018836 158270 1>,
<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 238635 15257 2>,
<0x1 CAM_CC_ICP_CLK_SRC 329148 7590 1>,
<0x1 CAM_CC_CPHY_RX_CLK_SRC 19661 33247 10>,
<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI6PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CSI7PHYTIMER_CLK_SRC 6554 5 1>,
<0x1 CAM_CC_CCI_0_CLK_SRC 0 397 1>,
<0x1 CAM_CC_CCI_1_CLK_SRC 0 397 1>,
<0x1 CAM_CC_CCI_2_CLK_SRC 0 397 1>,
<0x1 CAM_CC_SLOW_AHB_CLK_SRC 58983 11666 1>,
<0x1 CAM_CC_FAST_AHB_CLK_SRC 32768 6492 1>,
<0x1 CAM_CC_CRE_CLK_SRC 84182 1927 1>,
<0x2 VIDEO_CC_MVS1_CLK_SRC 140136940 1283195 1>,
<0x3 DISP_CC_MDSS_MDP_CLK_SRC 14273741 213648 1>,
<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 707789 3572 1>,
<0x4 VIDEO_CC_MVS0_CLK_SRC 41008497 1926104 1>;
};
};