replace common qcom sources with samsung ones
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SaschaNes
227
qcom/opensource/mm-devicetree/bindings/hw-fence.yaml
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227
qcom/opensource/mm-devicetree/bindings/hw-fence.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/hw-fence.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HW Fence
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maintainers:
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- Grace An <quic_gracan@quicinc.com>
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- Kalyan Thota <quic_kalyant@quicinc.com>
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description: |
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HW Fence implements Linux APIs to initialize, deinitialize, register-for-signal, and
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overall manage the hw-fences, for hw-to-hw communcation between hw cores.
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properties:
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compatible:
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const: qcom,msm-hw-fence
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qcom,ipcc-reg:
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description: Registers ranges for ipcc registers.
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qcom,hw-fence-table-entries:
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description: A u32 indicating number of entries for the hw-fence table
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,hw-fence-queue-entries:
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description: A u32 indicating default number of entries for the Queues
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$ref: /schemas/types.yaml#/definitions/uint32
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hw_fence@0:
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description: Doorbell configuration to communicate with secondary vm through hypervisor.
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type: object
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properties:
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compatible:
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const: qcom,msm-hw-fence-db
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qcom,master: true
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gunyah-label:
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$ref: /schemas/types.yaml#/definitions/uint32
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peer-name:
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$ref: /schemas/types.yaml#/definitions/uint32
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hw_fence@1:
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description: |
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Carved-out memory-mapping region, to be used for mapping of global tables and
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queues used by the hw-fence driver and fence controller running in secondary vm.
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type: object
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properties:
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compatible:
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const: qcom,msm-hw-fence-mem
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qcom,master: true
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gunyah-label:
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$ref: /schemas/types.yaml#/definitions/uint32
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peer-name:
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$ref: /schemas/types.yaml#/definitions/uint32
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shared-buffer:
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,hw-fence-ipc-ver:
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description: |
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A u32 indicating ipc version. If not provided in device-tree, this is read from
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the registers.
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$ref: /schemas/types.yaml#/definitions/uint32
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soccp_controller:
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description: phandle for the soccp controller.
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$ref: /schemas/types.yaml#/definitions/phandle
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interrupts:
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description: Interrupt associated with APSS NS0 (to receive interrupts from SOCCP).
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interrupt-controller: true
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description: Mark the device node as an interrupt controller.
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'#interrupt-cells':
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description: Should be one. The first cell is interrupt number.
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const: 1
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iommus:
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description: Specifies the SID's used by this context bank.
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patternProperties:
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"qcom,hw\-fence\-client\-type\-+\w":
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description: |
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A list of four u32 describing client properties that
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override default values specified by the driver for some clients.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: number of clients for given type
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- enum:
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- 1
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- 2
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description: 1 (Tx) or 2 (Rx and Tx)
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- description: number of entries per client queue
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- enum:
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- 0
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- 1
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description: |
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bool indicating whether tx queue wr_idx update is skipped within hw fence
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driver and hfi_header->tx_wm is used instead
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"qcom,hw\-fence\-client\-type\-+\w+\-extra":
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description: |
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A list of four u32 indicating extra client queue properties.Later u32 values do not need to
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be provided to provide values for earlier u32 values.
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minItems: 1
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maxItems: 4
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: size of padding between queue table header and first queue header in bytes
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- description: size of padding between queue header(s) and first queue payload in bytes
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- description: start_index for TxQ rd_wr_index
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- enum:
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- 0
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- 1
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description: |
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bool indicating whether TxQ rd_wr_idx indexes by payloads instead of
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default dwords
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required:
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- compatible
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- qcom,ipcc-reg
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- qcom,hw-fence-table-entries
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- qcom,hw-fence-queue-entries
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- hw_fence@1
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if:
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required:
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- soccp-controller
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then:
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required:
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- iommus
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properties:
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hw_fence@0: false
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else:
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required:
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- hw_fence@0
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properties:
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- interrupts: false
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- interrupt-controller: false
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- '#interrupt-cells': false
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- iommus: false
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additionalProperties: false
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examples:
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- |
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msm_hw_fence: qcom,hw-fence {
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compatible = "qcom,msm-hw-fence";
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status = "ok";
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qcom,ipcc-reg = <0x400000 0x100000>;
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qcom,hw-fence-table-entries = <8192>;
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qcom,hw-fence-queue-entries = <800>;
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# time register
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qcom,qtime-reg = <0xC221000 0x1000>;
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# ipc version
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qcom,hw-fence-ipc-ver = <0x20003>;
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# client queues: clients_num, queues_num, queue_entries, skip_txq_wr_idx
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qcom,hw-fence-client-type-dpu = <4 2 128 0>;
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qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
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# extra client queue properties
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qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
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# haven doorbell specific
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hw_fence@0 {
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compatible = "qcom,msm-hw-fence-db";
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qcom,master;
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gunyah-label = <6>;
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peer-name = <3>;
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};
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# haven io-mem specific
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hw_fence@1 {
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compatible = "qcom,msm-hw-fence-mem";
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qcom,master;
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gunyah-label = <5>;
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peer-name = <3>;
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shared-buffer = <&hwfence_shbuf>;
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};
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};
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- |
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msm_hw_fence: qcom,hw-fence {
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compatible = "qcom,msm-hw-fence";
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status = "ok";
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# SOCCP properties
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x562 0x1>;
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soccp_controller = <&soccp_pas>;
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qcom,ipcc-reg = <0x400000 0x100000>;
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qcom,hw-fence-table-entries = <8192>;
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qcom,hw-fence-queue-entries = <800>;
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# time register
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qcom,qtime-reg = <0xC221000 0x1000>;
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# ipc version
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qcom,hw-fence-ipc-ver = <0x20003>;
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# base client queue properties
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qcom,hw-fence-client-type-dpu = <4 2 128 0>;
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qcom,hw-fence-client-type-ife2 = <3 1 64 1>;
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# extra client queue properties
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qcom,hw-fence-client-type-ife2-extra = <20 28 1 1>;
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# haven io-mem specific
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hw_fence@1 {
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compatible = "qcom,msm-hw-fence-mem";
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qcom,master;
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shared-buffer = <&hwfence_shbuf>;
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};
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};
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...
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