replace common qcom sources with samsung ones

This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions

View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/component.h>
#include <linux/delay.h>
@@ -377,10 +377,17 @@ void adreno_irqctrl(struct adreno_device *adreno_dev, int state)
*/
void adreno_hang_int_callback(struct adreno_device *adreno_dev, int bit)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
atomic_inc(&device->gpu_exception_count[GPU_HANG]);
dev_crit_ratelimited(KGSL_DEVICE(adreno_dev)->dev,
"MISC: GPU hang detected\n");
adreno_irqctrl(adreno_dev, 0);
#if IS_ENABLED(CONFIG_SEC_ABC)
sec_abc_send_event("MODULE=gpu_qc@WARN=gpu_fault");
#endif
/* Trigger a fault in the dispatcher - this will effect a restart */
adreno_scheduler_fault(adreno_dev, ADRENO_HARD_FAULT);
}
@@ -846,7 +853,6 @@ static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev,
static int register_l3_voter(struct kgsl_device *device)
{
int ret = 0;
/*
* The L3 vote setup is performed only once. Once set up is done, it is
* safe to access num_l3_pwrlevels without acquiring the device mutex.
@@ -1198,7 +1204,6 @@ static void adreno_setup_device(struct adreno_device *adreno_dev)
mutex_init(&adreno_dev->dev.mutex);
mutex_init(&adreno_dev->dev.file_mutex);
mutex_init(&adreno_dev->fault_recovery_mutex);
mutex_init(&adreno_dev->dcvs_tuning_mutex);
INIT_LIST_HEAD(&adreno_dev->dev.globals);
/* Set the fault tolerance policy to replay, skip, throttle */
@@ -1406,12 +1411,12 @@ int adreno_device_probe(struct platform_device *pdev,
/*
* Force no write allocate for A5x, A6x and all gen7 targets
* except gen_7_9_x and gen_7_14_0_family. gen_7_9_x and gen_7_14_0_family
* except gen_7_9_x and gen_7_14_0. gen_7_9_x and gen_7_14_0
* use write allocate.
*/
if (adreno_is_a5xx(adreno_dev) || adreno_is_a6xx(adreno_dev) ||
(adreno_is_gen7(adreno_dev) && !adreno_is_gen7_9_x(adreno_dev) &&
!adreno_is_gen7_14_0_family(adreno_dev)))
!adreno_is_gen7_14_0(adreno_dev)))
kgsl_mmu_set_feature(device, KGSL_MMU_FORCE_LLCC_NWA);
/* Bind the components before doing the KGSL platform probe. */
@@ -1514,7 +1519,6 @@ int adreno_device_probe(struct platform_device *pdev,
adreno_dev->pm_nb.notifier_call = adreno_pm_notifier;
register_pm_notifier(&adreno_dev->pm_nb);
}
kgsl_qcom_va_md_register(device);
KGSL_BOOT_MARKER("GPU Ready");
@@ -1709,6 +1713,7 @@ static int adreno_pm_suspend(struct device *dev)
adreno_dev = ADRENO_DEVICE(device);
ops = ADRENO_POWER_OPS(adreno_dev);
/* Return early if fault recovery is in progress */
if (!mutex_trylock(&adreno_dev->fault_recovery_mutex))
@@ -2226,7 +2231,7 @@ int adreno_reset(struct kgsl_device *device, int fault)
* the IOMMU hardware needs a reset too)
*/
if (!(fault & ADRENO_IOMMU_STALL_ON_PAGE_FAULT))
if (!(fault & ADRENO_IOMMU_PAGE_FAULT))
ret = adreno_soft_reset(device);
if (ret) {
@@ -3390,7 +3395,7 @@ bool adreno_smmu_is_stalled(struct adreno_device *adreno_dev)
fault = adreno_gpu_fault(adreno_dev);
return ((fault & ADRENO_IOMMU_STALL_ON_PAGE_FAULT) &&
return ((fault & ADRENO_IOMMU_PAGE_FAULT) &&
test_bit(KGSL_FT_PAGEFAULT_GPUHALT_ENABLE, &mmu->pfpolicy)) ? true : false;
}