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replace common qcom sources with samsung ones

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This commit is contained in:
SaschaNes
2025-08-12 22:13:00 +02:00
parent ba24dcded9
commit 6f7753de11
5682 changed files with 2450203 additions and 103634 deletions
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687
qcom/opensource/graphics-devicetree/gpu/pineapple-gpu-pwrlevels.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L1 0x882f5ffd
#define ACD_LEVEL_TURBO 0x882f5ffd
#define ACD_LEVEL_NOM_L1 0x882f5ffd
#define ACD_LEVEL_NOM 0xc0285ffd
#define ACD_LEVEL_SVS_L2 0xe0295ffd
#define ACD_LEVEL_SVS_L1 0xe0295ffd
#define ACD_LEVEL_SVS_L0 0xc02a5ffd
#define ACD_LEVEL_SVS 0xc02a5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd
#define ACD_LEVEL_LOW_SVS 0xc02f5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
qcom,speed-bin = <2>;
qcom,initial-pwrlevel = <12>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <8>;
qcom,bus-min = <8>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <4>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
qcom,initial-pwrlevel = <11>;
/* Turbo */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_0, FC_Y0)
SKU_CODE(PCODE_1, FC_Y0)
SKU_CODE(PCODE_0, FC_Y1)>;
qcom,initial-pwrlevel = <12>;
/* Turbo_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* Turbo */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <869000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <8>;
qcom,bus-min = <8>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
qcom,gpu-pwrlevels-3 {
#address-cells = <1>;
#size-cells = <0>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
qcom,initial-pwrlevel = <10>;
/* Nom_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <2>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
};
};

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qcom/opensource/graphics-devicetree/gpu/pineapple-gpu.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,pineapple.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "pineapple-gpu.dtsi"
#include "pineapple-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>, <577 0x10000>;
qcom,board-id = <0 0>;
};

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qcom/opensource/graphics-devicetree/gpu/pineapple-gpu.dtsi Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
/* External feature codes */
#define FC_UNKNOWN 0x0
#define FC_AA 0x1
#define FC_AB 0x2
#define FC_AC 0x3
#define FC_AD 0x4
/* Internal feature codes */
#define FC_Y0 0x00f1
#define FC_Y1 0x00f2
/* Pcodes */
#define PCODE_UNKNOWN 0
#define PCODE_0 1
#define PCODE_1 2
#define PCODE_2 3
#define PCODE_3 4
#define PCODE_4 5
#define PCODE_5 6
#define PCODE_6 7
#define PCODE_7 8
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
&msm_gpu {
compatible = "qcom,adreno-gpu-gen7-9-0", "qcom,kgsl-3d0";
status = "ok";
reg = <0x3d00000 0x40000>, <0x3d61000 0x3000>,
<0x03d50000 0x10000>, <0x03d9e000 0x2000>,
<0x10900000 0x80000>, <0x10048000 0x8000>,
<0x10b05000 0x1000>;
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", "cx_misc",
"qdss_gfx", "qdss_etr", "qdss_tmc";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&aoss_qmp QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb",
"apb_pclk";
qcom,gpu-model = "Adreno750";
qcom,chipid = <0x43051400>;
qcom,no-nap;
qcom,min-access-length = <32>;
qcom,ubwc-mode = <4>;
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
qcom,bus-table-cnoc =
<0>, /* Off */
<100>; /* On */
qcom,bus-table-ddr =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
<MHZ_TO_KBPS(547, 4) >, /* index=1 */
<MHZ_TO_KBPS(768, 4) >, /* index=2 */
<MHZ_TO_KBPS(1555, 4)>, /* index=3 */
<MHZ_TO_KBPS(1708, 4)>, /* index=4 */
<MHZ_TO_KBPS(2092, 4)>, /* index=5 */
<MHZ_TO_KBPS(2736, 4)>, /* index=6 */
<MHZ_TO_KBPS(3187, 4)>, /* index=7 */
<MHZ_TO_KBPS(3686, 4)>, /* index=8 */
<MHZ_TO_KBPS(4224, 4)>; /* index=9 */
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
zap-shader {
memory-region = <&gpu_micro_code_mem>;
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 128K Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <131072>;
qcom,mempool-reserved = <128>;
};
/* 256K Page Pool configuration */
qcom,gpu-mempool@4 {
reg = <4>;
qcom,mempool-page-size = <262144>;
qcom,mempool-reserved = <80>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@5 {
reg = <5>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
};
&soc {
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x03da0000 0x40000>;
vddcx-supply = <&gpu_cc_cx_gdsc>;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_lpac: gfx3d_lpac {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x1 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x2 0x000>;
qcom,iommu-dma = "disabled";
};
};
gmu: qcom,gmu@3d69000 {
compatible = "qcom,gen7-gmu";
reg = <0x3d68000 0x37000>,
<0xb280000 0x10000>,
<0x03D40000 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
<0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
regulator-names = "vddcx", "vdd";
vddcx-supply = <&gpu_cc_cx_gdsc>;
vdd-supply = <&gpu_cc_gx_gdsc>;
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
"memnoc_clk", "ahb_clk", "hub_clk";
qcom,gmu-freq-table = <260000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
<625000000 RPMH_REGULATOR_LEVEL_SVS>;
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(768, 4)>;
iommus = <&kgsl_smmu 0x5 0x000>;
qcom,iommu-dma = "disabled";
qcom,ipc-core = <0x00400000 0x140000>;
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
coresight_cx_dgbc: qcom,gpu-coresight-cx {
compatible = "qcom,gpu-coresight-cx";
coresight-name = "coresight-gfx-cx";
coresight-atid = <52>;
out-ports {
port {
cx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_cx_dbgc>;
};
};
};
};
coresight_gx_dgbc: qcom,gpu-coresight-gx {
compatible = "qcom,gpu-coresight-gx";
coresight-name = "coresight-gfx";
coresight-atid = <53>;
out-ports {
port {
gx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_gx_dbgc>;
};
};
};
};
};
&funnel_gfx {
status = "ok";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_gfx_in_gx_dbgc: endpoint {
remote-endpoint =
<&gx_dbgc_out_funnel_gfx>;
};
};
port@1 {
reg = <1>;
funnel_gfx_in_cx_dbgc: endpoint {
remote-endpoint =
<&cx_dbgc_out_funnel_gfx>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L1 0x882f5ffd
#define ACD_LEVEL_TURBO 0x882f5ffd
#define ACD_LEVEL_NOM_L1 0x882f5ffd
#define ACD_LEVEL_NOM 0xc0285ffd
#define ACD_LEVEL_SVS_L2 0xe0295ffd
#define ACD_LEVEL_SVS_L1 0xe0295ffd
#define ACD_LEVEL_SVS_L0 0xc02a5ffd
#define ACD_LEVEL_SVS 0xc02a5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc02c5ffd
#define ACD_LEVEL_LOW_SVS 0xc02f5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xc02f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
qcom,initial-pwrlevel = <11>;
/* Turbo */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <903000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <9>;
qcom,bus-min = <9>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_TURBO>;
};
/* Nom_L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <834000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* Nom */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <770000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <720000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <7>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <680000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <9>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <629000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <578000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <4>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <422000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <5>;
qcom,bus-min = <3>;
qcom,bus-max = <7>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <366000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <5>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <310000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <4>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <231000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <1>;
qcom,bus-min = <1>;
qcom,bus-max = <3>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,pineapple.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "pineapple-v2-gpu.dtsi"
#include "pineapple-v2-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x20000>, <577 0x20000>;
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "pineapple-gpu.dtsi"
&msm_gpu {
compatible = "qcom,adreno-gpu-gen7-9-1", "qcom,kgsl-3d0";
qcom,gpu-model = "Adreno750v2";
qcom,chipid = <0x43051401>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* ACD Control register values */
#define ACD_LEVEL_TURBO_L4 0x88295ffd
#define ACD_LEVEL_TURBO_L3 0x882a5ffd
#define ACD_LEVEL_TURBO_L1 0x882a5ffd
#define ACD_LEVEL_NOM_L1 0x882b5ffd
#define ACD_LEVEL_NOM 0x882b5ffd
#define ACD_LEVEL_SVS_L2 0x882b5ffd
#define ACD_LEVEL_SVS_L1 0xa82b5ffd
#define ACD_LEVEL_SVS_L0 0x882d5ffd
#define ACD_LEVEL_SVS 0xa82e5ffd
#define ACD_LEVEL_LOW_SVS_L1 0xc0285ffd
#define ACD_LEVEL_LOW_SVS 0xe02d5ffd
#define ACD_LEVEL_LOW_SVS_D0 0xe02f5ffd
#define ACD_LEVEL_LOW_SVS_D1 0xe8285ffd
#define ACD_LEVEL_LOW_SVS_D2 0xe82f5ffd
&msm_gpu {
/* Power levels */
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <10>;
qcom,initial-min-pwrlevel = <10>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AB)
SKU_CODE(PCODE_UNKNOWN, FC_AC)>;
/* NOM_L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* NOM */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <8>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <8>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <125000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,initial-pwrlevel = <13>;
qcom,initial-min-pwrlevel = <13>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_UNKNOWN)>;
/* TURBO_L4 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <1150000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L4>;
};
/* TURBO_L3 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
};
/* TURBO_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_NOM_L1>;
};
/* NOM */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_NOM>;
};
/* SVS_L2 */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <779000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <9>;
qcom,bus-min = <7>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L2>;
};
/* SVS_L1 */
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <ACD_LEVEL_SVS_L1>;
};
/* SVS_L0 */
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <8>;
qcom,acd-level = <ACD_LEVEL_SVS_L0>;
};
/* SVS */
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <4>;
qcom,bus-max = <8>;
qcom,acd-level = <ACD_LEVEL_SVS>;
};
/* Low_SVS_L1 */
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_L1>;
};
/* Low_SVS */
qcom,gpu-pwrlevel@10 {
reg = <10>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS>;
};
/* Low_SVS_D0 */
qcom,gpu-pwrlevel@11 {
reg = <11>;
qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
qcom,bus-freq = <4>;
qcom,bus-min = <2>;
qcom,bus-max = <6>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D0>;
};
/* Low_SVS_D1 */
qcom,gpu-pwrlevel@12 {
reg = <12>;
qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D1>;
};
/* Low_SVS_D2 */
qcom,gpu-pwrlevel@13 {
reg = <13>;
qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
qcom,bus-freq = <3>;
qcom,bus-min = <2>;
qcom,bus-max = <3>;
qcom,acd-level = <ACD_LEVEL_LOW_SVS_D2>;
};
/* Low_SVS_D3 */
qcom,gpu-pwrlevel@14 {
reg = <14>;
qcom,gpu-freq = <125000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
qcom,bus-freq = <2>;
qcom,bus-min = <2>;
qcom,bus-max = <2>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,gpucc-sun.h>
#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sun-gpu.dtsi"
#include "sun-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sun";
compatible = "qcom,sun";
qcom,msm-id = <0x26a 0x10000>, <0x27f 0x10000>, <0x100026a 0x10000>, <0x100027f 0x10000>;
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
/* External feature codes */
#define FC_UNKNOWN 0x0
#define FC_AA 0x1
#define FC_AB 0x2
#define FC_AC 0x3
#define FC_AD 0x4
/* Internal feature codes */
#define FC_Y0 0x00f1
#define FC_Y1 0x00f2
/* Pcodes */
#define PCODE_UNKNOWN 0
#define PCODE_0 1
#define PCODE_1 2
#define PCODE_2 3
#define PCODE_3 4
#define PCODE_4 5
#define PCODE_5 6
#define PCODE_6 7
#define PCODE_7 8
#define SKU_CODE(pcode, featurecode) ((pcode << 16) + featurecode)
&msm_gpu {
compatible = "qcom,adreno-gpu-gen8-0-0", "qcom,kgsl-3d0";
status = "ok";
reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
<0x3d61000 0x3000>, <0x3d9e000 0x2000>,
<0x10900000 0x80000>, <0x10048000 0x8000>,
<0x10b05000 0x1000>;
reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc", "cx_misc",
"qdss_gfx", "qdss_etr", "qdss_tmc";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>, <0 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq", "cx_host_irq";
clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&aoss_qmp QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gpu_cc_ahb",
"apb_pclk";
qcom,gpu-model = "Adreno830";
qcom,chipid = <0x44050000>;
qcom,min-access-length = <32>;
qcom,ubwc-mode = <5>;
qcom,gpu-qdss-stm = <0x37000000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0", "gpuss-1", "gpuss-2", "gpuss-3",
"gpuss-4", "gpuss-5", "gpuss-6", "gpuss-7";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
qcom,bus-table-cnoc =
<0>, /* Off */
<100>; /* On */
qcom,bus-table-ddr =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=2 */
<MHZ_TO_KBPS(1353, 4)>, /* LowSVS index=3 */
<MHZ_TO_KBPS(1555, 4)>, /* SVS index=4 */
<MHZ_TO_KBPS(1708, 4)>, /* SVS index=5 */
<MHZ_TO_KBPS(2092, 4)>, /* SVS index=6 */
<MHZ_TO_KBPS(2736, 4)>, /* NOM index=7 */
<MHZ_TO_KBPS(3187, 4)>, /* NOM index=8 */
<MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */
<MHZ_TO_KBPS(4224, 4)>, /* TURBO_L1 index=10 */
<MHZ_TO_KBPS(4761, 4)>; /* TURBO_L3 index=11 */
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
zap-shader {
memory-region = <&gpu_microcode_mem>;
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 128K Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <131072>;
qcom,mempool-reserved = <128>;
};
/* 256K Page Pool configuration */
qcom,gpu-mempool@4 {
reg = <4>;
qcom,mempool-page-size = <262144>;
qcom,mempool-reserved = <80>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@5 {
reg = <5>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
};
&soc {
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x3da0000 0x40000>;
power-domains = <&gpucc GPU_CC_CX_GDSC>;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_lpac: gfx3d_lpac {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x1 0x000>;
qcom,iommu-dma = "disabled";
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x2 0x000>;
qcom,iommu-dma = "disabled";
};
};
gmu: qcom,gmu@3d37000 {
compatible = "qcom,gen8-gmu";
reg = <0x3d37000 0x68000>,
<0x3d40000 0x10000>;
reg-names = "gmu", "gmu_ao_blk_dec0";
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
<0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
power-domains = <&gpucc GPU_CC_CX_GDSC>,
<&gpucc GPU_CC_CX_GMU_GDSC>,
<&gxclkctl GX_CLKCTL_GX_GDSC>;
power-domain-names = "cx", "gmu_cx", "gx";
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
<&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_HUB_CX_INT_CLK>;
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
"memnoc_clk", "ahb_clk", "hub_clk";
qcom,gmu-freq-table = <500000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
<650000000 RPMH_REGULATOR_LEVEL_SVS>;
qcom,gmu-perf-ddr-bw = <MHZ_TO_KBPS(1555, 4)>;
iommus = <&kgsl_smmu 0x5 0x000>;
qcom,iommu-dma = "disabled";
qcom,ipc-core = <0x00400000 0x140000>;
qcom,soccp-controller = <&soccp_pas>;
qcom,qmp = <&aoss_qmp>;
};
coresight_cx_dgbc: qcom,gpu-coresight-cx {
compatible = "qcom,gpu-coresight-cx";
coresight-name = "coresight-gfx-cx";
out-ports {
port {
cx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_cx_dbgc>;
};
};
};
};
coresight_gx_dgbc: qcom,gpu-coresight-gx {
compatible = "qcom,gpu-coresight-gx";
coresight-name = "coresight-gfx";
out-ports {
port {
gx_dbgc_out_funnel_gfx: endpoint {
remote-endpoint =
<&funnel_gfx_in_gx_dbgc>;
};
};
};
};
};
&funnel_gfx {
status = "ok";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_gfx_in_gx_dbgc: endpoint {
remote-endpoint =
<&gx_dbgc_out_funnel_gfx>;
};
};
port@1 {
reg = <1>;
funnel_gfx_in_cx_dbgc: endpoint {
remote-endpoint =
<&cx_dbgc_out_funnel_gfx>;
};
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/clock/qcom,gpucc-sun.h>
#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sun.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sun-v2-gpu.dtsi"
#include "sun-v2-gpu-pwrlevels.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sun";
compatible = "qcom,sun";
qcom,msm-id = <0x26a 0x20000>, <0x27f 0x20000>, <0x100026a 0x20000>, <0x100027f 0x20000>;
qcom,board-id = <0 0>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "sun-gpu.dtsi"
&msm_gpu {
compatible = "qcom,adreno-gpu-gen8-0-1", "qcom,kgsl-3d0";
qcom,gpu-model = "Adreno830v2";
qcom,chipid = <0x44050001>;
};