replace common qcom sources with samsung ones

qcom/opensource/dsp-devicetree/Kbuild

@@ -0,0 +1,34 @@
+ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+ifeq ($(CONFIG_ARCH_QTI_VM), y)
+dtbo-y += pineapple/pineapple-dsp-trustedvm.dtbo
+else
+dtbo-y += pineapple/pineapple-dsp.dtbo
+endif
+endif
+
+ifeq ($(CONFIG_ARCH_BLAIR), y)
+dtbo-y += blair/blair-dsp.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_SUN), y)
+ifeq ($(CONFIG_ARCH_QTI_VM), y)
+dtbo-y += sun/sun-dsp-trustedvm.dtbo
+else
+dtbo-y += sun/sun-dsp.dtbo
+endif
+endif
+
+ifeq ($(CONFIG_ARCH_MONACO), y)
+dtbo-y += monaco/monaco-dsp.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_PARROT), y)
+dtbo-y += parrot/parrot-dsp.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_RAVELIN), y)
+dtbo-y += ravelin/ravelin-dsp.dtbo
+endif
+always-y	:= $(dtb-y) $(dtbo-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb *.dtbo

qcom/opensource/dsp-devicetree/Makefile

@@ -0,0 +1,9 @@
+KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
+
+all: dtbs
+
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
+
+%:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)

qcom/opensource/dsp-devicetree/bindings/msm-cdsp-loader.txt

@@ -0,0 +1,16 @@
+Qualcomm Technologies, Inc. CDSP Loader Driver
+
+msm-cdsp-loader driver implements a mechanism to load the Compute DSP firmware images.
+
+Required properties:
+
+ - compatible:  This must be "qcom,msm-cdsp-loader".
+ - qcom,proc-img-to-load: CDSP firmware name, must be "cdsp".
+
+Example:
+ The following is an example:
+
+	qcom,msm-cdsp-loader {
+		compatible = "qcom,cdsp-loader";
+		qcom,proc-img-to-load = "cdsp";
+	};

qcom/opensource/dsp-devicetree/bindings/msm-fastrpc.txt

@@ -0,0 +1,105 @@
+Qualcomm Technologies, Inc. FastRPC Driver
+
+The MSM FastRPC driver implements an IPC (Inter-Processor Communication)
+mechanism that allows for clients to transparently make remote method
+invocations across DSP and APPS boundaries. This enables developers
+to offload tasks to the DSP and free up the application processor for
+other tasks.
+
+Required properties:
+- compatible :	Must be one of "qcom,msm-fastrpc-adsp" or "qcom,msm-fastrpc-compute"
+
+Optional properties:
+- qcom,rpc-latency-us		:	FastRPC QoS latency vote
+- qcom,adsp-remoteheap-vmid	:	FastRPC remote heap VMID list
+- qcom,secure-context-bank	:	Bool indicating secure FastRPC context bank.
+- qcom,fastrpc-legacy-remote-heap	:	Bool indicating hypervisor is not supported.
+- qcom,fastrpc-adsp-audio-pdr		:	Flag to enable ADSP Audio PDR
+- qcom,secure-domains		:	FastRPC secure domain configuration
+- qcom,fastrpc-adsp-sensors-pdr		:	Flag to enable Sensors PDR
+- qcom,single-core-latency-vote		:	Limit FastRPC PM QoS to only vote for 1
+						lowest capacity core
+
+Optional subnodes:
+- qcom,msm_fastrpc_compute_cb	:	Child nodes representing the compute context banks
+- qcom,msm-fastrpc-rpmsg		:	Child node for rpmsg instead of glink for IPC
+
+Subnode Required properties:
+- compatible	:	Must be "qcom,msm-fastrpc-compute-cb"
+- label			:	Label describing the channel this context bank belongs to
+- iommus		:	A list of phandle and IOMMU specifier pairs that describe the
+					IOMMU master interfaces of the device
+- dma-coherent	:	A flag marking a context bank as I/O coherent
+- shared-cb		:	A value indicating how many fastrpc sessions can share a
+					context bank
+- pd-type		:	A value indicating remote subsystem proess type
+- alloc-size-range:	A pair values indicating the allocation size range
+						of context bank
+
+Example:
+	qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,fastrpc-rpmsg;
+		qcom,rpc-latency-us = <235>;
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-sensors-pdr;
+
+		qcom,msm_fastrpc_rpmsg {
+			compatible = "qcom,msm-fastrpc-rpmsg";
+			qcom,glink-channels = "fastrpcglink-apps-dsp";
+			intents = <0x64 64>;
+		};
+
+		qcom,msm_fastrpc_compute_cb_1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1401 0x0>;
+			dma-coherent;
+		};
+		qcom,msm_fastrpc_compute_cb_2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "sdsprpc-smd";
+			iommus = <&apps_smmu 0x1402 0x0>;
+			shared-cb = <5>;
+		};
+	};
+
+Legacy SMMU v1/v2:
+
+Required properties:
+- compatible	:	Must be "qcom,msm-fastprc-legacy-compute-cb"
+
+Required subnode:
+- qcom,msm_fastrpc_compute_cb	:	Child nodes representing the compute context
+									banks
+
+Required subnode properties:
+- qcom,adsp-shared-phandle	:	phandle that describe the context bank handle
+- qcom,adsp-shared-sids		:	A list of SID associated with the context bank
+- qcom,virtual-addr-pool	:	Virtual address range that the context bank
+								will be using
+
+Example:
+        qcom,adsprpc_domains {
+                compatible = "qcom,msm-fastrpc-legacy-compute-cb";
+                qcom,msm_fastrpc_compute_cb {
+                       qcom,adsp-shared-phandle = <&adsp_shared>;
+                       qcom,adsp-shared-sids = <0x8 0x9>;
+                       qcom,virtual-addr-pool = <0x80000000 0x7FFFFFFF>;
+                };
+        };
+
+Remote Heap:
+
+Required properties:
+- compatible		:	Must be "qcom,msm-adsprpc-mem-region"
+- memory-region		:	CMA region which is owned by this device
+- restrict-access	:	Blocking vote for hyp_assign_phys function call
+
+Example:
+       qcom,adsprpc-mem {
+               compatible = "qcom,msm-adsprpc-mem-region";
+               memory-region = <&adsp_mem>;
+               restrict-access;
+       };

qcom/opensource/dsp-devicetree/blair/blair-dsp.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "blair-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. blair v1 SoC";
+	compatible = "qcom,blair";
+	qcom,msm-id = <507 0x10000>, <578 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/blair/blair-dsp.dtsi

@@ -0,0 +1,132 @@
+&remoteproc_adsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x00A3 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x00A4 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x00A5 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,nsessions = <8>;
+			dma-coherent;
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x00A6 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x00A7 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <611>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			iommus = <&apps_smmu 0x1001 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			iommus = <&apps_smmu 0x1002 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1003 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1004 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1005 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1006 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1009 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			dma-coherent;
+		};
+	};
+};

qcom/opensource/dsp-devicetree/kera/kera-dsp-trustedvm.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "kera-dsp-trustedvm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera - TrustedVM";
+	compatible = "qcom,kera";
+	qcom,msm-id = <659 0x10000>;
+};

qcom/opensource/dsp-devicetree/kera/kera-dsp-trustedvm.dtsi

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	fastrpc_gen_pool_region: fastrpc_gen_pool_region {
+		iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>;
+	};
+
+	fastrpc_compute_cb1: compute-cb@13 {
+		compatible = "qcom,fastrpc-compute-cb";
+		reg = <11>;
+		iommus = <&apps_smmu 0xC0B 0x0>;
+		memory-region = <&fastrpc_gen_pool_region>;
+		qcom,iommu-faults = "stall-disable", "HUPCF";
+		dma-coherent;
+		qcom,iova-best-fit;
+		qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+		qrtr-gen-pool = <&fastrpc_compute_cb1>;
+		frpc-gen-addr-pool = <0x8000 0x9000>;
+		pd-type = <4>;	/* SECURE_STATICPD */
+	};
+
+	qrtr-genpool {
+		compatible = "qcom,qrtr-genpool";
+		gen-pool = <&fastrpc_compute_cb1>;
+		interrupt-parent = <&ipcc_mproc_ns1>;
+		interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
+				<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
+				<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
+	};
+};

qcom/opensource/dsp-devicetree/kera/kera-dsp.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "kera-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kera v1 SoC";
+	compatible = "qcom,kera";
+	qcom,msm-id = <659 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/kera/kera-dsp.dtsi

@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&remoteproc_adsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1003 0x0080>,
+				 <&apps_smmu 0x1043 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1004 0x0080>,
+				 <&apps_smmu 0x1044 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,nsessions = <8>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1005 0x0080>,
+				 <&apps_smmu 0x1045 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1006 0x0080>,
+				 <&apps_smmu 0x1046 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <5>;	/* OIS_STATICPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1007 0x0040>,
+				 <&apps_smmu 0x1067 0x0000>,
+				 <&apps_smmu 0x1087 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x1008 0x0080>,
+				 <&apps_smmu 0x1048 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <235>;
+		qcom,single-core-latency-vote;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			iommus = <&apps_smmu 0x0C01 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			iommus = <&apps_smmu 0x0C02 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x0C03 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x0C04 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x0C05 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x0C06 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@7 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x0C07 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@8 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x0C08 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x0C09 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			qcom,nsessions = <3>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <6>;	/* CPZ_USERPD */
+		};
+
+		compute-cb@10 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <12>;
+			iommus = <&apps_smmu 0x0C0C 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@11 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <13>;
+			iommus = <&apps_smmu 0x0C0D 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@12 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <14>;
+			iommus = <&apps_smmu 0x0C0E 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+	};
+};

qcom/opensource/dsp-devicetree/monaco/monaco-dsp.dts

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "monaco-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Monaco SoC";
+	compatible = "qcom,monaco";
+	qcom,msm-id = <486 0x10000>, <517 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/monaco/monaco-dsp.dtsi

@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&glink_edge {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x01C3 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x01C4 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+			qcom,nsessions = <5>;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x01C5 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x01C6 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x01C7 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable";
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};

qcom/opensource/dsp-devicetree/parrot/parrot-dsp.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+/plugin/;
+
+#include "parrot-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. parrot v1 SoC";
+	compatible = "qcom,parrot";
+	qcom,msm-id = <537 0x10000>, <613 0x10000>, <663 0x10000>, <633 0x10000>, <583 0x10000>, <631 0x10000>, <634 0x10000>, <638 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/parrot/parrot-dsp.dtsi

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+&glink_edge {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1803 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <1>;
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1804 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+                        pd-type = <2>;
+		};
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1805 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+                        qcom,nsessions = <5>;
+			pd-type = <3>;
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <235>;
+
+                qcom,qos-cores = <0 1 2 3>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1401 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			pd-type = <1>;
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1402 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1403 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1404 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1405 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1406 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@7 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1407 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@8 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x1408 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			label = "cdsprpc-smd";
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1409 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;
+			dma-coherent;
+
+			pd-type = <6>;
+		};
+
+		compute-cb@10 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <11>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x140B 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <7>;
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@11 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <12>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x140C 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <9>;
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@12 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <13>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x140D 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <9>;
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@13 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <14>;
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x140E 0x0400>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+
+			qcom,iova-max-align-shift = <9>;
+			pd-type = <9>;
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+	};
+};

qcom/opensource/dsp-devicetree/pineapple/pineapple-dsp-trustedvm.dts

@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "pineapple-dsp-trustedvm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Pineapple - TrustedVM";
+	compatible = "qcom,pineapple";
+	qcom,msm-id = <557 0x10000>;
+};

qcom/opensource/dsp-devicetree/pineapple/pineapple-dsp-trustedvm.dtsi

@@ -0,0 +1,33 @@
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	msm_fastrpc: qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,rpc-latency-us = <235>;
+		qcom,fastrpc-gids = <2908>;
+		qcom,qos-cores = <0 1 2 3>;
+
+		fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0xC0B 0x0>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qrtr-gen-pool = <&fastrpc_compute_cb1>;
+			frpc-gen-addr-pool = <0x8000 0x9000>;
+			pd-type = <4>;	/* SECURE_STATICPD */
+		};
+	};
+
+	qrtr-genpool {
+		compatible = "qcom,qrtr-genpool";
+		gen-pool = <&fastrpc_compute_cb1>;
+		interrupt-parent = <&ipcc_mproc_ns1>;
+		interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
+				<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
+				<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
+	};
+};

qcom/opensource/dsp-devicetree/pineapple/pineapple-dsp.dts

@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interconnect/qcom,pineapple.h>
+#include <dt-bindings/clock/qcom,videocc-pineapple.h>
+#include <dt-bindings/clock/qcom,gcc-pineapple.h>
+#include "pineapple-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. pineapple v1 SoC";
+	compatible = "qcom,pineapple";
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/pineapple/pineapple-dsp.dtsi

@@ -0,0 +1,225 @@
+&glink_edge {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1003 0x0080>,
+				 <&apps_smmu 0x1043 0x0020>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1004 0x0080>,
+				 <&apps_smmu 0x1044 0x0020>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,nsessions = <8>;
+			dma-coherent;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1005 0x0080>,
+				 <&apps_smmu 0x1045 0x0020>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1006 0x0080>,
+				 <&apps_smmu 0x1046 0x0020>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1007 0x0040>,
+				 <&apps_smmu 0x1067 0x0000>,
+				 <&apps_smmu 0x1087 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <235>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			iommus = <&apps_smmu 0x1961 0x0000>,
+				 <&apps_smmu 0x0C01 0x0020>,
+				 <&apps_smmu 0x19C1 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			iommus = <&apps_smmu 0x1962 0x0000>,
+				 <&apps_smmu 0x0C02 0x0020>,
+				 <&apps_smmu 0x19C2 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1963 0x0000>,
+				 <&apps_smmu 0x0C03 0x0020>,
+				 <&apps_smmu 0x19C3 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1964 0x0000>,
+				 <&apps_smmu 0x0C04 0x0020>,
+				 <&apps_smmu 0x19C4 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1965 0x0000>,
+				 <&apps_smmu 0x0C05 0x0020>,
+				 <&apps_smmu 0x19C5 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1966 0x0000>,
+				 <&apps_smmu 0x0C06 0x0020>,
+				 <&apps_smmu 0x19C6 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@7 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1967 0x0000>,
+				 <&apps_smmu 0x0C07 0x0020>,
+				 <&apps_smmu 0x19C7 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@8 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x1968 0x0000>,
+				 <&apps_smmu 0x0C08 0x0020>,
+				 <&apps_smmu 0x19C8 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1969 0x0000>,
+				 <&apps_smmu 0x0C09 0x0020>,
+				 <&apps_smmu 0x19C9 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			qcom,nsessions = <3>;
+			dma-coherent;
+			pd-type = <6>;	/* CPZ_USERPD */
+		};
+
+		compute-cb@10 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <12>;
+			iommus = <&apps_smmu 0x196C 0x0000>,
+				 <&apps_smmu 0x0C0C 0x0020>,
+				 <&apps_smmu 0x19CC 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@11 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <13>;
+			iommus = <&apps_smmu 0x196D 0x0000>,
+				 <&apps_smmu 0x0C0D 0x0020>,
+				 <&apps_smmu 0x19CD 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@12 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <14>;
+			iommus = <&apps_smmu 0x196E 0x0000>,
+				 <&apps_smmu 0x0C0E 0x0020>,
+				 <&apps_smmu 0x19CE 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x10000000 0xF0000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};

qcom/opensource/dsp-devicetree/ravelin/ravelin-dsp.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+/dts-v1/;
+/plugin/;
+
+#include "ravelin-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. ravelin v1 SoC";
+	compatible = "qcom,ravelin";
+	qcom,msm-id = <568 0x10000>, <602 0x10000>, <654 0x10000>, <653 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/ravelin/ravelin-dsp.dtsi

@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+&glink_edge {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1003 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1004 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,nsessions = <4>;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x1005 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+	};
+};

qcom/opensource/dsp-devicetree/sun/sun-dsp-trustedvm.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-dsp-trustedvm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun - TrustedVM";
+	compatible = "qcom,sun";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+			<0x100026a 0x10000>, <0x100026a 0x20000>,
+			<0x100027f 0x10000>, <0x100027f 0x20000>;
+};

qcom/opensource/dsp-devicetree/sun/sun-dsp-trustedvm.dtsi

@@ -0,0 +1,32 @@
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	fastrpc_gen_pool_region: fastrpc_gen_pool_region {
+		iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>;
+	};
+
+	fastrpc_compute_cb1: compute-cb@13 {
+		compatible = "qcom,fastrpc-compute-cb";
+		reg = <11>;
+		iommus = <&apps_smmu 0xC0B 0x0>;
+		memory-region = <&fastrpc_gen_pool_region>;
+		qcom,iommu-faults = "stall-disable", "HUPCF";
+		dma-coherent;
+		qcom,iova-best-fit;
+		qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+		qrtr-gen-pool = <&fastrpc_compute_cb1>;
+		frpc-gen-addr-pool = <0x8000 0x9000>;
+		pd-type = <4>;	/* SECURE_STATICPD */
+	};
+
+	qrtr-genpool {
+		compatible = "qcom,qrtr-genpool";
+		gen-pool = <&fastrpc_compute_cb1>;
+		interrupt-parent = <&ipcc_mproc_ns1>;
+		interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
+				<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
+				<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
+	};
+};

qcom/opensource/dsp-devicetree/sun/sun-dsp.dts

@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include "sun-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. sun v1 SoC";
+	compatible = "qcom,sun";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+                        <0x100026a 0x10000>, <0x100026a 0x20000>,
+                        <0x100027f 0x10000>, <0x100027f 0x20000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/sun/sun-dsp.dtsi

@@ -0,0 +1,267 @@
+&remoteproc_adsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1003 0x0080>,
+				 <&apps_smmu 0x1043 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1004 0x0080>,
+				 <&apps_smmu 0x1044 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,nsessions = <8>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1005 0x0080>,
+				 <&apps_smmu 0x1045 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1006 0x0080>,
+				 <&apps_smmu 0x1046 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <5>;	/* OIS_STATICPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1007 0x0040>,
+				 <&apps_smmu 0x1067 0x0000>,
+				 <&apps_smmu 0x1087 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x1008 0x0080>,
+				 <&apps_smmu 0x1048 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <235>;
+		qcom,single-core-latency-vote;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			iommus = <&apps_smmu 0x19C1 0x0000>,
+				 <&apps_smmu 0x0C21 0x0000>,
+				 <&apps_smmu 0x0C01 0x0040>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			iommus = <&apps_smmu 0x1962 0x0000>,
+				 <&apps_smmu 0x0C02 0x0020>,
+				 <&apps_smmu 0x0C42 0x0000>,
+				 <&apps_smmu 0x19C2 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1963 0x0000>,
+				 <&apps_smmu 0x0C23 0x0000>,
+				 <&apps_smmu 0x0C03 0x0040>,
+				 <&apps_smmu 0x19C3 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1964 0x0000>,
+				 <&apps_smmu 0x0C24 0x0000>,
+				 <&apps_smmu 0x0C04 0x0040>,
+				 <&apps_smmu 0x19C4 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1965 0x0000>,
+				 <&apps_smmu 0x0C25 0x0000>,
+				 <&apps_smmu 0x0C05 0x0040>,
+				 <&apps_smmu 0x19C5 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1966 0x0000>,
+				 <&apps_smmu 0x0C06 0x0020>,
+				 <&apps_smmu 0x0C46 0x0000>,
+				 <&apps_smmu 0x19C6 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@7 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1967 0x0000>,
+				 <&apps_smmu 0x0C27 0x0000>,
+				 <&apps_smmu 0x0C07 0x0040>,
+				 <&apps_smmu 0x19C7 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@8 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x1968 0x0000>,
+				 <&apps_smmu 0x0C08 0x0020>,
+				 <&apps_smmu 0x0C48 0x0000>,
+				 <&apps_smmu 0x19C8 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x1969 0x0000>,
+				 <&apps_smmu 0x0C29 0x0000>,
+				 <&apps_smmu 0x0C09 0x0040>,
+				 <&apps_smmu 0x19C9 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			qcom,nsessions = <3>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <6>;	/* CPZ_USERPD */
+		};
+
+		compute-cb@10 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <12>;
+			iommus = <&apps_smmu 0x196C 0x0000>,
+				 <&apps_smmu 0x0C2C 0x0000>,
+				 <&apps_smmu 0x0C0C 0x0040>,
+				 <&apps_smmu 0x19CC 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@11 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <13>;
+			iommus = <&apps_smmu 0x196D 0x0000>,
+				 <&apps_smmu 0x0C0D 0x0020>,
+				 <&apps_smmu 0x0C2E 0x0000>,
+				 <&apps_smmu 0x0C4D 0x0000>,
+				 <&apps_smmu 0x19CD 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@12 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <14>;
+			iommus = <&apps_smmu 0x196E 0x0000>,
+				 <&apps_smmu 0x0C0E 0x0040>,
+				 <&apps_smmu 0x19CE 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+	};
+};

qcom/opensource/dsp-devicetree/tuna/tuna-dsp-trustedvm.dts

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "tuna-dsp-trustedvm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Tuna - TrustedVM";
+	compatible = "qcom,tuna";
+	qcom,msm-id = <655 0x10000>;
+};

qcom/opensource/dsp-devicetree/tuna/tuna-dsp-trustedvm.dtsi

@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	fastrpc_gen_pool_region: fastrpc_gen_pool_region {
+		iommu-addresses = <&fastrpc_compute_cb1 0x8000 0x11000>;
+	};
+
+	fastrpc_compute_cb1: compute-cb@13 {
+		compatible = "qcom,fastrpc-compute-cb";
+		reg = <11>;
+		iommus = <&apps_smmu 0xC0B 0x0>;
+		memory-region = <&fastrpc_gen_pool_region>;
+		qcom,iommu-faults = "stall-disable", "HUPCF";
+		dma-coherent;
+		qcom,iova-best-fit;
+		qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+		qrtr-gen-pool = <&fastrpc_compute_cb1>;
+		frpc-gen-addr-pool = <0x8000 0x9000>;
+		pd-type = <4>;	/* SECURE_STATICPD */
+	};
+
+	qrtr-genpool {
+		compatible = "qcom,qrtr-genpool";
+		gen-pool = <&fastrpc_compute_cb1>;
+		interrupt-parent = <&ipcc_mproc_ns1>;
+		interrupts = <IPCC_CLIENT_CDSP 0 IRQ_TYPE_EDGE_RISING>,
+				<IPCC_CLIENT_CDSP 1 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 0>,
+				<&ipcc_mproc_ns1 IPCC_CLIENT_CDSP 1>;
+	};
+};

qcom/opensource/dsp-devicetree/tuna/tuna-dsp.dts

@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "tuna-dsp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Tuna v1 SoC";
+	compatible = "qcom,tuna";
+	qcom,msm-id = <655 0x10000>;
+	qcom,board-id = <0 0>;
+};

qcom/opensource/dsp-devicetree/tuna/tuna-dsp.dtsi

@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&remoteproc_adsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "adsp";
+		memory-region = <&adsp_mem_heap>;
+		qcom,vmids = <22 37>;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x1003 0x0080>,
+				 <&apps_smmu 0x1043 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x1004 0x0080>,
+				 <&apps_smmu 0x1044 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,nsessions = <8>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <3>;	/* SENSORS_STATICPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x1005 0x0080>,
+				 <&apps_smmu 0x1045 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <2>;	/* AUDIO_STATICPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x1006 0x0080>,
+				 <&apps_smmu 0x1046 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <5>;	/* OIS_STATICPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x1007 0x0040>,
+				 <&apps_smmu 0x1067 0x0000>,
+				 <&apps_smmu 0x1087 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x1008 0x0080>,
+				 <&apps_smmu 0x1048 0x0020>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+	};
+};
+
+&remoteproc_cdsp_glink {
+	qcom,fastrpc {
+		compatible = "qcom,fastrpc";
+		qcom,glink-channels = "fastrpcglink-apps-dsp";
+		qcom,intents = <0x64 64>;
+		label = "cdsp";
+		qcom,fastrpc-gids = <2908>;
+		qcom,rpc-latency-us = <235>;
+		qcom,single-core-latency-vote;
+
+		compute-cb@1 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <1>;
+			iommus = <&apps_smmu 0x0C01 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <1>;	/* ROOT_PD */
+		};
+
+		compute-cb@2 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <2>;
+			iommus = <&apps_smmu 0x0C02 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@3 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <3>;
+			iommus = <&apps_smmu 0x0C03 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@4 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <4>;
+			iommus = <&apps_smmu 0x0C04 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <7>;	/* USERPD */
+		};
+
+		compute-cb@5 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <5>;
+			iommus = <&apps_smmu 0x0C05 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@6 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <6>;
+			iommus = <&apps_smmu 0x0C06 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x4000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@7 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <7>;
+			iommus = <&apps_smmu 0x0C07 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@8 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <8>;
+			iommus = <&apps_smmu 0x0C08 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x1000000 0xFFFFFFFF>;
+		};
+
+		compute-cb@9 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <9>;
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x0C09 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
+			qcom,nsessions = <3>;
+			dma-coherent;
+			qcom,iova-best-fit;
+			pd-type = <6>;	/* CPZ_USERPD */
+		};
+
+		compute-cb@10 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <12>;
+			iommus = <&apps_smmu 0x0C0C 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@11 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <13>;
+			iommus = <&apps_smmu 0x0C0D 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+
+		compute-cb@12 {
+			compatible = "qcom,fastrpc-compute-cb";
+			reg = <14>;
+			iommus = <&apps_smmu 0x0C0E 0x0000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+			qcom,iova-best-fit;
+			qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/
+			pd-type = <9>;	/* USER_UNSIGNEDPD_POOL */
+			alloc-size-range = <0x0 0xFFFFFFFF>;
+		};
+	};
+};