replace common qcom sources with samsung ones
This commit is contained in:
SaschaNes
38
qcom/opensource/display-devicetree/Kbuild
Normal file
38
qcom/opensource/display-devicetree/Kbuild
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@@ -0,0 +1,38 @@
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ifeq ($(CONFIG_DISPLAY_SAMSUNG), n)
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ifneq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \
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display/sun-sde-display-cdp-overlay.dtbo \
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display/sun-sde-display-mtp-overlay.dtbo \
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display/sun-sde-display-rumi-overlay.dtbo \
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display/sun-sde-display-rcm-overlay.dtbo \
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display/sun-sde-display-qrd-sku1-overlay.dtbo \
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display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \
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display/sun-sde-display-qrd-sku2-v8-overlay.dtbo \
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display/sun-sde-display-cdp-kiwi-overlay.dtbo \
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display/sun-sde-display-mtp-kiwi-overlay.dtbo \
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display/sun-sde-display-cdp-kiwi-v8-overlay.dtbo \
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display/sun-sde-display-mtp-kiwi-v8-overlay.dtbo \
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display/sun-sde-display-cdp-nfc-overlay.dtbo \
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display/sun-sde-display-mtp-nfc-overlay.dtbo \
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display/sun-sde-display-cdp-v8-overlay.dtbo \
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display/sun-sde-display-mtp-v8-overlay.dtbo \
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display/sun-sde-display-atp-overlay.dtbo \
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display/sun-sde-display-mtp-3-5mm-overlay.dtbo \
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display/sun-sde-display-rcm-kiwi-overlay.dtbo \
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display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \
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display/sun-sde-display-rcm-v8-overlay.dtbo \
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display/sun-sde-display-mtp-qmp1000-overlay.dtbo \
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display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo \
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display/sun-sde-display-hdk-overlay.dtbo \
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display/sun-sde-display-cdp-no-display-overlay.dtbo
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else
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dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \
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display/trustedvm-sun-sde-display-mtp-overlay.dtbo \
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display/trustedvm-sun-sde-display-qrd-overlay.dtbo
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endif
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endif
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always-y := $(dtb-y) $(dtbo-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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9
qcom/opensource/display-devicetree/Makefile
Normal file
9
qcom/opensource/display-devicetree/Makefile
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@@ -0,0 +1,9 @@
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KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
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all: dtbs
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clean:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
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%:
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$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
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226
qcom/opensource/display-devicetree/bindings/dsi.yaml
Normal file
226
qcom/opensource/display-devicetree/bindings/dsi.yaml
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@@ -0,0 +1,226 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies Inc. Snapdragon DSI Controller output
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description: >
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/graph.txt
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[3] Documentation/devicetree/bindings/media/video-interfaces.txt
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[4] Documentation/devicetree/bindings/display/panel/
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maintainers:
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- Vara Reddy <quic_varar@quicinc.com>
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- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
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properties:
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compatible:
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const: qcom,mdss-dsi-ctrl
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reg:
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description: Physical base address and length of the registers of controller
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reg-names:
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description: The names of register regions.
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required:
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- "dsi_ctrl"
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interrupts:
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description: The interrupt signal from the DSI block.
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power-domains:
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const: <&mmcc MDSS_GDSC>
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clocks:
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description: Phandles to device clocks.
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$ref: /schemas/types.yaml#/definitions/phandle
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clock-names:
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description: >
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Clocks necessary for DSI operation. For DSIv2, we need an additional clock "src" and for
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DSI6G v2.0 onwards, we also need the clock "byte_intf".
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required:
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- "mdp_core"
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- "iface"
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- "bus"
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- "core_mmss"
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- "byte"
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- "pixel"
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- "core"
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assigned-clocks:
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description: Parents of "byte" and "pixel" for the given platform.
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assigned-clock-parents:
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description: >
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The Byte clock and Pixel clock PLL outputs provided
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by a DSI PHY block. See [1] for details on clock bindings.
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vdd-supply:
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description: phandle to vdd regulator device node
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$ref: /schemas/types.yaml#/definitions/phandle
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vddio-supply:
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description: phandle to vdd-io regulator device node
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$ref: /schemas/types.yaml#/definitions/phandle
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vdda-supply:
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description: phandle to vdda regulator device node
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$ref: /schemas/types.yaml#/definitions/phandle
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phys:
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description: phandle to DSI PHY device node
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$ref: /schemas/types.yaml#/definitions/phandle
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phy-names:
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description: the name of the corresponding PHY device
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$ref: /schemas/types.yaml#/definitions/string-array
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syscon-sfpb:
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description: A phandle to mmss_sfpb syscon node (only for DSIv2)
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$ref: /schemas/types.yaml#/definitions/phandle
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panel@0:
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description: >
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Node of panel connected to this DSI controller.
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See files in [4] for each supported panel.
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qcom,dual-dsi-mode:
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description: >
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Boolean value indicating if the DSI controller is
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driving a panel which needs 2 DSI links.
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qcom,master-dsi:
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description: >
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Boolean value indicating if the DSI controller is driving
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the master link of the 2-DSI panel.
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qcom,sync-dual-dsi:
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description: >
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Boolean value indicating if the DSI controller is
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driving a 2-DSI panel whose 2 links need receive command simultaneously.
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pinctrl-names:
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description: the pin control state names; should contain "default"
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pinctrl-0:
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description: the default pinctrl state (active)
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pinctrl-n:
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description: the "sleep" pinctrl state
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qcom,dsi-ctrl-shared:
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description: >
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Boolean value indicating if the DSI controller is
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shared between dual displays.
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- power-domains
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- clocks
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- clock-names
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- assigned-clocks
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- assigned-clock-parents
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- vdd-supply
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- vddio-supply
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- vdda-supply
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- phys
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- phy-names
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- syscon-sfpb
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- ports
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examples:
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- |
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dsi0: dsi@fd922800 {
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compatible = "qcom,mdss-dsi-ctrl";
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qcom,dsi-host-index = <0>;
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interrupt-parent = <&mdp>;
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interrupts = <4 0>;
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reg-names = "dsi_ctrl";
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reg = <0xfd922800 0x200>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names =
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"bus",
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"byte",
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"core",
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"core_mmss",
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"iface",
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"mdp_core",
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"pixel";
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clocks =
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MDSS_BYTE0_CLK>,
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<&mmcc MDSS_ESC0_CLK>,
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<&mmcc MMSS_MISC_AHB_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_PCLK0_CLK>;
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assigned-clocks =
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<&mmcc BYTE0_CLK_SRC>,
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<&mmcc PCLK0_CLK_SRC>;
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assigned-clock-parents =
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<&dsi_phy0 0>,
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<&dsi_phy0 1>;
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vdda-supply = <&pma8084_l2>;
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vdd-supply = <&pma8084_l22>;
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vddio-supply = <&pma8084_l12>;
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phys = <&dsi_phy0>;
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phy-names ="dsi-phy";
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qcom,dual-dsi-mode;
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qcom,master-dsi;
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qcom,sync-dual-dsi;
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qcom,dsi-ctrl-shared;
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qcom,mdss-mdp-transfer-time-us = <12000>;
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frame-threshold-time-us = <800>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&dsi_active>;
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pinctrl-1 = <&dsi_suspend>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&mdp_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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panel: panel@0 {
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compatible = "sharp,lq101r1sx01";
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reg = <0>;
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link2 = <&secondary>;
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power-supply = <...>;
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backlight = <...>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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};
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};
|
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...
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161
qcom/opensource/display-devicetree/bindings/dsi_phy.yaml
Normal file
161
qcom/opensource/display-devicetree/bindings/dsi_phy.yaml
Normal file
@@ -0,0 +1,161 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dsi_phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies Inc. Snapdragon DSI PHY output
|
||||
|
||||
description: >
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
maintainers:
|
||||
- Vara Reddy <quic_varar@quicinc.com>
|
||||
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-phy-28nm-hpm
|
||||
- qcom,dsi-phy-28nm-lp
|
||||
- qcom,dsi-phy-20nm
|
||||
- qcom,dsi-phy-28nm-8960
|
||||
- qcom,dsi-phy-14nm
|
||||
- qcom,dsi-phy-10nm
|
||||
|
||||
reg:
|
||||
description: >
|
||||
Physical base address and length of the registers of PLL, PHY. Some
|
||||
revisions require the PHY regulator base address, whereas others require the
|
||||
PHY lane base address. See below for each PHY revision.
|
||||
|
||||
reg-names:
|
||||
description: >
|
||||
The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator"
|
||||
is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed.
|
||||
required:
|
||||
- "dsi_pll"
|
||||
- "dsi_phy"
|
||||
|
||||
clock-cells:
|
||||
description: >
|
||||
Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
const: <&mmcc MDSS_GDSC>
|
||||
|
||||
clocks:
|
||||
description: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
clock-names:
|
||||
const: iface
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
vddio-supply:
|
||||
description: >
|
||||
For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator
|
||||
device node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
vcca-supply:
|
||||
description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
vdds-supply:
|
||||
description: For 10nm PHY , phandle to vdds regulator device node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode:
|
||||
description: Boolean value indicating if the LDO mode PHY regulator is wanted.
|
||||
|
||||
qcom,mdss-mdp-transfer-time-us:
|
||||
description: >
|
||||
Specifies the dsi transfer time for command mode
|
||||
panels in microseconds. Driver uses this number to adjust
|
||||
the clock rate according to the expected transfer time.
|
||||
Increasing this value would slow down the mdp processing
|
||||
and can result in slower performance.
|
||||
Decreasing this value can speed up the mdp processing,
|
||||
but this can also impact power consumption.
|
||||
As a rule this time should not be higher than the time
|
||||
that would be expected with the processing at the
|
||||
dsi link rate since anyways this would be the maximum
|
||||
transfer time that could be achieved.
|
||||
If ping pong split is enabled, this time should not be higher
|
||||
than two times the dsi link rate time.
|
||||
If the property is not specified, then the default value is 14000 us.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
frame-threshold-time-us:
|
||||
description: >
|
||||
For command mode panels, this specifies the idle
|
||||
time for dsi controller where no active data is
|
||||
send to the panel, as controller is done sending
|
||||
active pixels. If there is no desired DSI clocks
|
||||
specified, then clocks will be derived from this
|
||||
threshold time, which has a default value in chipset
|
||||
based on the CPU processing power.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
dsi_pll_codes:
|
||||
description: Contain an u32 array data to store dsi pll codes which were passed from UEFI.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
qcom,dsi-phy-shared:
|
||||
description: Boolean value indicating if the DSI phy is shared between dual displays.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clock-cells
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- vddio-supply
|
||||
- vcca-supply
|
||||
- vdds-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
"dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
|
||||
qcom,panel-force-clock-lane-hs;
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
qcom,dsi-phy-shared;
|
||||
};
|
||||
|
||||
dsi_pll_codes_data:dsi_pll_codes {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
label = "dsi_pll_codes";
|
||||
};
|
||||
...
|
||||
2064
qcom/opensource/display-devicetree/bindings/mdss-dsi-panel.yaml
Normal file
2064
qcom/opensource/display-devicetree/bindings/mdss-dsi-panel.yaml
Normal file
File diff suppressed because it is too large
Load Diff
28
qcom/opensource/display-devicetree/bindings/msm_hdcp.yaml
Normal file
28
qcom/opensource/display-devicetree/bindings/msm_hdcp.yaml
Normal file
@@ -0,0 +1,28 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/msm_hdcp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MSM HDCP driver
|
||||
|
||||
description: |
|
||||
Standalone driver managing HDCP related communications between TZ and HLOS for MSM chipset.
|
||||
|
||||
maintainers:
|
||||
- Rajkumar Subbiah <quic_rsubbia@quicinc.com>
|
||||
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,msm-hdcp
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
qcom_msmhdcp: qcom,msm_hdcp {
|
||||
compatible = "qcom,msm-hdcp";
|
||||
};
|
||||
...
|
||||
579
qcom/opensource/display-devicetree/bindings/sde-dp.yaml
Normal file
579
qcom/opensource/display-devicetree/bindings/sde-dp.yaml
Normal file
@@ -0,0 +1,579 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/sde-dp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SDE DP
|
||||
|
||||
description: |
|
||||
sde-dp is the master Display Port device which supports DP host controllers that are compatible
|
||||
with VESA Display Port interface specification.
|
||||
msm_ext_disp is a device which manages the interaction between external
|
||||
display interfaces, e.g. Display Port, and the audio subsystem.
|
||||
[Optional child nodes]: These nodes are for devices which are
|
||||
dependent on msm_ext_disp. If msm_ext_disp is disabled then
|
||||
these devices will be disabled as well. Ex. Audio Codec device.
|
||||
|
||||
maintainers:
|
||||
- Rajkumar Subbiah <quic_rsubbia@quicinc.com>
|
||||
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,dp-display
|
||||
|
||||
reg:
|
||||
description: |
|
||||
Base address and length of DP hardware's memory mapped regions.
|
||||
|
||||
reg-names:
|
||||
description: |
|
||||
A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
|
||||
"dp_ahb" - AHB memory region.
|
||||
"dp_aux" - AUX memory region.
|
||||
"dp_link" - LINK memory region.
|
||||
"dp_p0" - PCLK0 memory region.
|
||||
"dp_phy" - PHY memory region.
|
||||
"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
|
||||
"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
|
||||
"dp_mmss_cc" - Display Clock Control memory region.
|
||||
"dp_pll" - USB3 DP combo PLL memory region.
|
||||
"usb3_dp_com" - USB3 DP PHY combo memory region.
|
||||
"hdcp_physical" - DP HDCP memory region.
|
||||
"dp_p1" - DP PCLK1 memory region.
|
||||
"gdsc" - DISPCC GDSC memory region.
|
||||
|
||||
cell-index:
|
||||
description: Specifies the controller instance.
|
||||
|
||||
'#clock-cells':
|
||||
description: Denotes the DP driver as a clock producer (has one or more clock outputs)
|
||||
|
||||
clocks:
|
||||
description: Clocks required for Display Port operation.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core_aux_clk
|
||||
- const: core_usb_ref_clk_src
|
||||
- const: core_usb_pipe_clk
|
||||
- const: link_clk
|
||||
- const: link_clk_src
|
||||
- const: link_iface_clk
|
||||
- const: pixel_clk_rcg
|
||||
- const: pixel_parent
|
||||
- const: pixel1_clk_rcg
|
||||
- const: strm0_pixel_clk
|
||||
- const: strm1_pixel_clk
|
||||
|
||||
vdda-1p2-supply:
|
||||
description: phandle to vdda 1.2V regulator node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
vdda-0p9-supply:
|
||||
description: phandle to vdda 0.9V regulator node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
interrupt-parent:
|
||||
description: phandle to the interrupt parent device node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
interrupts:
|
||||
description: The interrupt signal from the DSI block.
|
||||
|
||||
qcom,aux-cfg0-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 0 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg1-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 1 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg2-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 2 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg3-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 3 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg4-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 4 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg5-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 5 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg6-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 6 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg7-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 7 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg8-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 8 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,aux-cfg9-settings:
|
||||
description: |
|
||||
Specifies the DP AUX configuration 9 settings. The first
|
||||
entry in this array corresponds to the register offset
|
||||
within DP AUX, while the remaining entries indicate the
|
||||
programmable values.
|
||||
|
||||
qcom,max-pclk-frequency-khz:
|
||||
description: An integer specifying the max. pixel clock in KHz supported by Display Port.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,mst-enable:
|
||||
description: MST feature enable control node.
|
||||
|
||||
qcom,dsc-feature-enable:
|
||||
description: DSC feature enable control node.
|
||||
|
||||
qcom,fec-feature-enable:
|
||||
description: FEC feature enable control node.
|
||||
|
||||
qcom,qos-cpu-mask:
|
||||
description: A u32 value indicating desired PM QoS CPU affine mask
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,qos-cpu-latency-us:
|
||||
description: A u32 value indicating desired PM QoS CPU latency in usec
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,altmode-dev:
|
||||
description: Phandle for the AltMode GLink driver.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
usb-controller:
|
||||
description: Phandle for the USB controller.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,pll-revision:
|
||||
description: PLL hardware revision.
|
||||
|
||||
usb-phy:
|
||||
description: Phandle for USB PHY driver. This is used to register for USB cable events.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,dsc-continuous-pps:
|
||||
description: |
|
||||
Control node for sending PPS every frame in hardware for DSC over DP.
|
||||
This is needed by certain bridge chips where there is such a requirement to do so.
|
||||
|
||||
qcom,dp-aux-switch:
|
||||
description: Phandle for the driver used to program the AUX switch for Display Port orientation.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,dp-hpd-gpio:
|
||||
description: HPD gpio for direct DP connector without USB PHY or AUX switch.
|
||||
|
||||
qcom,dp-gpio-aux-switch:
|
||||
description: Gpio DP AUX switch chipset support.
|
||||
|
||||
clock-mmrm:
|
||||
description: |
|
||||
List of the clocks that enable setting the clk rate through MMRM driver.
|
||||
The order of the list must match the 'clocks' and 'clock-names'
|
||||
properties. The 'DISP_CC' ID of the clock must be used to enable
|
||||
the property for the respective clock, whereas a value of zero
|
||||
disables the property.
|
||||
|
||||
vdd_mx-supply:
|
||||
description: phandle to vdda MX regulator node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
qcom,aux-en-gpio:
|
||||
description: Specifies the aux-channel enable gpio.
|
||||
|
||||
qcom,aux-sel-gpio:
|
||||
description: Specifies the aux-channel select gpio.
|
||||
|
||||
qcom,usbplug-cc-gpio:
|
||||
description: Specifies the usbplug orientation gpio.
|
||||
|
||||
qcom,ext-disp:
|
||||
description: phandle for msm-ext-display module
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
compatible:
|
||||
const: qcom,msm-ext-disp
|
||||
|
||||
qcom,dp-low-power-hw-hpd:
|
||||
description: Low power hardware HPD feature enable control node
|
||||
|
||||
qcom,phy-version:
|
||||
description: Phy version
|
||||
|
||||
pinctrl-names:
|
||||
description: |
|
||||
List of names to assign mdss pin states defined in pinctrl device node
|
||||
Refer to pinctrl-bindings.txt
|
||||
|
||||
pinctrl-<0..n>:
|
||||
description: |
|
||||
Lists phandles each pointing to the pin configuration node within a pin
|
||||
controller. These pin configurations are installed in the pinctrl
|
||||
device node. Refer to pinctrl-bindings.txt
|
||||
|
||||
qcom,max-lclk-frequency-khz:
|
||||
description: An integer specifying the max. link clock in KHz supported by Display Port.
|
||||
|
||||
qcom,mst-fixed-topology-ports:
|
||||
description: u32 values of which MST output port to reserve, start from one
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,hbr-rbr-voltage-swing:
|
||||
description: Specifies the voltage swing levels for HBR and RBR rates.
|
||||
|
||||
qcom,hbr-rbr-pre-emphasis:
|
||||
description: Specifies the pre-emphasis levels for HBR and RBR rates.
|
||||
|
||||
qcom,hbr2-3-voltage-swing:
|
||||
description: Specifies the voltage swing levels for HBR2 and HBR3 rates.
|
||||
|
||||
qcom,hbr2-3-pre-emphasis:
|
||||
description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates.
|
||||
|
||||
compatible:
|
||||
const: qcom,msm-ext-disp-audio-codec-rx
|
||||
|
||||
ext_disp_audio_codec:
|
||||
description: Node for Audio Codec.
|
||||
|
||||
pattern properties:
|
||||
"qcom,+\w+\-supply\-entries":
|
||||
description: |
|
||||
A node that lists the elements of the supply used by the
|
||||
a particular "type" of DSI module. The module "types"
|
||||
can be "core", "ctrl", and "phy". Within the same type,
|
||||
there can be more than one instance of this binding,
|
||||
in which case the entry would be appended with the
|
||||
supply entry index.
|
||||
e.g. qcom,ctrl-supply-entry@0
|
||||
type: object
|
||||
patternProperties:
|
||||
"qcom,ctrl\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
"qcom,core\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
"qcom,phy\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- cell-index
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdda-1p2-supply
|
||||
- vdda-0p9-supply
|
||||
- interrupt-parent
|
||||
- interrupts
|
||||
- qcom,aux-cfg0-settings
|
||||
- qcom,aux-cfg1-settings
|
||||
- qcom,aux-cfg2-settings
|
||||
- qcom,aux-cfg3-settings
|
||||
- qcom,aux-cfg4-settings
|
||||
- qcom,aux-cfg5-settings
|
||||
- qcom,aux-cfg6-settings
|
||||
- qcom,aux-cfg7-settings
|
||||
- qcom,aux-cfg8-settings
|
||||
- qcom,aux-cfg9-settings
|
||||
- qcom,max-pclk-frequency-khz
|
||||
- qcom,mst-enable
|
||||
- qcom,dsc-feature-enable
|
||||
- qcom,fec-feature-enable
|
||||
- qcom,qos-cpu-mask
|
||||
- qcom,qos-cpu-latency-us
|
||||
- qcom,altmode-dev
|
||||
- usb-controller
|
||||
- qcom,pll-revision
|
||||
- usb-phy
|
||||
- qcom,dp-aux-switch
|
||||
- qcom,dp-hpd-gpio
|
||||
- qcom,dp-gpio-aux-switch
|
||||
- qcom,<type>-supply-entries
|
||||
|
||||
examples:
|
||||
- |
|
||||
ext_disp: qcom,msm-ext-disp {
|
||||
compatible = "qcom,msm-ext-disp";
|
||||
|
||||
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
sde_dp: qcom,dp_display@0 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,dp-display";
|
||||
|
||||
qcom,dp-aux-switch = <&fsa4480>;
|
||||
qcom,ext-disp = <&ext_disp>;
|
||||
qcom,altmode-dev = <&altmode 0>;
|
||||
usb-controller = <&usb0>;
|
||||
|
||||
reg = <0xae90000 0x0dc>,
|
||||
<0xae90200 0x0c0>,
|
||||
<0xae90400 0x508>,
|
||||
<0xae91000 0x094>,
|
||||
<0x88eaa00 0x200>,
|
||||
<0x88ea200 0x200>,
|
||||
<0x88ea600 0x200>,
|
||||
<0xaf02000 0x1a0>,
|
||||
<0x88ea000 0x200>,
|
||||
<0x88e8000 0x20>,
|
||||
<0x0aee1000 0x034>,
|
||||
<0xae91400 0x094>,
|
||||
<0xaf03000 0x8>;
|
||||
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
||||
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
||||
"dp_mmss_cc", "dp_pll", "usb3_dp_com",
|
||||
"hdcp_physical", "dp_p1", "gdsc";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <12 0>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&clock_rpmh RPMH_CXO_CLK>,
|
||||
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
|
||||
<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
|
||||
clock-names = "core_aux_clk", "core_usb_ref_clk_src",
|
||||
"core_usb_pipe_clk", "link_clk", "link_clk_src",
|
||||
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
||||
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
|
||||
clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>;
|
||||
|
||||
qcom,pll-revision = "5nm-v1";
|
||||
qcom,phy-version = <0x420>;
|
||||
qcom,dp-aux-switch = <&fsa4480>;
|
||||
|
||||
qcom,aux-cfg0-settings = [1c 00];
|
||||
qcom,aux-cfg1-settings = [20 13 23 1d];
|
||||
qcom,aux-cfg2-settings = [24 00];
|
||||
qcom,aux-cfg3-settings = [28 00];
|
||||
qcom,aux-cfg4-settings = [2c 0a];
|
||||
qcom,aux-cfg5-settings = [30 26];
|
||||
qcom,aux-cfg6-settings = [34 0a];
|
||||
qcom,aux-cfg7-settings = [38 03];
|
||||
qcom,aux-cfg8-settings = [3c bb];
|
||||
qcom,aux-cfg9-settings = [40 03];
|
||||
qcom,max-pclk-frequency-khz = <593470>;
|
||||
qcom,mst-enable;
|
||||
qcom,dsc-feature-enable;
|
||||
qcom,fec-feature-enable;
|
||||
qcom,dsc-continuous-pps;
|
||||
qcom,qos-cpu-mask = <0xf>;
|
||||
qcom,qos-cpu-latency-us = <300>;
|
||||
vdda-1p2-supply = <&L6B>;
|
||||
vdda-0p9-supply = <&L1B>;
|
||||
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||
|
||||
qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>,
|
||||
<0x11 0x1e 0x1f 0xff>,
|
||||
<0x16 0x1f 0xff 0xff>,
|
||||
<0x1f 0xff 0xff 0xff>;
|
||||
qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>,
|
||||
<0x00 0x0e 0x15 0xff>,
|
||||
<0x00 0x0e 0xff 0xff>,
|
||||
<0x02 0xff 0xff 0xff>;
|
||||
|
||||
qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>,
|
||||
<0x09 0x19 0x1f 0xff>,
|
||||
<0x10 0x1f 0xff 0xff>,
|
||||
<0x1f 0xff 0xff 0xff>;
|
||||
qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>,
|
||||
<0x02 0x0e 0x16 0xff>,
|
||||
<0x02 0x11 0xff 0xff>,
|
||||
<0x04 0xff 0xff 0xff>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <21700>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <912000>;
|
||||
qcom,supply-max-voltage = <912000>;
|
||||
qcom,supply-enable-load = <115000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,core-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,core-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "refgen";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pll-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,pll-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdd_mx";
|
||||
qcom,supply-min-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,supply-max-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
360
qcom/opensource/display-devicetree/bindings/sde-dsi.yaml
Normal file
360
qcom/opensource/display-devicetree/bindings/sde-dsi.yaml
Normal file
@@ -0,0 +1,360 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/sde-dsi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MDSS DSI
|
||||
|
||||
description: |
|
||||
mdss-dsi is the master DSI device which supports multiple DSI host controllers
|
||||
that are compatible with MIPI display serial interface specification.
|
||||
|
||||
maintainers:
|
||||
- Vara Reddy <quic_varar@quicinc.com>
|
||||
- Vishnuvardhan Prodduturi <quic_vproddut@quicinc.com>
|
||||
|
||||
pattern properties:
|
||||
"qcom,+\w+\-supply\-entries":
|
||||
description: |
|
||||
A node that lists the elements of the supply used by the
|
||||
a particular "type" of DSI module. The module "types"
|
||||
can be "core", "ctrl", and "phy". Within the same type,
|
||||
there can be more than one instance of this binding,
|
||||
in which case the entry would be appended with the
|
||||
supply entry index.
|
||||
e.g. qcom,ctrl-supply-entry@0
|
||||
type: object
|
||||
patternProperties:
|
||||
"qcom,ctrl\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
"qcom,core\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
"qcom,phy\-supply\-entry\@+\w":
|
||||
properties:
|
||||
reg:
|
||||
description: offset and length of the register set for the device.
|
||||
qcom,supply-name:
|
||||
description: name of the supply (vdd/vdda/vddio)
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
qcom,supply-min-voltage:
|
||||
description: minimum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-max-voltage:
|
||||
description: maximum voltage level (uV)
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-enable-load:
|
||||
description: load drawn (uA) from enabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-disable-load:
|
||||
description: load drawn (uA) from disabled supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-on-sleep:
|
||||
description: time to sleep (ms) before turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-on-sleep:
|
||||
description: time to sleep (ms) after turning on
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-pre-off-sleep:
|
||||
description: time to sleep (ms) before turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
qcom,supply-post-off-sleep:
|
||||
description: time to sleep (ms) after turning off
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,dsi-ctrl-hw-v2.4
|
||||
- qcom,dsi-ctrl-hw-v2.5
|
||||
- qcom,dsi-ctrl-hw-v2.6
|
||||
- qcom,dsi-ctrl-hw-v2.7
|
||||
- qcom,dsi-ctrl-hw-v2.8
|
||||
- qcom,dsi-ctrl-hw-v2.9
|
||||
- qcom,dsi-phy-v3.0
|
||||
- qcom,dsi-phy-v4.0
|
||||
- qcom,dsi-phy-v4.1
|
||||
- qcom,dsi-phy-v4.2
|
||||
- qcom,dsi-phy-v4.3
|
||||
- qcom,dsi-phy-v4.3.2
|
||||
- qcom,dsi-phy-v5.2
|
||||
- qcom,dsi-phy-v7.2
|
||||
|
||||
reg:
|
||||
description: |
|
||||
List of base address and length of memory mapped
|
||||
regions of DSI controller, disp_cc and mdp_intf.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_ctrl
|
||||
- const: disp_cc_base
|
||||
- const: mdp_intf_base
|
||||
|
||||
cell-index:
|
||||
description: Specifies the controller instance.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- const: mdp_core_clk
|
||||
- const: iface_clk
|
||||
- const: core_mmss_clk
|
||||
- const: bus_clk
|
||||
- const: byte_clk
|
||||
- const: pixel_clk
|
||||
- const: core_clk
|
||||
- const: byte_clk_rcg
|
||||
- const: pixel_clk_rcg
|
||||
|
||||
pll-label:
|
||||
description: Supported versions of DSI PLL.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
enum: [dsi_pll_5nm, dsi_pll_4nm, dsi_pll_3nm]
|
||||
|
||||
gdsc-supply:
|
||||
description: phandle to gdsc regulator node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
vdda-supply:
|
||||
description: phandle to vdda regulator node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
vcca-supply:
|
||||
description: phandle to vcca regulator node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
interrupt-parent:
|
||||
description: phandle to the interrupt parent device node.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
interrupts:
|
||||
description: The interrupt signal from the DSI block.
|
||||
|
||||
qcom,dsi-default-panel:
|
||||
description: Specifies the default panel.
|
||||
|
||||
qcom,mdp:
|
||||
description: Specifies the mdp node which can find panel node from this.
|
||||
|
||||
qcom,demura-panel-id:
|
||||
description: |
|
||||
Specifies the u64 demura panel ID as an array <2>
|
||||
If demura is not used this node must be set to <0,0>.
|
||||
$ref: /schemas/types.yaml#/definitions/uint64
|
||||
|
||||
qcom,msm-bus,name:
|
||||
description: String property describing MDSS client.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
qcom,msm-bus,num-cases:
|
||||
description: |
|
||||
This is the number of bus scaling use cases
|
||||
defined in the vectors property. This must be
|
||||
set to <2> for MDSS DSI driver where use-case 0
|
||||
is used to remove BW votes from the system. Use
|
||||
case 1 is used to generate bandwidth requestes
|
||||
when sending command packets.
|
||||
|
||||
qcom,msm-bus,num-paths:
|
||||
description: |
|
||||
This represents number of paths in each bus
|
||||
scaling usecase. This value depends on number of
|
||||
AXI master ports dedicated to MDSS for
|
||||
particular chipset.
|
||||
|
||||
qcom,msm-bus,vectors-KBps:
|
||||
description: |
|
||||
A series of 4 cell properties, with a format
|
||||
of (src, dst, ab, ib) which is defined at
|
||||
Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
|
||||
DSI driver should always set average bandwidth
|
||||
(ab) to 0 and always use instantaneous
|
||||
bandwidth(ib) values.
|
||||
|
||||
label:
|
||||
description: String to describe controller.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
qcom,platform-te-gpio:
|
||||
description: Specifies the gpio used for TE.
|
||||
|
||||
qcom,panel-te-source:
|
||||
description: Specifies the source pin for Vsync from panel or WD Timer.
|
||||
|
||||
qcom,dsi-ctrl:
|
||||
description: handle to dsi controller device
|
||||
|
||||
qcom,dsi-phy:
|
||||
description: handle to dsi phy device
|
||||
|
||||
qcom,dsi-ctrl-num:
|
||||
description: Specifies the DSI controllers to use for primary panel
|
||||
|
||||
qcom,dsi-sec-ctrl-num:
|
||||
description: Specifies the DSI controllers to use for secondary panel
|
||||
|
||||
qcom,dsi-phy-num:
|
||||
description: Specifies the DSI PHYs to use for primary panel
|
||||
|
||||
qcom,dsi-sec-phy-num:
|
||||
description: Specifies the DSI PHYs to use for secondary panel
|
||||
|
||||
qcom,dsi-select-clocks:
|
||||
description: Specifies the required clocks to use for primary panel
|
||||
|
||||
qcom,dsi-select-sec-clocks:
|
||||
description: Specifies the required clocks to use for secondary panel
|
||||
|
||||
qcom,dsi-display-list:
|
||||
description: Specifies the list of supported displays.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
qcom,dsi-manager:
|
||||
description: Specifies dsi manager is present
|
||||
|
||||
qcom,dsi-display:
|
||||
description: Specifies dsi display is present
|
||||
|
||||
qcom,hdmi-display:
|
||||
description: Specifies hdmi is present
|
||||
|
||||
qcom,dp-display:
|
||||
description: Specified dp is present
|
||||
|
||||
qcom,mdss-mdp-transfer-time-us:
|
||||
description: |
|
||||
Specifies the dsi transfer time for command mode
|
||||
panels in microseconds. Driver uses this number to adjust
|
||||
the clock rate according to the expected transfer time.
|
||||
Increasing this value would slow down the mdp processing
|
||||
and can result in slower performance.
|
||||
Decreasing this value can speed up the mdp processing,
|
||||
but this can also impact power consumption.
|
||||
As a rule this time should not be higher than the time
|
||||
that would be expected with the processing at the
|
||||
dsi link rate since anyways this would be the maximum
|
||||
transfer time that could be achieved.
|
||||
If ping pong split enabled, this time should not be higher
|
||||
than two times the dsi link rate time.
|
||||
If the property is not specified, then the default value is 14000 us.
|
||||
|
||||
qcom,dsi-phy-pll-bypass:
|
||||
description: |
|
||||
A boolean property that enables bypassing hardware access in DSI
|
||||
PHY/PLL drivers to allow the DSI driver to run on emulation platforms
|
||||
that might be missing those modules.
|
||||
|
||||
qcom,null-insertion-enabled:
|
||||
description: A boolean to enable NULL packet insertion feature for DSI controller.
|
||||
|
||||
ports:
|
||||
description: |
|
||||
This video port is used when external bridge is present.
|
||||
The connection is modeled using the OF graph bindings
|
||||
specified in Documentation/devicetree/bindings/graph.txt.
|
||||
Video port 0 reg 0 is for the bridge output. The remote
|
||||
endpoint phandle should be mipi_dsi_device device node.
|
||||
|
||||
qcom,dsi-pll-ssc-en:
|
||||
description: Boolean property to indicate that ssc is enabled.
|
||||
|
||||
qcom,dsi-pll-ssc-mode:
|
||||
description: |
|
||||
Spread-spectrum clocking. It can be either "down-spread"
|
||||
or "center-spread". Default is "down-spread" if it is not specified.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
default: down-spread
|
||||
enum: [down-spread, center-spread]
|
||||
|
||||
qcom,ssc-frequency-hz:
|
||||
description: |
|
||||
Integer property to specify the spread frequency
|
||||
to be programmed for the SSC.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,ssc-ppm:
|
||||
description: Integer property to specify the Parts per Million value of SSC.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
qcom,avdd-regulator-gpio:
|
||||
description: Specifies the gpio pin used for avdd power supply regulator.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- cell-index
|
||||
- clocks
|
||||
- clock-names
|
||||
- pll-label
|
||||
- gdsc-supply
|
||||
- vdda-supply
|
||||
- vcca-supply
|
||||
- interrupt-parent
|
||||
- qcom,dsi-default-panel
|
||||
- qcom,mdp
|
||||
- qcom,demura-panel-id
|
||||
- qcom,msm-bus,name
|
||||
- qcom,msm-bus,num-cases
|
||||
- qcom,msm-bus,num-paths
|
||||
- qcom,msm-bus,vectors-KBps
|
||||
|
||||
...
|
||||
36
qcom/opensource/display-devicetree/bindings/sde-wb.yaml
Normal file
36
qcom/opensource/display-devicetree/bindings/sde-wb.yaml
Normal file
@@ -0,0 +1,36 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/sde-wb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display
|
||||
|
||||
maintainers:
|
||||
- Veera Sundaram Sankaran <quic_veeras@quicinc.com>
|
||||
- Kalyan Thota <quic_kalyant@quicinc.com>
|
||||
- Ravi Teja Tamatam <quic_travitej@quicinc.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,wb-display
|
||||
|
||||
cell-index:
|
||||
description: Index of writeback device instance. Default to 0 if not specified.
|
||||
default: 0
|
||||
|
||||
label:
|
||||
description: String to describe this writeback display. Default to "unknown" if not specified.
|
||||
default: "unknown"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
sde_wb: qcom,wb-display {
|
||||
compatible = "qcom,wb-display";
|
||||
cell-index = <2>;
|
||||
label = "wb_display";
|
||||
};
|
||||
...
|
||||
2076
qcom/opensource/display-devicetree/bindings/sde.yaml
Normal file
2076
qcom/opensource/display-devicetree/bindings/sde.yaml
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,51 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
|
||||
qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-t-clk-post = <0x03>;
|
||||
qcom,mdss-dsi-t-clk-pre = <0x24>;
|
||||
qcom,mdss-dsi-force-clock-lane-hs;
|
||||
qcom,mdss-dsi-ext-bridge-mode;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-width = <1920>;
|
||||
qcom,mdss-dsi-panel-height = <1080>;
|
||||
qcom,mdss-dsi-h-front-porch = <88>;
|
||||
qcom,mdss-dsi-h-back-porch = <148>;
|
||||
qcom,mdss-dsi-h-pulse-width = <44>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <36>;
|
||||
qcom,mdss-dsi-v-front-porch = <4>;
|
||||
qcom,mdss-dsi-v-pulse-width = <5>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,display-topology = <1 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_dsc_10b_cmd: qcom,mdss_dsi_nt37801_amoled_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled cmd mode dsi csot panel with DSC 10bit";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1223800000>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 02 c3 19
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 04 c5 0b 0b 0b
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 02 f5 10
|
||||
39 01 00 00 00 00 02 6f 1b
|
||||
39 01 00 00 00 00 02 f4 55
|
||||
39 01 00 00 00 00 02 6f 18
|
||||
39 01 00 00 00 00 02 f8 19
|
||||
39 01 00 00 00 00 02 6f 0f
|
||||
39 01 00 00 00 00 02 fc 00
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 ab 28 00 28 f2
|
||||
00 02 c2 03 e1 00 0a 03 14 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 03 04 55 77
|
||||
77 77 99 9b 10 00 1e 48 9a bb bc de
|
||||
f0 11 30
|
||||
39 01 00 00 00 00 02 f3 dc
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3b 00 14 00 2c
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 ff 07 ff 0f
|
||||
ff
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 5f 00
|
||||
39 01 00 00 00 00 02 9c 01
|
||||
05 01 00 00 00 00 01 2c
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 b2 55 01 ff 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,124 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_dsc_10b_video: qcom,mdss_dsi_nt37801_amoled_dsc_10b_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled video mode dsi csot panel with DSC 10bit";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <30>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 c2 81
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 03
|
||||
39 01 00 00 00 00 02 c6 a2
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 05
|
||||
39 01 00 00 00 00 02 6f 08
|
||||
39 01 00 00 00 00 06 ec 10 00 00 00 ff
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3b 00 14 00 2c
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 02 c3 19
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 04 c5 0b 0b 0b
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 02 f5 10
|
||||
39 01 00 00 00 00 02 6f 1b
|
||||
39 01 00 00 00 00 02 f4 55
|
||||
39 01 00 00 00 00 02 6f 18
|
||||
39 01 00 00 00 00 02 f8 19
|
||||
39 01 00 00 00 00 02 6f 0f
|
||||
39 01 00 00 00 00 02 fc 00
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 ab 2a 00 28 f1
|
||||
9a 02 68 03 92 00 0e 03 14 02 56 10
|
||||
ec
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 04 56 77
|
||||
77 77 99 9b f0 00 02 78 9a bb bc dd
|
||||
ee ff 00
|
||||
39 01 00 00 00 00 02 f3 dc
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 ff 07 ff 0f
|
||||
ff
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5f 00
|
||||
39 01 00 00 00 00 02 9c 01
|
||||
05 01 00 00 00 00 01 2c
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 b2 55 01 ff 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <10>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,588 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_fhd_plus_cmd: qcom,mdss_dsi_nt37801_fhd_plus_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled fhd plus cmd mode dsi csot panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
39 01 00 00 00 00 02 8F 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 04 37
|
||||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 0e 03 dd 00 07 02 77 02 8B 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0
|
||||
39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0
|
||||
39 01 00 00 00 00 02 03 00
|
||||
39 01 00 00 00 00 02 8F 01
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <680000000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 0e 03 dd 00 07 02 77 02 8B 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <680000000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 0e 03 dd 00 07 02 77 02 8B 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-framerate = <40>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <680000000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 02 02 00 01
|
||||
02 02 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 0e 03 dd 00 07 02 77 02 8B 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 02 02 00 01
|
||||
02 02 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
cell-index = <4>;
|
||||
qcom,mdss-dsi-panel-framerate = <30>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <680000000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 03 03 00 01
|
||||
03 03 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2a 00 00 04 37
|
||||
39 01 00 00 00 00 05 2b 00 00 09 5f
|
||||
39 01 00 00 00 00 02 90 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 0e 03 dd 00 07 02 77 02 8B 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 8f 01
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 03 03 00 01
|
||||
03 03 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,372 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_cmd_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_cphy {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled cmd mode dsi csot panel with DSC CPHY";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-cphy-mode;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <22>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <728870000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <22>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <548200000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <22>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <728870000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_cmd_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_ddicspr {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled cmd mode dsi csot panel with DSC and bypass DDIC SPR";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
39 01 00 00 00 00 07 b1 00 10 00 10 00 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,152 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_cmd_spr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_spr {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled cmd mode dsi csot panel with DSC and AP SPR";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsc-version = <0x12>;
|
||||
qcom,src-chroma-format = <1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 A0 F0 00 32 D1
|
||||
00 01 E2 01 9B 00 3C 02 20 08 A4 11
|
||||
50
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 02 DE 00
|
||||
39 01 00 00 00 00 02 6F 09
|
||||
39 01 00 00 00 00 07 DE 10 34 25 30 14 25
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 81
|
||||
39 01 00 00 00 00 02 6F 1D
|
||||
39 01 00 00 00 00 02 FB 6F
|
||||
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 07
|
||||
39 01 00 00 00 00 02 B0 24
|
||||
39 01 00 00 00 00 02 03 10
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,597 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_cmd: qcom,mdss_dsi_nt37801_wqhd_plus_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled cmd mode dsi csot panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 02 8F 00
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 8f 00
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 02 2f 01
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 24 45
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1199900000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 8f 00
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 01 01 00 01
|
||||
01 01 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-framerate = <40>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1199900000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 8f 00
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 02 02 00 01
|
||||
02 02 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 02 02 00 01
|
||||
02 02 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
cell-index = <4>;
|
||||
qcom,mdss-dsi-panel-framerate = <30>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <1199900000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 05 2a 00 00 05 9f
|
||||
39 01 00 00 00 00 05 2b 00 00 0c 7f
|
||||
39 01 00 00 00 00 02 8f 00
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 03 03 00 01
|
||||
03 03 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 02 26 01
|
||||
39 01 00 00 00 00 02 5a 01
|
||||
39 01 00 00 00 00 02 2f 30
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1c
|
||||
39 01 00 00 00 00 09 ba 91 03 03 00 01
|
||||
03 03 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 06 c0 54 c0 00 21 43
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 02
|
||||
39 01 00 00 00 00 02 cc 30
|
||||
39 01 00 00 00 00 02 ce 01
|
||||
39 01 00 00 20 00 02 cc 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,143 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_video_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_vid_cphy {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled video mode dsi csot panel with DSC CPHY";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,panel-cphy-mode;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,130 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_video_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_ddicspr {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled video mode dsi csot panel with DSC and bypass DDIC SPR";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
39 01 00 00 00 00 07 b1 00 10 00 10 00 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,154 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_vid_spr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_spr {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled vid mode dsi csot panel with DSC and AP SPR";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsc-version = <0x12>;
|
||||
qcom,src-chroma-format = <1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 D2
|
||||
00 02 86 04 3A 00 0A 02 AB 01 E9 10
|
||||
F0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 02 DE 00
|
||||
39 01 00 00 00 00 02 6F 09
|
||||
39 01 00 00 00 00 07 DE 10 34 25 30 14 25
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 81
|
||||
39 01 00 00 00 00 02 6F 1D
|
||||
39 01 00 00 00 00 02 FB 6F
|
||||
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 07
|
||||
39 01 00 00 00 00 02 B0 24
|
||||
39 01 00 00 00 00 02 03 10
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,142 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_video: qcom,mdss_dsi_nt37801_wqhd_plus_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled video mode dsi csot panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
/*
|
||||
* ###############################################################
|
||||
* # Pentile SPR phases for SM8750 and later
|
||||
* ###############################################################
|
||||
* # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* #
|
||||
* # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B
|
||||
* # G G G G ... G G G G ... G G G G ... G G G G ...
|
||||
* # R B R B ... B R B R ... R B R B ... B R B R ...
|
||||
* ###############################################################
|
||||
*/
|
||||
qcom,spr-pentile-pack-type = "BG-RG Type B";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,149 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_qsync_cmd_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd_cphy {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled qsync cmd mode dsi csot panel with DSC CPHY";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-cphy-mode;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <60>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <22>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1f
|
||||
39 01 00 00 00 00 02 c0 50
|
||||
39 01 00 00 00 00 02 6f 22
|
||||
39 01 00 00 00 00 03 c0 0C bf
|
||||
39 01 00 00 00 00 02 6f 13
|
||||
39 01 00 00 00 00 03 c0 00 cc
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 03 44 00 00
|
||||
39 01 00 00 00 00 02 2f 10
|
||||
];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,148 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_qsync_cmd: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled qsync cmd mode dsi csot panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <60>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 05 3B 00 18 00 10
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2F 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
39 01 00 00 00 00 02 6f 1f
|
||||
39 01 00 00 00 00 02 c0 50
|
||||
39 01 00 00 00 00 02 6f 22
|
||||
39 01 00 00 00 00 03 c0 0C bf
|
||||
39 01 00 00 00 00 02 6f 13
|
||||
39 01 00 00 00 00 03 c0 00 cc
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 03 44 00 00
|
||||
39 01 00 00 00 00 02 2f 10
|
||||
];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_qsync_video_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid_cphy {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled qsync video mode dsi csot panel with DSC CPHY";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,panel-cphy-mode;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <80>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 82
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 03 F3 CC 0C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,130 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_nt37801_amoled_qsync_video: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"nt37801 amoled qsync video mode dsi csot panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,spr-pack-type = "pentile";
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <80>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250
|
||||
15700 12250 35800 6750 2550>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <13000000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <10>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <3200>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <20>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <20>;
|
||||
qcom,mdss-dsi-v-front-porch = <44>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 01 00 00 00 00 02 C2 81
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 03
|
||||
39 01 00 00 00 00 02 C6 A2
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 05
|
||||
39 01 00 00 00 00 02 6F 08
|
||||
39 01 00 00 00 00 06 EC 10 00 00 00 FF
|
||||
39 01 00 00 00 00 02 17 01
|
||||
39 01 00 00 00 00 05 3B 00 14 00 2C
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 02 C3 19
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 04 C5 0B 0B 0B
|
||||
39 01 00 00 00 00 05 FF AA 55 A5 80
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 02 F5 10
|
||||
39 01 00 00 00 00 02 6F 1B
|
||||
39 01 00 00 00 00 02 F4 55
|
||||
39 01 00 00 00 00 02 6F 18
|
||||
39 01 00 00 00 00 02 F8 19
|
||||
39 01 00 00 00 00 02 6F 0F
|
||||
39 01 00 00 00 00 02 FC 00
|
||||
39 01 00 00 00 00 05 2A 00 00 05 9F
|
||||
39 01 00 00 00 00 05 2B 00 00 0C 7F
|
||||
39 01 00 00 00 00 03 90 03 03
|
||||
39 01 00 00 00 00 13 91 89 28 00 28 c2
|
||||
00 02 68 04 6c 00 0a 02 77 01 e9 10
|
||||
f0
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 81
|
||||
39 01 00 00 00 00 02 6f 23
|
||||
39 01 00 00 00 00 15 fb 00 01 00 11 33
|
||||
33 33 55 57 d0 00 00 44 56 77 78 9a
|
||||
bc dd f0
|
||||
39 01 00 00 00 00 02 6F 06
|
||||
39 01 00 00 00 00 02 F3 DC
|
||||
39 01 00 00 00 00 02 26 00
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 07 51 07 FF 07 FF 0F
|
||||
FF
|
||||
39 01 00 00 00 00 02 5A 01
|
||||
39 01 00 00 00 00 02 5F 00
|
||||
39 01 00 00 00 00 02 9C 01
|
||||
05 01 00 00 00 00 01 2C
|
||||
39 01 00 00 00 00 02 2f 00
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 01
|
||||
39 01 00 00 00 00 05 B2 55 01 FF 03
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-rc-override_v1;
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,101 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
|
||||
qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
|
||||
qcom,mdss-pan-physical-width-dimension = <71>;
|
||||
qcom,mdss-pan-physical-height-dimension = <129>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,dcs-cmd-by-left;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <3840>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 11 91 09 20 00 20 02
|
||||
00 03 1c 04 21 00
|
||||
0f 03 19 01 97
|
||||
39 01 00 00 00 00 03 92 10 f0
|
||||
15 01 00 00 00 00 02 90 03
|
||||
15 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 04
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
15 01 00 00 00 00 02 ef 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
15 01 00 00 00 00 02 b4 01
|
||||
15 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 80
|
||||
15 01 00 00 00 00 02 6f 01
|
||||
15 01 00 00 00 00 02 f3 10
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 00
|
||||
/* sleep out + delay 120ms */
|
||||
05 01 00 00 78 00 01 11
|
||||
/* display on + delay 120ms */
|
||||
05 01 00 00 78 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <32>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
|
||||
qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
|
||||
qcom,mdss-pan-physical-width-dimension = <71>;
|
||||
qcom,mdss-pan-physical-height-dimension = <129>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <3840>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 11 91 09 20 00 20 02
|
||||
00 03 1c 04 21 00
|
||||
0f 03 19 01 97
|
||||
39 01 00 00 00 00 03 92 10 f0
|
||||
15 01 00 00 00 00 02 90 03
|
||||
15 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 04
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 07
|
||||
15 01 00 00 00 00 02 ef 01
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 00
|
||||
15 01 00 00 00 00 02 b4 10
|
||||
15 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 06 f0 55 aa 52 08 01
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 80
|
||||
15 01 00 00 00 00 02 6f 01
|
||||
15 01 00 00 00 00 02 f3 10
|
||||
39 01 00 00 00 00 05 ff aa 55 a5 00
|
||||
/* sleep out + delay 120ms */
|
||||
05 01 00 00 78 00 01 11
|
||||
/* display on + delay 120ms */
|
||||
05 01 00 00 78 00 01 29
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <32>;
|
||||
qcom,mdss-dsc-slice-width = <1080>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,136 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au {
|
||||
qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,vert-padding-value = <2940>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 07 FF
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 02
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
1280
qcom/opensource/display-devicetree/display/dsi-panel-sim-cmd.dtsi
Normal file
1280
qcom/opensource/display-devicetree/display/dsi-panel-sim-cmd.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,284 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"Simulator cmd mode DSC 3.75:1 dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,adjust-timer-wakeup-ms = <1>;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-ack-disabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <2560>;
|
||||
qcom,mdss-dsi-h-front-porch = <100>;
|
||||
qcom,mdss-dsi-h-back-porch = <32>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <10>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
/* CMD2_P0 */
|
||||
15 01 00 00 00 00 02 ff 20
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 01
|
||||
15 01 00 00 00 00 02 01 55
|
||||
15 01 00 00 00 00 02 02 45
|
||||
15 01 00 00 00 00 02 05 40
|
||||
15 01 00 00 00 00 02 06 19
|
||||
15 01 00 00 00 00 02 07 1e
|
||||
15 01 00 00 00 00 02 0b 73
|
||||
15 01 00 00 00 00 02 0c 73
|
||||
15 01 00 00 00 00 02 0e b0
|
||||
15 01 00 00 00 00 02 0f aE
|
||||
15 01 00 00 00 00 02 11 b8
|
||||
15 01 00 00 00 00 02 13 00
|
||||
15 01 00 00 00 00 02 58 80
|
||||
15 01 00 00 00 00 02 59 01
|
||||
15 01 00 00 00 00 02 5a 00
|
||||
15 01 00 00 00 00 02 5b 01
|
||||
15 01 00 00 00 00 02 5c 80
|
||||
15 01 00 00 00 00 02 5d 81
|
||||
15 01 00 00 00 00 02 5e 00
|
||||
15 01 00 00 00 00 02 5f 01
|
||||
15 01 00 00 00 00 02 72 31
|
||||
15 01 00 00 00 00 02 68 03
|
||||
/* CMD2_P4 */
|
||||
15 01 00 00 00 00 02 ff 24
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
15 01 00 00 00 00 02 00 1c
|
||||
15 01 00 00 00 00 02 01 0b
|
||||
15 01 00 00 00 00 02 02 0c
|
||||
15 01 00 00 00 00 02 03 01
|
||||
15 01 00 00 00 00 02 04 0f
|
||||
15 01 00 00 00 00 02 05 10
|
||||
15 01 00 00 00 00 02 06 10
|
||||
15 01 00 00 00 00 02 07 10
|
||||
15 01 00 00 00 00 02 08 89
|
||||
15 01 00 00 00 00 02 09 8a
|
||||
15 01 00 00 00 00 02 0a 13
|
||||
15 01 00 00 00 00 02 0b 13
|
||||
15 01 00 00 00 00 02 0c 15
|
||||
15 01 00 00 00 00 02 0d 15
|
||||
15 01 00 00 00 00 02 0e 17
|
||||
15 01 00 00 00 00 02 0f 17
|
||||
15 01 00 00 00 00 02 10 1c
|
||||
15 01 00 00 00 00 02 11 0b
|
||||
15 01 00 00 00 00 02 12 0c
|
||||
15 01 00 00 00 00 02 13 01
|
||||
15 01 00 00 00 00 02 14 0f
|
||||
15 01 00 00 00 00 02 15 10
|
||||
15 01 00 00 00 00 02 16 10
|
||||
15 01 00 00 00 00 02 17 10
|
||||
15 01 00 00 00 00 02 18 89
|
||||
15 01 00 00 00 00 02 19 8a
|
||||
15 01 00 00 00 00 02 1a 13
|
||||
15 01 00 00 00 00 02 1b 13
|
||||
15 01 00 00 00 00 02 1c 15
|
||||
15 01 00 00 00 00 02 1d 15
|
||||
15 01 00 00 00 00 02 1e 17
|
||||
15 01 00 00 00 00 02 1f 17
|
||||
/* STV */
|
||||
15 01 00 00 00 00 02 20 40
|
||||
15 01 00 00 00 00 02 21 01
|
||||
15 01 00 00 00 00 02 22 00
|
||||
15 01 00 00 00 00 02 23 40
|
||||
15 01 00 00 00 00 02 24 40
|
||||
15 01 00 00 00 00 02 25 6d
|
||||
15 01 00 00 00 00 02 26 40
|
||||
15 01 00 00 00 00 02 27 40
|
||||
/* Vend */
|
||||
15 01 00 00 00 00 02 e0 00
|
||||
15 01 00 00 00 00 02 dc 21
|
||||
15 01 00 00 00 00 02 dd 22
|
||||
15 01 00 00 00 00 02 de 07
|
||||
15 01 00 00 00 00 02 df 07
|
||||
15 01 00 00 00 00 02 e3 6d
|
||||
15 01 00 00 00 00 02 e1 07
|
||||
15 01 00 00 00 00 02 e2 07
|
||||
/* UD */
|
||||
15 01 00 00 00 00 02 29 d8
|
||||
15 01 00 00 00 00 02 2a 2a
|
||||
/* CLK */
|
||||
15 01 00 00 00 00 02 4b 03
|
||||
15 01 00 00 00 00 02 4c 11
|
||||
15 01 00 00 00 00 02 4d 10
|
||||
15 01 00 00 00 00 02 4e 01
|
||||
15 01 00 00 00 00 02 4f 01
|
||||
15 01 00 00 00 00 02 50 10
|
||||
15 01 00 00 00 00 02 51 00
|
||||
15 01 00 00 00 00 02 52 80
|
||||
15 01 00 00 00 00 02 53 00
|
||||
15 01 00 00 00 00 02 56 00
|
||||
15 01 00 00 00 00 02 54 07
|
||||
15 01 00 00 00 00 02 58 07
|
||||
15 01 00 00 00 00 02 55 25
|
||||
/* Reset XDONB */
|
||||
15 01 00 00 00 00 02 5b 43
|
||||
15 01 00 00 00 00 02 5c 00
|
||||
15 01 00 00 00 00 02 5f 73
|
||||
15 01 00 00 00 00 02 60 73
|
||||
15 01 00 00 00 00 02 63 22
|
||||
15 01 00 00 00 00 02 64 00
|
||||
15 01 00 00 00 00 02 67 08
|
||||
15 01 00 00 00 00 02 68 04
|
||||
/* Resolution:1440x2560*/
|
||||
15 01 00 00 00 00 02 72 02
|
||||
/* mux */
|
||||
15 01 00 00 00 00 02 7a 80
|
||||
15 01 00 00 00 00 02 7b 91
|
||||
15 01 00 00 00 00 02 7c d8
|
||||
15 01 00 00 00 00 02 7d 60
|
||||
15 01 00 00 00 00 02 7f 15
|
||||
15 01 00 00 00 00 02 75 15
|
||||
/* ABOFF */
|
||||
15 01 00 00 00 00 02 b3 c0
|
||||
15 01 00 00 00 00 02 b4 00
|
||||
15 01 00 00 00 00 02 b5 00
|
||||
/* Source EQ */
|
||||
15 01 00 00 00 00 02 78 00
|
||||
15 01 00 00 00 00 02 79 00
|
||||
15 01 00 00 00 00 02 80 00
|
||||
15 01 00 00 00 00 02 83 00
|
||||
/* FP BP */
|
||||
15 01 00 00 00 00 02 93 0a
|
||||
15 01 00 00 00 00 02 94 0a
|
||||
/* Inversion Type */
|
||||
15 01 00 00 00 00 02 8a 00
|
||||
15 01 00 00 00 00 02 9b ff
|
||||
/* IMGSWAP =1 @PortSwap=1 */
|
||||
15 01 00 00 00 00 02 9d b0
|
||||
15 01 00 00 00 00 02 9f 63
|
||||
15 01 00 00 00 00 02 98 10
|
||||
/* FRM */
|
||||
15 01 00 00 00 00 02 ec 00
|
||||
/* CMD1 */
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* VESA DSC PPS settings
|
||||
* (1440x2560 slide 16H)
|
||||
*/
|
||||
39 01 00 00 00 00 11 c1 09
|
||||
20 00 10 02 00 02 68 01 bb
|
||||
00 0a 06 67 04 c5
|
||||
|
||||
39 01 00 00 00 00 03 c2 10 f0
|
||||
/* C0h = 0x0(2 Port SDC)
|
||||
* 0x01(1 PortA FBC)
|
||||
* 0x02(MTK) 0x03(1 PortA VESA)
|
||||
*/
|
||||
15 01 00 00 00 00 02 c0 03
|
||||
/* VBP+VSA=,VFP = 10H */
|
||||
15 01 00 00 00 00 04 3b 03 0a 0a
|
||||
/* FTE on */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
/* EN_BK =1(auto black) */
|
||||
15 01 00 00 00 00 02 e5 01
|
||||
/* CMD mode(10) VDO mode(03) */
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
/* Non Reload MTP */
|
||||
15 01 00 00 00 00 02 fb 01
|
||||
05 01 00 00 f0 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [05 01 00 00 78 00
|
||||
02 28 00 05 01 00 00 78 00 02 10 00];
|
||||
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <16>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <0>;
|
||||
qcom,mdss-dsi-h-back-porch = <0>;
|
||||
qcom,mdss-dsi-h-pulse-width = <0>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <0>;
|
||||
qcom,mdss-dsi-v-front-porch = <0>;
|
||||
qcom,mdss-dsi-v-pulse-width = <0>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
15 01 00 00 00 00 02 bb 10
|
||||
15 01 00 00 00 00 02 b0 03
|
||||
05 01 00 00 78 00 01 11
|
||||
15 01 00 00 00 00 02 51 ff
|
||||
15 01 00 00 00 00 02 53 24
|
||||
15 01 00 00 00 00 02 ff 23
|
||||
15 01 00 00 00 00 02 08 05
|
||||
15 01 00 00 00 00 02 46 90
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
15 01 00 00 00 00 02 ff f0
|
||||
15 01 00 00 00 00 02 92 01
|
||||
15 01 00 00 00 00 02 ff 10
|
||||
/* enable TE generation */
|
||||
15 01 00 00 00 00 02 35 00
|
||||
05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 10 00 01 28
|
||||
05 01 00 00 40 00 01 10];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <16>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <2>;
|
||||
qcom,mdss-dsc-bit-per-component = <10>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,263 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
qcom,mdss-dsi-bpp-switch;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,cmd-sync-wait-broadcast;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-hor-line-idle = <0 40 256>,
|
||||
<40 120 128>,
|
||||
<120 240 64>;
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <30>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <2520>;
|
||||
qcom,mdss-dsi-panel-height = <2160>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,dsi-wd-jitter-enable;
|
||||
qcom,mdss-dsi-panel-jitter = <0x2 0x1>;
|
||||
qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>;
|
||||
qcom,dsi-wd-ltj-time-sec = <3600>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-mdp-transfer-time-us-min = <14000>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <16000>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <28>;
|
||||
qcom,mdss-dsi-h-back-porch = <4>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <12>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,dsi-wd-jitter-enable;
|
||||
qcom,mdss-dsi-panel-jitter = <0x2 0x1>;
|
||||
qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>;
|
||||
qcom,dsi-wd-ltj-time-sec = <3600>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-mdp-transfer-time-us-min = <6900>;
|
||||
qcom,mdss-mdp-transfer-time-us-max = <7900>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-width = <1280>;
|
||||
qcom,mdss-dsi-panel-height = <1440>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <3840>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <40>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
cell-index = <4>;
|
||||
qcom,mdss-dsi-panel-width = <2520>;
|
||||
qcom,mdss-dsi-panel-height = <2160>;
|
||||
qcom,mdss-dsi-h-front-porch = <30>;
|
||||
qcom,mdss-dsi-h-back-porch = <100>;
|
||||
qcom,mdss-dsi-h-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <7>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <1>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <80>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@5 {
|
||||
cell-index = <5>;
|
||||
qcom,mdss-dsi-bpp-mode= <24>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <80>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
};
|
||||
|
||||
timing@6 {
|
||||
cell-index = <6>;
|
||||
qcom,mdss-dsi-bpp-mode= <30>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <540>;
|
||||
qcom,mdss-dsi-panel-height = <1920>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <80>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 00 00 02 28 00
|
||||
05 01 00 00 00 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video {
|
||||
qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0 1>;
|
||||
qcom,dsi-phy-num = <0 1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-panel-broadcast-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <1280>;
|
||||
qcom,mdss-dsi-panel-height = <1440>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <44>;
|
||||
qcom,mdss-dsi-h-pulse-width = <16>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <4>;
|
||||
qcom,mdss-dsi-v-front-porch = <8>;
|
||||
qcom,mdss-dsi-v-pulse-width = <4>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command =
|
||||
[05 01 00 00 32 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands =
|
||||
[15 01 00 00 00 00 02 51 00];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,69 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"sim hd command mode secondary dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "burst_mode";
|
||||
qcom,panel-ack-disabled;
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
qcom,mdss-dsi-tx-eot-append;
|
||||
qcom,mdss-dsi-post-init-delay = <1>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-width = <720>;
|
||||
qcom,mdss-dsi-panel-height = <1280>;
|
||||
qcom,mdss-dsi-h-front-porch = <120>;
|
||||
qcom,mdss-dsi-h-back-porch = <60>;
|
||||
qcom,mdss-dsi-h-pulse-width = <12>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <2>;
|
||||
qcom,mdss-dsi-v-front-porch = <12>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-on-command = [
|
||||
05 01 00 00 f0 00 01 00
|
||||
];
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 78 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00
|
||||
];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,71 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_sim_vid: qcom,mdss_dsi_sim_video {
|
||||
qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-t-clk-post = <0x04>;
|
||||
qcom,mdss-dsi-t-clk-pre = <0x1b>;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>;
|
||||
qcom,panel-ack-disabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-width = <1440>;
|
||||
qcom,mdss-dsi-panel-height = <2560>;
|
||||
qcom,mdss-dsi-h-front-porch = <8>;
|
||||
qcom,mdss-dsi-h-back-porch = <8>;
|
||||
qcom,mdss-dsi-h-pulse-width = <8>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <6>;
|
||||
qcom,mdss-dsi-v-front-porch = <6>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-on-command =
|
||||
[32 01 00 00 00 00 02 00 00];
|
||||
qcom,mdss-dsi-off-command =
|
||||
[22 01 00 00 00 00 02 00 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
|
||||
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <720>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,365 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled cmd mode 120hz dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <683100000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode 120hz dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,557 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled cmd mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-panel-mode-switch;
|
||||
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,spr-pack-type = "pentile";
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-video-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <10>;
|
||||
qcom,mdss-dsi-h-back-porch = <16>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <8>;
|
||||
qcom,mdss-dsi-v-front-porch = <18>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
];
|
||||
|
||||
qcom,cmd-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,vid-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
|
||||
qcom,cmd-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 07
|
||||
];
|
||||
qcom,cmd-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-in-commands = [
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
];
|
||||
qcom,video-mode-switch-in-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 03
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
];
|
||||
qcom,video-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
cell-index = <3>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <813936000>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,134 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,spr-pack-type = "pentile";
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,164 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled qsync cmd mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <95>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-on-commands = [
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 3c 00 3c 00
|
||||
0c 00 0c 04 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 0c bb 00 4c 00 01 00
|
||||
01 32 01 6e 01 6e
|
||||
39 01 00 00 00 00 02 bb 01
|
||||
];
|
||||
qcom,mdss-dsi-qsync-on-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-qsync-off-commands = [
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 02 bb 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
];
|
||||
qcom,mdss-dsi-qsync-off-commands-state =
|
||||
"dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled qsync video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,qsync-enable;
|
||||
qcom,mdss-dsi-qsync-min-refresh-rate = <80>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <144>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 09
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 09 11 09 11 08
|
||||
c1 07 fa 05 a4 00 3c 00 34 00 24 00
|
||||
0c 00 0c 04 00 35
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
503
qcom/opensource/display-devicetree/display/sun-sde-common.dtsi
Normal file
503
qcom/opensource/display-devicetree/display/sun-sde-common.dtsi
Normal file
@@ -0,0 +1,503 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
&soc {
|
||||
mdss_mdp: qcom,mdss_mdp@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sde-kms";
|
||||
reg = <0x0ae00000 0x93800>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0af80000 0x7000>,
|
||||
<0x400000 0x2000>;
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys",
|
||||
"ipcc_reg";
|
||||
|
||||
/* interrupt config */
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#cooling-cells = <2>;
|
||||
|
||||
/* hw blocks */
|
||||
qcom,sde-off = <0x1000>;
|
||||
qcom,sde-len = <0x488>;
|
||||
|
||||
qcom,sde-ctl-hyp-off = <0x15000>;
|
||||
qcom,sde-ctl-hyp-size = <0xc00>;
|
||||
|
||||
qcom,sde-ctl-off = <0x16000 0x17000 0x18000
|
||||
0x19000 0x1a000 0x1b000>;
|
||||
qcom,sde-ctl-size = <0x1000>;
|
||||
qcom,sde-ctl-display-pref = "primary", "none", "none",
|
||||
"none", "none", "none";
|
||||
|
||||
qcom,sde-mixer-off = <0x45000 0x46000 0x47000
|
||||
0x48000 0x49000 0x4a000
|
||||
0x4b000 0x4c000 0x0f0f
|
||||
0x0f0f 0x0f0f 0x0f0f>;
|
||||
qcom,sde-mixer-size = <0x400>;
|
||||
qcom,sde-mixer-display-pref = "primary", "primary", "none",
|
||||
"none", "none", "none", "none", "none",
|
||||
"none", "none", "none", "none";
|
||||
|
||||
qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none",
|
||||
"none", "none", "none", "none",
|
||||
"dcwb", "dcwb", "dcwb", "dcwb";
|
||||
|
||||
qcom,sde-dspp-top-off = <0x1300>;
|
||||
qcom,sde-dspp-top-size = <0x8c>;
|
||||
|
||||
qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
|
||||
qcom,sde-dspp-size = <0x1800>;
|
||||
|
||||
qcom,sde-dspp-rc-version = <0x00010001>;
|
||||
qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800 0x12800>;
|
||||
qcom,sde-dspp-rc-size = <0x100>;
|
||||
qcom,sde-dspp-rc-mem-size = <2720>;
|
||||
qcom,sde-dspp-rc-min-region-width = <20>;
|
||||
|
||||
qcom,sde-dnsc-blur-version = <0x100>;
|
||||
qcom,sde-dnsc-blur-off = <0x7D000>;
|
||||
qcom,sde-dnsc-blur-size = <0x40>;
|
||||
qcom,sde-dnsc-blur-gaus-lut-off = <0x100>;
|
||||
qcom,sde-dnsc-blur-gaus-lut-size = <0x400>;
|
||||
qcom,sde-dnsc-blur-dither-off = <0x5E0>;
|
||||
qcom,sde-dnsc-blur-dither-size = <0x20>;
|
||||
|
||||
qcom,sde-dest-scaler-top-off = <0x0008F000>;
|
||||
qcom,sde-dest-scaler-top-size = <0x1C>;
|
||||
qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000 0x3000>;
|
||||
qcom,sde-dest-scaler-size = <0x800>;
|
||||
|
||||
qcom,sde-wb-off = <0x65000 0x66000>;
|
||||
qcom,sde-wb-size = <0x2c8>;
|
||||
qcom,sde-wb-xin-id = <0xa 6>;
|
||||
qcom,sde-wb-id = <1 2>;
|
||||
|
||||
qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>;
|
||||
qcom,sde-intf-size = <0x4BC>;
|
||||
qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
|
||||
qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
|
||||
|
||||
qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000
|
||||
0x6e000 0x6f000 0x70000 0x71000
|
||||
0x67000 0x67400 0x7f000 0x7f400>;
|
||||
qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
qcom,sde-pp-size = <0x2c>;
|
||||
qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3 0x4 0x4 0x5 0x5>;
|
||||
|
||||
qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000 0x52000 0x67700 0x7f700>;
|
||||
qcom,sde-merge-3d-size = <0x1c>;
|
||||
qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
|
||||
|
||||
qcom,sde-cdm-off = <0x7a200>;
|
||||
qcom,sde-cdm-size = <0x240>;
|
||||
|
||||
qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000 0x83000 0x83000 0x84000 0x84000>;
|
||||
qcom,sde-dsc-size = <0x8>;
|
||||
qcom,sde-dsc-pair-mask = <2 1 4 3 6 5 8 7>;
|
||||
qcom,sde-dsc-hw-rev = "dsc_1_2";
|
||||
qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200 0x100 0x200 0x100 0x200>;
|
||||
qcom,sde-dsc-enc-size = <0x100>;
|
||||
qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80 0xF00 0xF80 0xF00 0xF80>;
|
||||
qcom,sde-dsc-ctl-size = <0x24>;
|
||||
qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>;
|
||||
|
||||
qcom,sde-dither-off = <0xe0 0xe0 0xe0
|
||||
0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>;
|
||||
qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>;
|
||||
qcom,sde-dither-version = <0x00020000>;
|
||||
qcom,sde-dither-size = <0x20>;
|
||||
|
||||
qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
|
||||
"dma", "dma", "dma", "dma", "dma", "dma";
|
||||
qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
|
||||
0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>;
|
||||
qcom,sde-sspp-src-size = <0x344>;
|
||||
|
||||
qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 14 15>;
|
||||
qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1 1 1 1>;
|
||||
qcom,sde-sspp-smart-dma-priority = <7 8 9 10 1 2 3 4 5 6>;
|
||||
qcom,sde-smart-dma-rev = "smart_dma_v2p5";
|
||||
|
||||
qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7 10 9 12 11>;
|
||||
|
||||
qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130
|
||||
0x160 0x190 0x1c0 0x1f0 0x220>;
|
||||
|
||||
qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000
|
||||
4500000 4500000
|
||||
4500000 4500000
|
||||
4500000 4500000
|
||||
4500000 4500000>;
|
||||
|
||||
qcom,sde-max-per-pipe-bw-high-kbps = <5700000 5700000
|
||||
5700000 5700000
|
||||
5700000 5700000
|
||||
5700000 5700000
|
||||
5700000 5700000>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-sspp-clk-ctrl =
|
||||
<0x4330 0>, <0x6330 0>, <0x8330 0>, <0xa330 0>,
|
||||
<0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>,
|
||||
<0x2c330 0>, <0x2e330 0>;
|
||||
qcom,sde-sspp-clk-status =
|
||||
<0x4334 0>, <0x6334 0>, <0x8334 0>, <0xa334 0>,
|
||||
<0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>,
|
||||
<0x2c334 0>, <0x2e334 0>;
|
||||
qcom,sde-sspp-csc-off = <0x1a00>;
|
||||
qcom,sde-csc-type = "csc-10bit";
|
||||
qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
|
||||
qcom,sde-qseed-scalar-version = <0x3004>;
|
||||
qcom,sde-sspp-qseed-off = <0xa00>;
|
||||
qcom,sde-mixer-linewidth = <2560>;
|
||||
qcom,sde-sspp-linewidth = <5120>;
|
||||
qcom,sde-wb-linewidth = <4096>;
|
||||
qcom,sde-dsc-linewidth = <2560>;
|
||||
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
|
||||
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
|
||||
qcom,sde-wb-linewidth-linear = <8192>;
|
||||
qcom,sde-mixer-blendstages = <0xb>;
|
||||
qcom,sde-highest-bank-bit = <0x8 0x3>,
|
||||
<0x7 0x2>;
|
||||
qcom,sde-ubwc-version = <0x50000001>;
|
||||
qcom,sde-ubwc-swizzle = <0x6>;
|
||||
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
||||
qcom,sde-ubwc-static = <0x1>;
|
||||
qcom,sde-macrotile-mode = <0x1>;
|
||||
qcom,sde-smart-panel-align-mode = <0xc>;
|
||||
qcom,sde-panic-per-pipe;
|
||||
qcom,sde-has-cdp;
|
||||
qcom,sde-has-src-split;
|
||||
qcom,sde-pipe-order-version = <0x1>;
|
||||
qcom,sde-has-dim-layer;
|
||||
qcom,sde-has-dest-scaler;
|
||||
qcom,sde-max-trusted-vm-displays = <1>;
|
||||
|
||||
qcom,sde-max-bw-low-kbps = <18900000>;
|
||||
qcom,sde-max-bw-high-kbps = <28500000>;
|
||||
qcom,sde-min-core-ib-kbps = <2500000>;
|
||||
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||
qcom,sde-min-dram-ib-kbps = <800000>;
|
||||
qcom,sde-dram-channels = <4>;
|
||||
qcom,sde-num-nrt-paths = <0>;
|
||||
|
||||
qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>;
|
||||
qcom,sde-dspp-spr-size = <0x200>;
|
||||
qcom,sde-dspp-spr-version = <0x00020000>;
|
||||
|
||||
qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>;
|
||||
qcom,sde-dspp-demura-size = <0x150>;
|
||||
qcom,sde-dspp-demura-version = <0x00030000>;
|
||||
|
||||
qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>;
|
||||
qcom,sde-dspp-aiqe-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-size = <0x3fc>;
|
||||
|
||||
qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>;
|
||||
qcom,sde-dspp-aiqe-dither-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-dither-size = <0x20>;
|
||||
|
||||
qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>;
|
||||
qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-wrapper-size = <0x1c>;
|
||||
|
||||
qcom,sde-dspp-aiqe-aiscaler-off = <0x30000 0xffffffff>;
|
||||
qcom,sde-dspp-aiqe-aiscaler-version = <0x00010000>;
|
||||
qcom,sde-dspp-aiqe-aiscaler-size = <0x7d0>;
|
||||
|
||||
qcom,sde-aiqe-has-feature-mdnie;
|
||||
qcom,sde-aiqe-has-feature-abc;
|
||||
qcom,sde-aiqe-has-feature-ssrc;
|
||||
qcom,sde-aiqe-has-feature-copr;
|
||||
qcom,sde-aiqe-has-feature-aiscaler;
|
||||
|
||||
qcom,sde-lm-noise-off = <0x320>;
|
||||
qcom,sde-lm-noise-version = <0x00010000>;
|
||||
|
||||
qcom,sde-uidle-off = <0x80000>;
|
||||
qcom,sde-uidle-size = <0x80>;
|
||||
|
||||
qcom,sde-vbif-off = <0>;
|
||||
qcom,sde-vbif-size = <0x1074>;
|
||||
qcom,sde-vbif-id = <0>;
|
||||
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-vbif-default-ot-rd-limit = <40>;
|
||||
qcom,sde-vbif-default-ot-wr-limit = <32>;
|
||||
qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;
|
||||
|
||||
qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||
qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>;
|
||||
qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>;
|
||||
qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>;
|
||||
|
||||
qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>;
|
||||
|
||||
qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001
|
||||
0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>;
|
||||
|
||||
qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x0 0x0 0x0 0x0
|
||||
0x77776666 0x66666540 0x77776666 0x66666540
|
||||
0x77776541 0x0 0x77776541 0x0
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x0 0x0 0x0 0x0
|
||||
0x55555544 0x33221100 0x55555544 0x33221100>;
|
||||
|
||||
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
||||
|
||||
qcom,sde-qos-cpu-mask = <0x3>;
|
||||
qcom,sde-qos-cpu-mask-performance = <0x3>;
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
qcom,sde-ipcc-protocol-id = <0x4>;
|
||||
qcom,sde-ipcc-client-dpu-phys-id = <0x14>;
|
||||
qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-reg-dma-off = <0 0x800>;
|
||||
qcom,sde-reg-dma-id = <0 1>;
|
||||
qcom,sde-reg-dma-version = <0x00030000>;
|
||||
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
||||
qcom,sde-reg-dma-xin-id = <7>;
|
||||
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
||||
|
||||
qcom,sde-secure-sid-mask = <0x0002801 0x0002c01>;
|
||||
|
||||
qcom,sde-reg-bus,vectors-KBps = <0 0>,
|
||||
<0 14000>,
|
||||
<0 140000>,
|
||||
<0 310000>;
|
||||
|
||||
qcom,sde-sspp-vig-blocks {
|
||||
vcm@0 {
|
||||
cell-index = <0>;
|
||||
qcom,sde-vig-top-off = <0x700>;
|
||||
qcom,sde-vig-csc-off = <0x1a00>;
|
||||
qcom,sde-vig-qseed-off = <0xa00>;
|
||||
qcom,sde-vig-qseed-size = <0xe0>;
|
||||
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
|
||||
qcom,sde-vig-igc = <0x1d00 0x00060000>;
|
||||
qcom,sde-vig-inverse-pma;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
qcom,sde-ucsc-igc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-unmult = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-gc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-csc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
||||
};
|
||||
|
||||
vcm@1 {
|
||||
cell-index = <1>;
|
||||
qcom,sde-fp16-igc = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x280 0x00010000>;
|
||||
qcom,sde-ucsc-igc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-gc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-csc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sde-sspp-dma-blocks {
|
||||
dgm@0 {
|
||||
cell-index = <0>;
|
||||
qcom,sde-dma-top-off = <0x700>;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
qcom,sde-ucsc-igc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-unmult = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-gc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-csc = <0x700 0x00010001>;
|
||||
qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>;
|
||||
};
|
||||
|
||||
dgm@1 {
|
||||
cell-index = <1>;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
qcom,sde-ucsc-igc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-unmult = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-gc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-csc = <0x1700 0x00010001>;
|
||||
qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sde-dspp-blocks {
|
||||
qcom,sde-dspp-igc = <0x1260 0x00050000>;
|
||||
qcom,sde-dspp-hsic = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
|
||||
qcom,sde-dspp-hist = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-sixzone = <0x900 0x00020000>;
|
||||
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
|
||||
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
|
||||
qcom,sde-dspp-pcc = <0x1700 0x00060000>;
|
||||
qcom,sde-dspp-gc = <0x17c0 0x00020000>;
|
||||
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.9";
|
||||
label = "dsi-ctrl-0";
|
||||
cell-index = <0>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae94000 0x1000>,
|
||||
<0xaf0f000 0x4>,
|
||||
<0x0ae36000 0x300>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <16600>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.9";
|
||||
label = "dsi-ctrl-1";
|
||||
cell-index = <1>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae96000 0x1000>,
|
||||
<0xaf0f000 0x4>,
|
||||
<0x0ae37000 0x300>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <5 0>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <16600>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
|
||||
compatible = "qcom,dsi-phy-v7.2";
|
||||
label = "dsi-phy-0";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae95000 0xa00>,
|
||||
<0xae95500 0x400>,
|
||||
<0xae94200 0xa0>;
|
||||
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_3nm";
|
||||
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <98000>;
|
||||
qcom,supply-disable-load = <96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 {
|
||||
compatible = "qcom,dsi-phy-v7.2";
|
||||
label = "dsi-phy-1";
|
||||
cell-index = <1>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae97000 0xa00>,
|
||||
<0xae97500 0x400>,
|
||||
<0xae96200 0xa0>;
|
||||
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_3nm";
|
||||
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <98000>;
|
||||
qcom,supply-disable-load = <96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_pll_codes_data:dsi_pll_codes {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
label = "dsi_pll_codes";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun ATP";
|
||||
compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||
qcom,board-id = <0x10021 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x20001 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x60001 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x40001 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp-no-display.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP No Display";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x30001 0>;
|
||||
};
|
||||
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sim_vid>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp",
|
||||
"qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x50001 0>;
|
||||
};
|
||||
@@ -0,0 +1,319 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_dsc_10b_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_spr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_vid_spr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_ddicspr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_ddicspr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
avdd-supply = <&display_panel_avdd>;
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr
|
||||
&dsi_nt37801_amoled_qsync_cmd
|
||||
&dsi_nt37801_amoled_qsync_video
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd
|
||||
&dsi_nt37801_amoled_cmd_ddicspr
|
||||
&dsi_nt37801_amoled_video_ddicspr>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se15_i2c {
|
||||
status = "disabled";
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_qsync_cmd
|
||||
&dsi_nt37801_amoled_qsync_video
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd
|
||||
&dsi_nt37801_amoled_cmd_ddicspr
|
||||
&dsi_nt37801_amoled_video_ddicspr>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,9 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&mdss_mdp {
|
||||
qcom,sde-emulated-env;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-hdk.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. SunP QRD HDK";
|
||||
compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk";
|
||||
qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x1001f 0>;
|
||||
};
|
||||
@@ -0,0 +1,291 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
lt9611_pins: lt9611_pins {
|
||||
mux {
|
||||
pins = "gpio69", "gpio60", "gpio214", "gpio83";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio69", "gpio60", "gpio214", "gpio83";
|
||||
drive-strength = <8>;
|
||||
bias-disable = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se5_i2c {
|
||||
status = "ok";
|
||||
|
||||
lt9611: lt,lt9611@2b {
|
||||
compatible = "lt,lt9611uxc";
|
||||
reg = <0x2b>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <44 0>;
|
||||
interrupt-names = "lt_irq";
|
||||
lt,irq-gpio = <&tlmm 69 0x0>;
|
||||
lt,reset-gpio = <&tlmm 60 0x0>;
|
||||
lt,hdmi-3p3-en = <&tlmm 214 0x0>;
|
||||
lt,hdmi-1p2-en = <&tlmm 83 0x0>;
|
||||
lt,non-pluggable;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <<9611_pins>;
|
||||
|
||||
lt,preferred-mode = "1920x1080";
|
||||
|
||||
lt,customize-modes {
|
||||
lt,customize-mode-id@0 {
|
||||
lt,mode-h-active = <1920>;
|
||||
lt,mode-h-front-porch = <88>;
|
||||
lt,mode-h-pulse-width = <44>;
|
||||
lt,mode-h-back-porch = <148>;
|
||||
lt,mode-h-active-high;
|
||||
lt,mode-v-active = <1080>;
|
||||
lt,mode-v-front-porch = <4>;
|
||||
lt,mode-v-pulse-width = <5>;
|
||||
lt,mode-v-back-porch = <36>;
|
||||
lt,mode-v-active-high;
|
||||
lt,mode-clock-in-khz = <148500>;
|
||||
};
|
||||
|
||||
lt,customize-mode-id@1 {
|
||||
lt,mode-h-active = <3840>;
|
||||
lt,mode-h-front-porch = <176>;
|
||||
lt,mode-h-pulse-width = <88>;
|
||||
lt,mode-h-back-porch = <400>;
|
||||
lt,mode-h-active-high;
|
||||
lt,mode-v-active = <2160>;
|
||||
lt,mode-v-front-porch = <8>;
|
||||
lt,mode-v-pulse-width = <10>;
|
||||
lt,mode-v-back-porch = <72>;
|
||||
lt,mode-v-active-high;
|
||||
lt,mode-clock-in-khz = <608040>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lt9611_in_0: endpoint {
|
||||
remote-endpoint = <&ext_dsi_0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
ext_dsi_0_out: endpoint {
|
||||
remote-endpoint = <<9611_in_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video>;
|
||||
};
|
||||
|
||||
&qupv3_se4_spi {
|
||||
goodix-berlin@0 {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_ext_bridge_1080p>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x60008 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x20008 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x50008 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x30008 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <8 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP QMP1000";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x108 0>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x40108 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
|
||||
"qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x40008 0>;
|
||||
};
|
||||
@@ -0,0 +1,300 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_dsc_10b_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_spr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_vid_spr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_ddicspr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_ddicspr {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr
|
||||
&dsi_nt37801_amoled_qsync_cmd
|
||||
&dsi_nt37801_amoled_qsync_video
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd
|
||||
&dsi_nt37801_amoled_cmd_ddicspr
|
||||
&dsi_nt37801_amoled_video_ddicspr>;
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr
|
||||
&dsi_nt37801_amoled_dsc_10b_cmd
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_qsync_cmd
|
||||
&dsi_nt37801_amoled_qsync_video
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd
|
||||
&dsi_nt37801_amoled_cmd_ddicspr
|
||||
&dsi_nt37801_amoled_video_ddicspr>;
|
||||
};
|
||||
@@ -0,0 +1,168 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
&tlmm {
|
||||
pmx_sde: pmx_sde {
|
||||
sde_dsi_active: sde_dsi_active {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi_suspend: sde_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio98";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio98";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_active: sde_dsi1_active {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi1_suspend: sde_dsi1_suspend {
|
||||
mux {
|
||||
pins = "gpio97";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio97";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_te: pmx_sde_te {
|
||||
sde_te_active: sde_te_active {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te_suspend: sde_te_suspend {
|
||||
mux {
|
||||
pins = "gpio86";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio86";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_active: sde_te1_active {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te1_suspend: sde_te1_suspend {
|
||||
mux {
|
||||
pins = "gpio87";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio87";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_esync: pmx_sde_esync {
|
||||
sde_esync0_active: sde_esync0_active {
|
||||
mux {
|
||||
pins = "gpio88";
|
||||
function = "mdp_esync0_out";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio88";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_esync0_suspend: sde_esync0_suspend {
|
||||
mux {
|
||||
pins = "gpio88";
|
||||
function = "mdp_esync0_out";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio88";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_esync1_active: sde_esync1_active {
|
||||
mux {
|
||||
pins = "gpio100";
|
||||
function = "mdp_esync1_out";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio100";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_esync1_suspend: sde_esync1_suspend {
|
||||
mux {
|
||||
pins = "gpio100";
|
||||
function = "mdp_esync1_out";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio100";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x1000B 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x3000B 0>;
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
|
||||
<0x100026a 0x10000>, <0x100026a 0x20000>,
|
||||
<0x100027f 0x10000>, <0x100027f 0x20000>;
|
||||
qcom,board-id = <0x2000B 0>;
|
||||
};
|
||||
@@ -0,0 +1,236 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_cmd_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_qsync_video_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
|
||||
};
|
||||
|
||||
&qupv3_se4_spi {
|
||||
st_fts@0 {
|
||||
panel = <&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_qsync_cmd_cphy
|
||||
&dsi_nt37801_amoled_qsync_video_cphy>;
|
||||
};
|
||||
};
|
||||
|
||||
&battery_charger {
|
||||
qcom,display-panels = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_qsync_cmd_cphy
|
||||
&dsi_nt37801_amoled_qsync_video_cphy>;
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||
qcom,board-id = <0x40015 0>;
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||
qcom,board-id = <0x20015 0>;
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||
qcom,board-id = <0x15 0>;
|
||||
};
|
||||
@@ -0,0 +1,16 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-rcm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid";
|
||||
compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>;
|
||||
qcom,board-id = <0x30015 0>;
|
||||
};
|
||||
@@ -0,0 +1,6 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display-cdp.dtsi"
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde-display-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun RUMI";
|
||||
compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi";
|
||||
qcom,msm-id = <618 0x10000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display.dtsi"
|
||||
#include "sun-sde-display-emulated.dtsi"
|
||||
|
||||
322
qcom/opensource/display-devicetree/display/sun-sde-display.dtsi
Normal file
322
qcom/opensource/display-devicetree/display/sun-sde-display.dtsi
Normal file
@@ -0,0 +1,322 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde.dtsi"
|
||||
#include "sun-sde-display-common.dtsi"
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
|
||||
&pm8550_gpios {
|
||||
display_panel_avdd_default: display_panel_avdd_default {
|
||||
pins = "gpio11";
|
||||
function = "normal";
|
||||
input-disable;
|
||||
output-enable;
|
||||
bias-disable;
|
||||
power-source = <1>;
|
||||
qcom,drive-strength = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
sde_wb1: qcom,wb-display@1 {
|
||||
compatible = "qcom,wb-display";
|
||||
cell-index = <0>;
|
||||
label = "wb_display1";
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "mdp_core_clk";
|
||||
};
|
||||
|
||||
sde_wb2: qcom,wb-display@2 {
|
||||
compatible = "qcom,wb-display";
|
||||
cell-index = <1>;
|
||||
label = "wb_display2";
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "mdp_core_clk";
|
||||
};
|
||||
|
||||
|
||||
display_panel_avdd: display_gpio_regulator@1 {
|
||||
compatible = "qti-regulator-fixed";
|
||||
regulator-name = "display_panel_avdd";
|
||||
regulator-min-microvolt = <5500000>;
|
||||
regulator-max-microvolt = <5500000>;
|
||||
regulator-enable-ramp-delay = <233>;
|
||||
gpio = <&pm8550_gpios 11 0>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
proxy-supply = <&display_panel_avdd>;
|
||||
qcom,proxy-consumer-enable;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
disp_rdump_memory: disp_rdump_region@0xd5500000 {
|
||||
reg = <0xfc800000 0x00800000>;
|
||||
label = "disp_rdump_region";
|
||||
};
|
||||
};
|
||||
|
||||
&reserved_memory {
|
||||
splash_memory: splash_region {
|
||||
reg = <0x0 0xfc800000 0x0 0x02b00000>;
|
||||
label = "cont_splash_region";
|
||||
};
|
||||
/*
|
||||
* Demura memory regions are to be commented out if
|
||||
* feature not in use.
|
||||
*/
|
||||
/*
|
||||
demura_memory_0: demura_region_0 {
|
||||
reg = <0x0 0x0 0x0 0x0>;
|
||||
label = "demura hfc region 0";
|
||||
};
|
||||
|
||||
demura_memory_1: demura_region_1 {
|
||||
reg = <0x0 0x0 0x0 0x0>;
|
||||
label = "demura hfc region 1";
|
||||
};
|
||||
*/
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 0>,
|
||||
<&mdss_dsi_phy1 1>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
/*
|
||||
* The esync clk RCG is only necessary here to set its parent
|
||||
* to the pll dsi clk, which also needs to be available at the
|
||||
* point that its known whether the clock will be used. After
|
||||
* updating the parent, this clock handle is no longer needed.
|
||||
*/
|
||||
<&dispcc DISP_CC_ESYNC0_CLK_SRC>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk", "esync_clk_rcg";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
tvdd-supply = <&L4B>;
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
<&mdss_dsi_phy1 0>,
|
||||
<&mdss_dsi_phy1 1>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
/*
|
||||
* The esync clk RCG is only necessary here to set its parent
|
||||
* to the pll dsi clk, which also needs to be available at the
|
||||
* point that its known whether the clock will be used. After
|
||||
* updating the parent, this clock handle is no longer needed.
|
||||
*/
|
||||
<&dispcc DISP_CC_ESYNC1_CLK_SRC>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1",
|
||||
"mdp_core_clk", "esync_clk_rcg";
|
||||
vddio-supply = <&L12B>;
|
||||
vci-supply = <&L13B>;
|
||||
vdd-supply = <&L11B>;
|
||||
tvdd-supply = <&L4B>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2
|
||||
&sde_dp &sde_cesta>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_fhd_plus_cmd {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@4 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 540 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_spr {
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <720 40 720 40 1440 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd vid mode*/
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@2 { /* FHD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <540 20 540 20 540 20>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <360 40 360 40 360 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
14
qcom/opensource/display-devicetree/display/sun-sde.dts
Normal file
14
qcom/opensource/display-devicetree/display/sun-sde.dts
Normal file
@@ -0,0 +1,14 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "sun-sde.dtsi"
|
||||
|
||||
/ {
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
362
qcom/opensource/display-devicetree/display/sun-sde.dtsi
Normal file
362
qcom/opensource/display-devicetree/display/sun-sde.dtsi
Normal file
@@ -0,0 +1,362 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include <dt-bindings/interconnect/qcom,sun.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
|
||||
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
|
||||
#include "sun-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
ext_disp: qcom,msm-ext-disp {
|
||||
compatible = "qcom,msm-ext-disp";
|
||||
|
||||
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||
};
|
||||
};
|
||||
|
||||
qcom_msmhdcp: qcom,msm_hdcp {
|
||||
compatible = "qcom,msm-hdcp";
|
||||
};
|
||||
|
||||
sde_dp_pll: qcom,dp_pll@88eb000 {
|
||||
compatible = "qcom,dp-pll-3nm-v1";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sde_dp: qcom,dp_display@af54000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,dp-display";
|
||||
|
||||
usb-phy = <&usb_qmp_dp_phy>;
|
||||
qcom,ext-disp = <&ext_disp>;
|
||||
usb-controller = <&usb0>;
|
||||
qcom,altmode-dev = <&altmode 0>;
|
||||
qcom,dp-aux-switch = <&wcd_usbss>;
|
||||
|
||||
reg = <0xaf54000 0x104>,
|
||||
<0xaf54200 0x0c0>,
|
||||
<0xaf55000 0x770>,
|
||||
<0xaf56000 0x09c>,
|
||||
<0x88ebc00 0x200>,
|
||||
<0x88eb400 0x200>,
|
||||
<0x88eb800 0x200>,
|
||||
<0x88eb000 0x200>,
|
||||
<0x88e8000 0x020>,
|
||||
<0xaee1000 0x034>,
|
||||
<0xaf57000 0x09c>,
|
||||
<0xaf09000 0x014>;
|
||||
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
||||
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
||||
"dp_pll", "usb3_dp_com", "hdcp_physical",
|
||||
"dp_p1", "gdsc";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <12 0>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&tcsrcc TCSR_USB3_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&sde_dp_pll 0>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&sde_dp_pll 1>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
|
||||
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent",
|
||||
"link_iface_clk", "pixel_clk_rcg", "pixel_parent",
|
||||
"pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk";
|
||||
|
||||
qcom,dp-pll = <&sde_dp_pll>;
|
||||
qcom,phy-version = <0x800>;
|
||||
qcom,aux-cfg0-settings = [20 00];
|
||||
qcom,aux-cfg1-settings = [24 13];
|
||||
qcom,aux-cfg2-settings = [28 A4];
|
||||
qcom,aux-cfg3-settings = [2c 00];
|
||||
qcom,aux-cfg4-settings = [30 0a];
|
||||
qcom,aux-cfg5-settings = [34 26];
|
||||
qcom,aux-cfg6-settings = [38 0a];
|
||||
qcom,aux-cfg7-settings = [3c 03];
|
||||
qcom,aux-cfg8-settings = [40 b7];
|
||||
qcom,aux-cfg9-settings = [44 03];
|
||||
|
||||
qcom,max-pclk-frequency-khz = <675000>;
|
||||
|
||||
qcom,widebus-enable;
|
||||
qcom,4ppc-enable;
|
||||
qcom,mst-enable;
|
||||
qcom,dsc-feature-enable;
|
||||
qcom,fec-feature-enable;
|
||||
qcom,dsc-continuous-pps;
|
||||
|
||||
qcom,qos-cpu-mask = <0xf>;
|
||||
qcom,qos-cpu-latency-us = <300>;
|
||||
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
vdda-0p9-supply = <&L2D>;
|
||||
vdda_usb-0p9-supply = <&L2D>;
|
||||
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||
dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
|
||||
|
||||
qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>,
|
||||
<0x31 0x3e 0x3f 0xff>,
|
||||
<0x36 0x3f 0xff 0xff>,
|
||||
<0x3f 0xff 0xff 0xff>;
|
||||
qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>,
|
||||
<0x20 0x2e 0x35 0xff>,
|
||||
<0x20 0x2e 0xff 0xff>,
|
||||
<0x22 0xff 0xff 0xff>;
|
||||
|
||||
qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>,
|
||||
<0x29 0x39 0x3f 0xff>,
|
||||
<0x30 0x3f 0xff 0xff>,
|
||||
<0x3f 0xff 0xff 0xff>;
|
||||
qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>,
|
||||
<0x22 0x2e 0x36 0xff>,
|
||||
<0x22 0x31 0xff 0xff>,
|
||||
<0x24 0xff 0xff 0xff>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <30000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <912000>;
|
||||
qcom,supply-max-voltage = <912000>;
|
||||
qcom,supply-enable-load = <114000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
|
||||
qcom,phy-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vdda_usb-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <2500>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pll-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,pll-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdd_mx";
|
||||
qcom,supply-min-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,supply-max-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition {
|
||||
iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>,
|
||||
<&smmu_sde_unsec 0xd4e23000 0x002dd000>,
|
||||
<&smmu_sde_unsec 0xd2880000 0x05780000>,
|
||||
<&smmu_sde_unsec 0xa3500000 0x02c80000>,
|
||||
<&smmu_sde_unsec 0xfc800000 0x02b00000>,
|
||||
<&smmu_sde_sec 0x0 0x00020000>;
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
memory-region = <&smmu_sde_iommu_region_partition>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-earlymap; /* for cont-splash */
|
||||
dma-coherent;
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "mdp_core_clk";
|
||||
};
|
||||
|
||||
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||
compatible = "qcom,smmu_sde_sec";
|
||||
iommus = <&apps_smmu 0x801 0x0>;
|
||||
memory-region = <&smmu_sde_iommu_region_partition>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xa>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "mdp_core_clk";
|
||||
};
|
||||
|
||||
sde_cesta: qcom,sde_cesta@0x0af30000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,sde-cesta";
|
||||
reg = <0x0af20000 0x850>,
|
||||
<0xaf30000 0x60>,
|
||||
<0xaf31000 0x30>,
|
||||
<0xaf32000 0x30>,
|
||||
<0xaf33000 0x30>,
|
||||
<0xaf34000 0x30>,
|
||||
<0xaf35000 0x30>,
|
||||
<0xaf36000 0x30>;
|
||||
reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>;
|
||||
|
||||
clock-names = "branch_clk", "core_clk";
|
||||
clock-rate = <575000000 575000000>;
|
||||
clock-max-rate = <575000000 575000000>;
|
||||
clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_0>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_HW_1
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_1>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_HW_2
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_2>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_HW_3
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_3>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_HW_4
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_4>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_HW_5
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_HW_5>,
|
||||
<&mmss_noc MASTER_MDP_DISP_CRM_SW_0
|
||||
&mc_virt SLAVE_EBI1_DISP_CRM_SW_0>;
|
||||
interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1",
|
||||
"qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3",
|
||||
"qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5",
|
||||
"qcom,sde-data-bus-sw-0";
|
||||
|
||||
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
clocks =
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||
|
||||
clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk";
|
||||
clock-rate = <0 0 19200000 575000000>;
|
||||
clock-max-rate = <0 0 19200000 575000000>;
|
||||
|
||||
qcom,hw-fence-sw-version = <0x1>;
|
||||
|
||||
mmcx-supply = <&VDD_MMCX_LEVEL>;
|
||||
|
||||
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_DISPLAY_CB>;
|
||||
|
||||
qcom,sde-soccp-controller = <&soccp_pas>;
|
||||
|
||||
qcom,sde-vm-exclude-reg-names = "ipcc_reg";
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
|
||||
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC
|
||||
&config_noc SLAVE_DISPLAY_CFG>;
|
||||
interconnect-names = "qcom,sde-data-bus0",
|
||||
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
||||
|
||||
qcom,sde-has-idle-pc;
|
||||
|
||||
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
||||
qcom,sde-dspp-ltm-version = <0x00010003>;
|
||||
/* offsets are based off dspp 0, 1, 2, and 3 */
|
||||
qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>;
|
||||
|
||||
nvmem-cells = <&ssip_config>;
|
||||
nvmem-cell-names = "ssip_config";
|
||||
|
||||
qcom,platform-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,platform-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "mmcx";
|
||||
qcom,supply-min-voltage = <0>;
|
||||
qcom,supply-max-voltage = <0>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_ESYNC0_CLK>,
|
||||
<&dispcc_mx DISP_CC_OSC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
|
||||
"esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-1p2-supply = <&L3G>;
|
||||
qcom,split-link-supported;
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_ESYNC1_CLK>,
|
||||
<&dispcc_mx DISP_CC_OSC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk",
|
||||
"esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
vdda-0p9-supply = <&L3I>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-cdp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM";
|
||||
compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <1 0>;
|
||||
};
|
||||
@@ -0,0 +1,185 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-sec-reset-gpio = <&tlmm 97 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_spr {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_vid_spr {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sharp_4k_dsc_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
qcom,platform-bklight-en-gpio = <&tlmm 100 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr>;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se15_i2c {
|
||||
status = "disabled";
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-mtp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM";
|
||||
compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <8 0>, <0x40008 0>;
|
||||
};
|
||||
@@ -0,0 +1,99 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_spr {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_vid_spr {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_sec_hd_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <1>;
|
||||
qcom,mdss-dsi-bl-max-level = <1023>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se4_i2c {
|
||||
st_fts@49 {
|
||||
panel = <&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_dsc_10b_video
|
||||
&dsi_nt37801_amoled_cmd_spr
|
||||
&dsi_nt37801_amoled_vid_spr>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-sun-sde.dtsi"
|
||||
#include "trustedvm-sun-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
|
||||
compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
|
||||
"qcom,qrd";
|
||||
qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
|
||||
qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>;
|
||||
};
|
||||
@@ -0,0 +1,59 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "trustedvm-sun-sde-display.dtsi"
|
||||
|
||||
&dsi_nt37801_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_cmd_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&dsi_nt37801_amoled_video_cphy {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 98 0>;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>;
|
||||
};
|
||||
|
||||
&qupv3_se4_spi {
|
||||
st_fts@0 {
|
||||
panel = <&dsi_nt37801_amoled_cmd_cphy
|
||||
&dsi_nt37801_amoled_video_cphy
|
||||
&dsi_nt37801_amoled_cmd
|
||||
&dsi_nt37801_amoled_video>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sun-sde-display-common.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&sde_dsi1 {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>,
|
||||
<&clock_cpucc 2>,
|
||||
<&clock_cpucc 3>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"pll_byte_clk1", "pll_dsi_clk1";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>;
|
||||
};
|
||||
@@ -0,0 +1,91 @@
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/qcom,dispcc-sun.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sun.h>
|
||||
#include "sun-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
/* dummy display clock provider */
|
||||
clock_cpucc: qcom,cpucc {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "cpucc_clocks";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x804 0x2>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
reg = <0x0ae00000 0x93800>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0af80000 0x7000>,
|
||||
<0x0ae44000 0x02c>;
|
||||
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys",
|
||||
"sid_phys";
|
||||
|
||||
qcom,sde-vm-exclude-reg-names = "sid_phys";
|
||||
|
||||
qcom,tvm-include-reg = <0x0af20000 0x850>,
|
||||
<0xaf30000 0x60>,
|
||||
<0xaf31000 0x30>,
|
||||
<0xaf32000 0x30>,
|
||||
<0xaf33000 0x30>,
|
||||
<0xaf34000 0x30>,
|
||||
<0xaf35000 0x30>,
|
||||
<0xaf36000 0x30>;
|
||||
|
||||
qcom,sde-hw-version =<0xC0000000>;
|
||||
|
||||
clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
|
||||
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||
clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
|
||||
"core_clk", "vsync_clk", "lut_clk";
|
||||
qcom,sde-trusted-vm-env;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi1 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
|
||||
&mdss_dsi_phy1 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
Reference in New Issue
Block a user