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android_kernel_samsung_sm87…/qcom/pineapple.dtsi
Gokul krishna Krishnakumar db32d03865 ARM: dts: qcom: Add crmb/crmc to cesta device for pineapple 
Add crmb and crmc register space for cesta devices on pineapple.

Change-Id: Ia8ec195ca1683e652b31a5daa2ab271e8bcec321
Signed-off-by: Gokul krishna Krishnakumar <quic_gokukris@quicinc.com>
2023-09-20 14:28:36 -07:00

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,camcc-pineapple.h>
#include <dt-bindings/clock/qcom,dispcc-pineapple.h>
#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/clock/qcom,gpucc-pineapple.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,tcsrcc-pineapple.h>
#include <dt-bindings/clock/qcom,videocc-pineapple.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/interconnect/qcom,pineapple.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>
/ {
model = "Qualcomm Technologies, Inc. Pineapple";
compatible = "qcom,pineapple";
qcom,msm-id = <557 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
chosen: chosen {
bootargs = "loglevel=6 kpti=0 log_buf_len=256K swiotlb=noforce kernel.panic_on_rcu_stall=1 fw_devlink.strict=1 service_locator.enable=1 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 irqaffinity=0-1 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc cgroup.memory=nokmem,nosocket printk.console_no_auto_verbose=1 kasan=off service_locator.enable=1 loop.max_part=7 no-steal-acc can.stats_timer=0 ufs_qcom.crash_on_ber=y ftrace_dump_on_oops firmware_class.path=/vendor/firmware_mnt/image,/vendor/firmware_mnt/image/kiwi,/vendor/vm-system/oemvm/boot,/vendor/vm-system/trustedvm/boot,/vendor/firmware,/vendor/firmware/wlan/qca_cld/kiwi_v2 pcie_ports=compat disable_dma32=on pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x2";
stdout-path = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@89c000:115200n8";
};
aliases: aliases {
serial0 = &qupv3_se15_2uart;
hsuart0 = &qupv3_se14_4uart;
sdhc2 = &sdhc_2;
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
};
reserved_memory: reserved-memory { };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
firmware: firmware { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF_CL0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF_CL0>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL1>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 3>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL1>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 3>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_2>;
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL1>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 3>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL2>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL2>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF_CL3>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <588>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
};
core1 {
cpu = <&CPU3>;
};
core2 {
cpu = <&CPU4>;
};
};
cluster2 {
core0 {
cpu = <&CPU5>;
};
core1 {
cpu = <&CPU6>;
};
};
cluster3 {
core0 {
cpu = <&CPU7>;
};
};
};
};
idle-states {
entry-method = "psci";
SILVER_OFF_CL0: silver-cluster0-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <550>;
exit-latency-us = <750>;
min-residency-us = <6700>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
GOLD_OFF_CL1: gold-cluster1-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <550>;
exit-latency-us = <1050>;
min-residency-us = <7951>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
GOLD_OFF_CL2: gold-cluster2-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <550>;
exit-latency-us = <1050>;
min-residency-us = <7951>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
GOLD_OFF_CL3: gold-plus-cluster3-c4 { /* C4 */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <500>;
exit-latency-us = <1350>;
min-residency-us = <7480>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
CLUSTER_PWR_DN: cluster-d4 { /* D4 */
compatible = "domain-idle-state";
idle-state-name = "l3-off";
entry-latency-us = <750>;
exit-latency-us = <2350>;
min-residency-us = <9144>;
arm,psci-suspend-param = <0x41000044>;
};
APSS_OFF: cluster-e3 { /* E3 */
compatible = "domain-idle-state";
idle-state-name = "llcc-off";
entry-latency-us = <2800>;
exit-latency-us = <4400>;
min-residency-us = <10150>;
arm,psci-suspend-param = <0x4100c344>;
};
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
disp_rdump_region {
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD4: cpu-pd4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD5: cpu-pd5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD6: cpu-pd6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD7: cpu-pd7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD: cluster-pd {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
};
};
slimbam: bamdma@6C04000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0x6C04000 0x20000>, <0x6C8F000 0x1000>;
reg-names = "bam", "bam_remote_mem";
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
slim_msm: slim@6C40000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x6C40000 0x2C000>, <0x6C8E000 0x1000>;
reg-names = "ctrl", "slimbus_remote_mem";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x490>;
dmas = <&slimbam 3>, <&slimbam 4>;
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
intc: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
ranges;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x17100000 0x10000>, /* GICD */
<0x17180000 0x200000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
gic_its: msi-controller@17140000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x17140000 0x20000>;
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17420000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17420000 0x1000>;
clock-frequency = <19200000>;
frame@17421000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17421000 0x1000>,
<0x17422000 0x1000>;
};
frame@17423000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17423000 0x1000>;
status = "disabled";
};
frame@17425000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17425000 0x1000>;
status = "disabled";
};
frame@17427000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17427000 0x1000>;
status = "disabled";
};
frame@17429000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17429000 0x1000>;
status = "disabled";
};
frame@1742b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1742b000 0x1000>;
status = "disabled";
};
frame@1742d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x1742d000 0x1000>;
status = "disabled";
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
pcie_crm_hw_0_bcm_voter: bcm_voter@0 {
compatible = "qcom,bcm-voter";
qcom,crm-name = "pcie_crm";
qcom,crm-client-idx = <0>;
qcom,crm-pwr-states = <5>;
};
pcie_crm_hw_1_bcm_voter: bcm_voter@1 {
compatible = "qcom,bcm-voter";
qcom,crm-name = "pcie_crm";
qcom,crm-client-idx = <1>;
qcom,crm-pwr-states = <5>;
};
clk_virt: interconnect@0 {
compatible = "qcom,pineapple-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1";
qcom,bcm-voters = <&apps_bcm_voter>,
<&pcie_crm_hw_0_bcm_voter>,
<&pcie_crm_hw_1_bcm_voter>;
};
mc_virt: interconnect@1 {
compatible = "qcom,pineapple-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos",
"disp",
"cam_ife_0",
"cam_ife_1",
"cam_ife_2",
"pcie_crm_hw_0",
"pcie_crm_hw_1";
qcom,bcm-voters = <&apps_bcm_voter>,
<&disp_bcm_voter>,
<&cam_bcm_voter0>,
<&cam_bcm_voter1>,
<&cam_bcm_voter2>,
<&pcie_crm_hw_0_bcm_voter>,
<&pcie_crm_hw_1_bcm_voter>;
};
config_noc: interconnect@1600000 {
compatible = "qcom,pineapple-cnoc_cfg";
reg = <0x1600000 0x6200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
cnoc_main: interconnect@1500000 {
compatible = "qcom,pineapple-cnoc_main";
reg = <0x1500000 0x14080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,pineapple-system_noc";
reg = <0x1680000 0x1D080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie_noc: interconnect@16c0000 {
compatible = "qcom,pineapple-pcie_anoc";
reg = <0x16c0000 0x12200>;
#interconnect-cells = <1>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
qcom,bcm-voter-names = "hlos", "pcie_crm_hw_0", "pcie_crm_hw_1";
qcom,bcm-voters = <&apps_bcm_voter>,
<&pcie_crm_hw_0_bcm_voter>,
<&pcie_crm_hw_1_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,pineapple-aggre1_noc";
reg = <0x16E0000 0x16400>;
#interconnect-cells = <1>;
clocks =
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,pineapple-aggre2_noc";
reg = <0x1700000 0x1E400>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1780000 {
compatible = "qcom,pineapple-mmss_noc";
reg = <0x1780000 0x5B800>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
qcom,bcm-voters = <&apps_bcm_voter>,
<&disp_bcm_voter>,
<&cam_bcm_voter0>,
<&cam_bcm_voter1>,
<&cam_bcm_voter2>;
};
gem_noc: interconnect@24100000 {
compatible = "qcom,pineapple-gem_noc";
reg = <0x24100000 0xC5080>;
#interconnect-cells = <1>;
clocks = <&gcc GCC_CPUSS_UBWCP_CLK_SRC>;
clock-names = "gcc_ddrss_ubwcp_clk";
qcom,bcm-voter-names = "hlos",
"disp",
"cam_ife_0",
"cam_ife_1",
"cam_ife_2",
"pcie_crm_hw_0",
"pcie_crm_hw_1";
qcom,bcm-voters = <&apps_bcm_voter>,
<&disp_bcm_voter>,
<&cam_bcm_voter0>,
<&cam_bcm_voter1>,
<&cam_bcm_voter2>,
<&pcie_crm_hw_0_bcm_voter>,
<&pcie_crm_hw_1_bcm_voter>;
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,pineapple-nsp_noc";
reg = <0x320C0000 0xF080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@7e40000 {
compatible = "qcom,pineapple-lpass_ag_noc";
reg = <0x7e40000 0xE080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_lpiaon_noc: interconnect@7400000 {
compatible = "qcom,pineapple-lpass_lpiaon_noc";
reg = <0x7400000 0x19080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_lpicx_noc: interconnect@7430000 {
compatible = "qcom,pineapple-lpass_lpicx_noc";
reg = <0x7430000 0x3A200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,pineapple-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>, <126 716 12>,
<138 251 5>, <143 244 4>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
pcie_pdc: pdc@b350000 {
compatible = "qcom,pineapple-pcie-pdc", "qcom,pcie-pdc";
reg = <0xb350000 0x20000>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,pineapple-pinctrl";
reg = <0x0F000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qcom,gpios-reserved = <36 37 38 39>;
};
show_resume_irqs@17100000 {
compatible = "qcom,show-resume-irqs";
reg = <0x17100000 0x290000>;
};
dload_mode {
compatible = "qcom,dload-mode";
};
mini_dump_mode {
compatible = "qcom,minidump";
status = "ok";
};
vendor_hooks: qcom,cpu-vendor-hooks {
compatible = "qcom,cpu-vendor-hooks";
};
logbuf: qcom,logbuf-vendor-hooks {
compatible = "qcom,logbuf-vendor-hooks";
};
apps_rsc: rsc@17a00000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x17a00000 0x10000>,
<0x17a10000 0x10000>,
<0x17a20000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&CLUSTER_PD>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 3>,
<SLEEP_TCS 2>,
<WAKE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 1>;
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,pineapple-rpmh-clk";
#clock-cells = <1>;
};
dcvs_fp: qcom,dcvs-fp {
compatible = "qcom,dcvs-fp";
qcom,ddr-bcm-name = "MC4";
qcom,llcc-bcm-name = "SH5";
};
};
};
cam_rsc: rsc@add9000 {
label = "cam_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xadd4000 0x1000>,
<0xadd5000 0x1000>,
<0xadd6000 0x1000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
qcom,hw-channel;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
cam_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x520>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
channel@1 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
cam_bcm_voter0: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,no-amc;
};
};
cam_rsc_drv1: drv@1 {
qcom,drv-id = <1>;
qcom,tcs-offset = <0x520>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
channel@1 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
cam_bcm_voter1: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,no-amc;
};
};
cam_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0x520>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
channel@1 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<WAKE_TCS 1>,
<SLEEP_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
cam_bcm_voter2: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,no-amc;
};
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
qcom,drv-count = <1>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
disp_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x1c00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
qcom,no-amc;
};
};
};
cam_crm: crm@add7000 {
label = "cam_crm";
compatible = "qcom,cam-crm";
reg = <0xadd7000 0x2000>, <0xadd9800 0x800>, <0xadda000 0x2000>;
reg-names = "base", "crm_b", "crm_c";
interrupts = <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cam_crm";
clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
qcom,hw-drv-ids = <0 1 2>;
qcom,sw-drv-ids = <0>;
};
pcie_crm: crm@1d01000 {
label = "pcie_crm";
compatible = "qcom,pcie-crm";
reg = <0x1d01000 0x3000>, <0x1d04800 0x800>, <0x1d05000 0x2000>;
reg-names = "base", "crm_b", "crm_c";
interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pcie_crm";
clocks = <&pcie_0_pipe_clk>;
qcom,hw-drv-ids = <0 1>;
qcom,sw-drv-ids = <0>;
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qcom,msm-imem@14680000 {
compatible = "qcom,msm-imem";
reg = <0x14680000 0x1000>;
ranges = <0x0 0x14680000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,pil-reloc-info";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
/* PIL spss node - for loading Secure Processor */
spss_pas: remoteproc-spss@1880000 {
compatible = "qcom,pineapple-spss-pas";
ranges;
reg = <0x188101c 0x4>,
<0x1881024 0x4>,
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
interrupts = <0 352 1>;
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
status = "ok";
memory-region = <&spss_region_mem>;
qcom,spss-scsr-bits = <24 25>;
qcom,extra-size = <4096>;
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
glink-edge {
qcom,remote-pid = <8>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "spss_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0x1885008 0x8>,
<0x1885010 0x4>;
reg-names = "qcom,spss-addr",
"qcom,spss-size";
label = "spss";
qcom,glink-label = "spss";
};
};
qcom,spcom {
compatible = "qcom,spcom";
qcom,rproc-handle = <&spss_pas>;
qcom,boot-enabled;
/* predefined channels, remote side is server */
qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
/* sp2soc rmb shared register physical address and bmsk */
qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
/* soc2sp rmb shared register physical address */
qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
status = "ok";
};
spss_utils: qcom,spss_utils {
compatible = "qcom,spss-utils";
/* spss fuses physical address */
qcom,rproc-handle = <&spss_pas>;
qcom,spss-fuse1-addr = <0x221C8214>;
qcom,spss-fuse1-bit = <8>;
qcom,spss-fuse2-addr = <0x221C8214>;
qcom,spss-fuse2-bit = <7>;
qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */
qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */
qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */
qcom,spss-debug-reg-addr = <0x01886020>;
qcom,spss-debug-reg-addr1 = <0x01888020>;
qcom,spss-debug-reg-addr3 = <0x0188C020>;
qcom,spss-emul-type-reg-addr = <0x01fc8004>;
pil-mem = <&spss_region_mem>;
qcom,pil-size = <0x0F0000>; // padding to 960KB
status = "ok";
};
cluster-device {
compatible = "qcom,lpm-cluster-dev";
power-domains = <&CLUSTER_PD>;
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <2>;
label = "modem";
};
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
};
qcom,client_4 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x1000000>;
qcom,client-id = <5>;
qcom,allocate-on-request;
qcom,shared;
memory-region = <&qmc_dma_mem>;
label = "modem";
};
qcom,client_5 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x400000>;
qcom,client-id = <6>;
qcom,allocate-on-request;
qcom,shared;
label = "modem";
};
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie_0_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_phy_aux_clk: pcie_1_phy_aux_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_phy_aux_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie_1_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_0_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_1_clk";
#clock-cells = <0>;
};
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_tx_symbol_0_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
cpuss-sleep-stats@17800054 {
compatible = "qcom,cpuss-sleep-stats";
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
<0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
<0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>,
<0x178c0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
"seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <8>;
};
sram@c3f0000 {
compatible = "qcom,rpmh-stats-v3";
reg = <0x0c3f0000 0x400>;
qcom,qmp = <&aoss_qmp>;
ss-name = "modem", "adsp", "adsp_island",
"cdsp", "apss";
};
camcc_crmc: syscon@adda000 {
compatible = "syscon";
reg = <0xadda000 0x2000>;
};
camcc: clock-controller@ade0000 {
compatible = "qcom,pineapple-camcc", "syscon";
reg = <0xade0000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
"iface";
qcom,cam_crm-crmc = <&camcc_crmc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,pineapple-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo",
"sleep_clk",
"iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
gcc: clock-controller@100000 {
compatible = "qcom,pineapple-gcc", "syscon";
reg = <0x100000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&pcie_0_pipe_clk>,
<&pcie_1_phy_aux_clk>,
<&pcie_1_pipe_clk>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"pcie_0_pipe_clk",
"pcie_1_phy_aux_clk",
"pcie_1_pipe_clk",
"sleep_clk",
"ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,pineapple-gpucc", "syscon";
reg = <0x3d90000 0x9800>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gpll0_out_main",
"gpll0_out_main_div";
#clock-cells = <1>;
#reset-cells = <1>;
};
tcsrcc: clock-controller@1f40000 {
compatible = "qcom,pineapple-tcsrcc", "syscon";
reg = <0x1f40000 0xc0000>;
reg-name = "cc_base";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,pineapple-videocc", "syscon";
reg = <0xaaf0000 0x10000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"sleep_clk",
"iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
apsscc: syscon@17a80000 {
compatible = "syscon";
reg = <0x17a80000 0x21000>;
};
mccc: syscon@240ba000 {
compatible = "syscon";
reg = <0x240ba000 0x54>;
};
debugcc: qcom,cc-debug {
compatible = "qcom,pineapple-debugcc";
qcom,gcc = <&gcc>;
qcom,gpucc = <&gpucc>;
qcom,videocc = <&videocc>;
qcom,dispcc = <&dispcc>;
qcom,camcc = <&camcc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clock-names = "xo_clk_src";
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-epss";
reg = <0x17D91000 0x1000>,
<0x17D92000 0x1000>,
<0x17D93000 0x1000>,
<0x17D94000 0x1000>;
reg-names = "freq-domain0",
"freq-domain1",
"freq-domain2",
"freq-domain3";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int",
"dcvsh1_int",
"dcvsh2_int",
"dcvsh3_int";
#freq-domain-cells = <1>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>,
<&cpufreq_hw 1>,
<&cpufreq_hw 2>,
<&cpufreq_hw 3>;
};
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
opp-peak-kBps = <160000 100000>;
opp-avg-kBps = <80000 50000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
opp-peak-kBps = <200000 120000>;
opp-avg-kBps = <80000 50000>;
};
};
sdhc_2: sdhci@8804000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <4>;
no-sdio;
no-mmc;
qcom,restore-after-cx-collapse;
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>;
clock-names = "iface", "core";
/*
* DLL HSR settings. Refer go/hsr - <Target> DLL settings.
* Note that the DLL_CONFIG_2 value is not passed from the
* device tree, but it is calculated in the driver.
*/
qcom,dll-hsr-list = <0x0007442C 0x0 0x10
0x090106C0 0x80040868>;
iommus = <&apps_smmu 0x540 0x0>;
dma-coherent;
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc
SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
operating-points-v2 = <&sdhc2_opp_table>;
qos0 {
mask = <0xf0>;
vote = <44>;
};
qos1 {
mask = <0x0f>;
vote = <44>;
};
};
ufsphy_mem: ufsphy_mem@1d80000 {
reg = <0x1d80000 0x2000>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_aux_clk", "qref_clk",
"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&tcsrcc TCSR_UFS_CLKREF_EN>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ice_cfg: shared_ice {
alg1 {
alg-name = "alg1";
rx-alloc-percent = <60>;
status = "disabled";
};
alg2 {
alg-name = "alg2";
status = "disabled";
};
alg3 {
alg-name = "alg3";
num-core = <28 28 15 13>;
status = "ok";
};
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x8000>,
<0x1d90000 0x9000>;
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
qcom,prime-mask = <0x80>;
qcom,silver-mask = <0x0f>;
qcom,esi-affinity-mask = <0xf0>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_LN_BB_CLK3>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<100000000 403000000>,
<0 0>,
<0 0>,
<100000000 403000000>,
<100000000 403000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <30>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<14752 0>, <1000 0>, /* PWM G5 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<29504 0>, <1000 0>, /* PWM G5 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<1492582 0>, <102400 0>, /* HS G3 RA */
<2915200 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<1492582 0>, <204800 0>, /* HS G3 RA L2 */
<2915200 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<1492582 0>, <102400 0>, /* HS G3 RB */
<2915200 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
<5836800 0>, <819200 0>, /* HS G5 RA L2*/
<5836800 0>, <819200 0>, /* HS G5 RB L2 */
<7643136 0>, <819200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"HS_RA_G5_L2", "HS_RB_G5_L2",
"MAX";
iommus = <&apps_smmu 0x60 0x0>;
qcom,iommu-dma = "fastmap";
shared-ice-cfg = <&ice_cfg>;
dma-coherent;
qcom,bypass-pbl-rst-wa;
status = "disabled";
qos0 {
mask = <0xfc>;
vote = <44>;
perf;
cpu_freq_vote = <2 5 7>;
};
qos1 {
mask = <0x03>;
vote = <44>;
cpu_freq_vote = <0>;
};
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x400000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
};
thermal_zones: thermal-zones {
};
spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc42d000 0x4000>,
<0xc400000 0x3000>,
<0xc500000 0x400000>,
<0xc440000 0x80000>,
<0xc4c0000 0x10000>;
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,bus-id = <0>;
};
spmi1_bus: qcom,spmi@c432000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc432000 0x4000>,
<0xc400000 0x3000>,
<0xc500000 0x400000>,
<0xc440000 0x80000>,
<0xc4d0000 0x10000>;
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,bus-id = <1>;
depends-on-supply = <&spmi0_bus>;
status = "disabled";
};
spmi0_debug_bus: qcom,spmi-debug@10b14000 {
compatible = "qcom,spmi-pmic-arb-debug";
reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
reg-names = "core", "fuse";
clocks = <&aoss_qmp>;
clock-names = "core_clk";
qcom,fuse-enable-bit = <18>;
#address-cells = <2>;
#size-cells = <0>;
depends-on-supply = <&spmi_bus>;
depends-on2-supply = <&pm8550b_glink_debug>;
qcom,pmk8550-debug@0 {
compatible = "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550-debug@1 {
compatible = "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550vs-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550vs-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550vs-debug@4 {
compatible = "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550vs-debug@6 {
compatible = "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550b-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8550ve-debug@8 {
compatible = "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmr735d-debug@a {
compatible = "qcom,spmi-pmic";
reg = <0xa SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8010-debug@c {
compatible = "qcom,spmi-pmic";
reg = <0xc SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8010-debug@d {
compatible = "qcom,spmi-pmic";
reg = <0xd SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
qcom_tzlog: tz-log@14680720 {
compatible = "qcom,tz-log";
reg = <0x14680720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x28000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,offload-ops-support;
qcom,bam-pipe-offload-cpb-hlos = <1>;
qcom,bam-pipe-offload-hlos-cpb = <3>;
qcom,bam-pipe-offload-hlos-hlos = <4>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0480 0x0>,
<&apps_smmu 0x0481 0x0>;
qcom,iommu-dma = "atomic";
dma-coherent;
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x0481 0x0>;
dma-coherent;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x0483 0x0>;
qcom,iommu-vmid = <0x9>;
qcom,secure-context-bank;
dma-coherent;
};
};
qcom_rng: qrng@10c3000 {
compatible = "qcom,msm-rng";
reg = <0x10c3000 0x1000>;
qcom,no-qrng-config;
qcom,no-clock-support;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
cache-controller@25000000 {
compatible = "qcom,pineapple-llcc", "qcom,llcc-v50";
reg = <0x25000000 0x800000> , <0x25800000 0x200000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
cap-based-alloc-and-pwr-collapse;
llcc-perfmon {
compatible = "qcom,llcc-perfmon";
clocks = <&aoss_qmp QDSS_CLK>;
clock-names = "qdss_clk";
};
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupt-parent = <&pdc>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x088E0000 0x2000>,
<0x088E2000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
qcom,secure-eud-en;
qcom,eud-utmi-delay = /bits/ 16 <255>;
status = "ok";
};
ipcc_mproc: qcom,ipcc@406000 {
compatible = "qcom,ipcc";
reg = <0x406000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,aoss-qmp";
reg = <0xc300000 0x400>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
#power-domain-cells = <1>;
#clock-cells = <0>;
};
qmp_aop: qcom,qmp-aop {
compatible = "qcom,qmp-mbox";
qcom,qmp = <&aoss_qmp>;
label = "aop";
#mbox-cells = <1>;
};
qmp_tme: qcom,qmp-tme {
compatible = "qcom,qmp-mbox";
qcom,remote-pid = <14>;
mboxes = <&ipcc_mproc IPCC_CLIENT_TME
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "tme_qmp";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_TME
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "tme";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
qcom,tmecom-qmp-client {
compatible = "qcom,tmecom-qmp-client";
mboxes = <&qmp_tme 0>;
mbox-names = "tmecom";
label = "tmecom";
depends-on-supply = <&qmp_tme>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
qcom,glinkpkt-qmc-dma {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
qcom,glinkpkt-dev-name = "qmc_dma";
qcom,glinkpkt-enable-ch-close;
};
qcom,glinkpkt-qmc-cma {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
qcom,glinkpkt-dev-name = "qmc_cma";
qcom,glinkpkt-enable-ch-close;
};
};
qcom,glink {
compatible = "qcom,glink";
};
qcom,qsee_ipc_irq_bridge {
compatible = "qcom,qsee-ipc-irq-bridge";
qcom,qsee-ipc-irq-spss {
qcom,dev-name = "qsee_ipc_irq_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_TZ
IRQ_TYPE_EDGE_RISING>;
label = "spss";
};
};
sys-pm-vx@c320000 {
compatible = "qcom,sys-pm-violators", "qcom,sys-pm-pineapple";
reg = <0xc320000 0x0400>;
qcom,qmp = <&aoss_qmp>;
};
adsp_sleepmon: adsp-sleepmon {
compatible = "qcom,adsp-sleepmon";
qcom,rproc-handle = <&adsp_pas>;
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058
0x17840058 0x17850058 0x17860058 0x17870058>;
qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060
0x17840060 0x17850060 0x17860060 0x17870060>;
};
adsp_pas: remoteproc-adsp@03000000 {
compatible = "qcom,pineapple-adsp-pas";
reg = <0x03000000 0x10000>;
status = "ok";
cx-supply = <&VDD_LPI_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
mx-supply = <&VDD_LPI_MX_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
reg-names = "cx", "mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
memory-region = <&adsp_slpi_mem &q6_adsp_dtb_mem>;
/* Inputs from ssc */
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack";
/* Outputs to turing */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink_edge: glink-edge {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,net-id = <2>;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
qcom,no-wake-svc = <0x190>;
};
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3
0x2000 1>;
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
};
};
modem_pas: remoteproc-mss@04080000 {
compatible = "qcom,pineapple-modem-pas";
reg = <0x4080000 0x10000>;
status = "ok";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-supply = <&VDD_MODEM_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM_L1 100000>;
reg-names = "cx", "mx";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma>;
mpss_dsm_mem_reg = <&mpss_dsm_mem>, <&mpss_dsm_mem_2>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack",
"shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
};
};
cdsp_pas: remoteproc-cdsp@32300000 {
compatible = "qcom,pineapple-cdsp-pas";
reg = <0x32300000 0x10000>;
status = "ok";
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
mx-supply = <&VDD_MXC_LEVEL>;
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
nsp-supply = <&VDD_NSP1_LEVEL>;
nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
reg-names = "cx","mx","nsp";
memory-region = <&cdsp_mem &q6_cdsp_dtb_mem>;
global-sync-mem-reg = <&global_sync_mem>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,signal-aop;
qcom,qmp = <&aoss_qmp>;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "rproc_ddr", "crypto_ddr";
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>;
interrupt-names = "wdog",
"fatal",
"handover",
"ready",
"stop-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "cdsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-cores = <0 1>;
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
qcom,msm_fastrpc_rpmsg {
compatible = "qcom,msm-fastrpc-rpmsg";
qcom,glink-channels = "fastrpcglink-apps-dsp";
qcom,intents = <0x64 64>;
};
};
};
spss_pas: remoteproc-spss@1880000 {
compatible = "qcom,pineapple-spss-pas";
ranges;
reg = <0x188101c 0x4>,
<0x1881024 0x4>,
<0x1881028 0x4>,
<0x188103c 0x4>,
<0x1881100 0x4>,
<0x1882014 0x4>;
reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
"rmb_err", "rmb_general_purpose", "rmb_err_spare2";
interrupts = <0 352 1>;
cx-supply = <&VDD_CX_LEVEL>;
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
status = "ok";
memory-region = <&spss_region_mem>;
qcom,spss-scsr-bits = <24 25>;
qcom,extra-size = <4096>;
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
interconnect-names = "crypto_ddr";
glink-edge {
qcom,remote-pid = <8>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "spss_spss";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0x1885008 0x8>,
<0x1885010 0x4>;
reg-names = "qcom,spss-addr",
"qcom,spss-size";
label = "spss";
qcom,glink-label = "spss";
};
};
gic-interrupt-router {
compatible = "qcom,gic-intr-routing";
/* keep silver core only to avoid wakeup of gold cores */
qcom,gic-class0-cpus = <0 1>;
/* keep gold and gold+ cores in class1 */
qcom,gic-class1-cpus = <2 3 4 5 6 7>;
};
qcom,secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
qcom,vmid = <3>;
};
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
};
qti,smmu-proxy {
compatible = "smmu-proxy-sender";
};
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
qcom,master;
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0 &tlmm 49 0
&tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0 &tlmm 91 0
&tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0 &tlmm 88 0>;
};
tlmm-vm-test {
compatible = "qcom,tlmm-vm-test";
qcom,master;
tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 48 0 &tlmm 49 0
&tlmm 50 0 &tlmm 51 0 &tlmm 161 0 &tlmm 162 0 &tlmm 91 0
&tlmm 60 0 &tlmm 61 0 &tlmm 62 0 &tlmm 63 0 &tlmm 88 0>;
};
cpusys-vm-shmem-access {
compatible = "qcom,cpusys-vm-shmem-access";
gunyah-label = <5>;
peer-name = <3>;
shared-buffer = <&hwfence_shbuf>;
};
trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring {
size = <0x4000>;
gunyah-label = <0x11>;
};
trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring {
size = <0x4000>;
gunyah-label = <0x10>;
};
trust_ui_vm_swiotlb: trust_ui_vm_swiotlb {
size = <0x100000>;
gunyah-label = <0x12>;
};
trust_ui_vm: qcom,trust_ui_vm {
vm_name = "trustedvm";
shared-buffers-size = <0x108000>;
shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_vblk1_ring &trust_ui_vm_swiotlb>;
};
oem_vm_vblk0_ring: oem_vm_vblk0_ring {
size = <0x4000>;
gunyah-label = <0x13>;
};
oem_vm_swiotlb: oem_vm_swiotlb {
size = <0x100000>;
gunyah-label = <0x14>;
};
oem_vm: qcom,oem_vm {
vm_name = "oemvm";
shared-buffers-size = <0x104000>;
shared-buffers = <&oem_vm_vblk0_ring &oem_vm_swiotlb>;
};
trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 {
qcom,vm = <&trust_ui_vm>;
qcom,label = <0x11>;
};
trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 {
qcom,vm = <&trust_ui_vm>;
qcom,label = <0x10>;
};
gh-rm-booster {
compatible = "qcom,gh-rm-booster";
qcom,rm-vmid = <255>;
qcom,rm-affinity-default = <0>;
};
gh-secure-vm-loader@0 {
compatible = "qcom,gh-secure-vm-loader";
qcom,pas-id = <28>;
qcom,vmid = <45>;
qcom,firmware-name = "trustedvm";
memory-region = <&trust_ui_vm_mem &vm_comm_mem>;
virtio-backends = <&trust_ui_vm_virt_be0 &trust_ui_vm_virt_be1>;
};
oem_vm_virt_be0: oem_vm_virt_be0@13 {
qcom,vm = <&oem_vm>;
qcom,label = <0x13>;
};
gh-secure-vm-loader@1 {
compatible = "qcom,gh-secure-vm-loader";
qcom,pas-id = <34>;
qcom,vmid = <49>;
qcom,firmware-name = "oemvm";
memory-region = <&oem_vm_mem &vm_comm_mem>;
virtio-backends = <&oem_vm_virt_be0>;
};
gh-secure-vm-loader@2 {
compatible = "qcom,gh-secure-vm-loader";
qcom,pas-id = <35>;
qcom,vmid = <50>;
qcom,firmware-name = "cpusys_vm";
memory-region = <&cpusys_vm_mem>;
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
qcom,rproc-handle = <&cdsp_pas>;
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem_heap>;
restrict-access;
};
qcom,test-dbl {
compatible = "qcom,gh-dbl";
qcom,label = <0x4>;
};
qcom,pmic_glink {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
qcom,subsys-name = "lpass";
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
depends-on-supply = <&ipcc_mproc>;
battery_charger: qcom,battery_charger {
compatible = "qcom,battery-charger";
};
ucsi: qcom,ucsi {
compatible = "qcom,ucsi-glink";
};
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
#altmode-cells = <1>;
};
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
qcom,charger_ulog_glink {
compatible = "qcom,charger-ulog-glink";
};
pmic_glink_debug: qcom,pmic_glink_debug {
compatible = "qcom,pmic-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
depends-on-supply = <&spmi1_bus>;
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
pm8550b_glink_debug: qcom,pm8550b-debug@7 {
compatible = "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
qcom,can-sleep;
};
};
};
pmic_glink_adc: qcom,glink-adc {
compatible = "qcom,glink-adc";
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
status = "disabled";
};
};
qcom,test-msgq {
compatible = "qcom,gh-msgq-test";
gunyah-label = <4>;
qcom,primary;
};
qcom,gh-qtimer@17425000 {
compatible = "qcom,gh-qtmr";
reg = <0x17425000 0x1000>;
reg-names = "qtmr-base";
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "qcom,qtmr-intr";
qcom,primary;
};
msm_gpu: qcom,kgsl-3d0@3d00000 { };
mmio_sram: mmio-sram@17D09400 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mmio-sram";
reg = <0x0 0x17D09400 0x0 0x400>;
ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;
cpu_scp_lpri: scmi-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x17D09400 0x0 0x400>;
};
};
cpucp: qcom,cpucp@17400000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,cpucp";
reg = <0x17400000 0x10>,
<0x17d90000 0x2000>;
#mbox-cells = <1>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
scmi: qcom,scmi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,scmi";
mboxes = <&cpucp 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
scmi_memlat: protocol@80 {
reg = <0x80>;
#clock-cells = <1>;
};
scmi_plh: protocol@81 {
reg = <0x81>;
#clock-cells = <1>;
};
scmi_pmu: protocol@86 {
reg = <0x86>;
#clock-cells = <1>;
};
scmi_c1dcvs: protocol@87 {
reg = <0x87>;
#clock-cells = <1>;
};
};
cpucp_log: qcom,cpucp_log@d8140000 {
compatible = "qcom,cpucp-log";
reg = <0xd8040000 0x10000>, <0xd8050000 0x10000>;
mboxes = <&cpucp 1>;
};
qcom_c1dcvs: qcom,c1dcvs {
compatible = "qcom,c1dcvs-v2";
};
qcom_mpam: qcom,mpam {
compatible = "qcom,mpam";
};
qcom_cpufreq_stats: qcom,cpufreq_stats {
compatible = "qcom,cpufreq-stats-v2";
};
llcc_pmu: llcc-pmu@24095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x24095000 0x300>;
reg-names = "lagg-base";
};
qcom_pmu: qcom,pmu {
compatible = "qcom,pmu";
qcom,long-counter;
reg = <0x17d09880 0x380>;
reg-names = "pmu-base";
qcom,pmu-events-tbl =
< 0x0008 0xFF 0x02 0x02 >,
< 0x0011 0xFF 0x01 0x00 >,
< 0x0017 0xFF 0xFF 0x04 >,
< 0x0037 0xFF 0xFF 0x06 >,
< 0x1000 0xFF 0xFF 0x08 >;
};
ddr_freq_table: ddr-freq-table {
qcom,freq-tbl =
< 547000 >,
< 768000 >,
< 1555000 >,
< 1708000 >,
< 2092000 >,
< 2736000 >,
< 3187000 >,
< 3686000 >,
< 4224000 >;
};
llcc_freq_table: llcc-freq-table {
qcom,freq-tbl =
< 300000 >,
< 466000 >,
< 600000 >,
< 806000 >,
< 933000 >,
< 1066000 >;
};
ddrqos_freq_table: ddrqos-freq-table {
qcom,freq-tbl =
< 0 >,
< 1 >;
};
qcom_dcvs: qcom,dcvs {
compatible = "qcom,dcvs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom_l3_dcvs_hw: l3 {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <2>;
qcom,bus-width = <32>;
reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
reg-names = "l3-base", "l3tbl-base";
l3_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
qcom,shared-offset = <0x0090>;
};
};
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
ddr_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_llcc_dcvs_hw: llcc {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <1>;
qcom,bus-width = <16>;
qcom,freq-tbl = <&llcc_freq_table>;
llcc_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&gem_noc MASTER_APPSS_PROC
&gem_noc SLAVE_LLCC>;
};
llcc_dcvs_fp: fp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <1>;
qcom,fp-voter = <&dcvs_fp>;
};
};
qcom_ddrqos_dcvs_hw: ddrqos {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <3>;
qcom,bus-width = <1>;
qcom,freq-tbl = <&ddrqos_freq_table>;
ddrqos_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&mc_virt MASTER_LLCC
&mc_virt SLAVE_EBI1>;
};
};
qcom_ubwcp_dcvs_hw: ubwcp {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <4>;
qcom,bus-width = <4>;
qcom,freq-tbl = <&ddr_freq_table>;
ubwcp_dcvs_sp: sp {
compatible = "qcom,dcvs-path";
qcom,dcvs-path-type = <0>;
interconnects = <&gem_noc MASTER_UBWC_P
&mc_virt SLAVE_EBI1>;
};
};
};
qcom_memlat: qcom,memlat {
compatible = "qcom,memlat";
ddr {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
qcom,sampling-path = <&ddr_dcvs_fp>;
qcom,miss-ev = <0x1000>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 1132800 547000 >,
< 1536000 768000 >,
< 2131200 1555000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
qcom,cpufreq-memfreq-tbl =
< 576000 547000 >,
< 902400 768000 >,
< 1152000 1555000 >,
< 1382400 2092000 >,
< 1958400 2736000 >,
< 2515200 3686000 >,
< 3187200 4224000 >;
qcom,sampling-enabled;
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 576000 547000 >,
< 902400 768000 >,
< 1152000 1555000 >,
< 1382400 2092000 >,
< 1958400 2736000 >,
< 2515200 3686000 >,
< 3187200 4224000 >;
qcom,sampling-enabled;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 547000 >,
< 3187200 2092000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2515200 547000 >,
< 3187200 4224000 >;
qcom,sampling-enabled;
};
};
llcc {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
qcom,sampling-path = <&llcc_dcvs_fp>;
qcom,miss-ev = <0x37>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 902400 300000 >,
< 1536000 466000 >,
< 2131200 600000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 576000 300000 >,
< 1152000 466000 >,
< 1382400 600000 >,
< 1958400 806000 >,
< 2515200 933000 >,
< 3187200 1066000 >;
qcom,sampling-enabled;
};
gold-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 300000 >,
< 3187200 600000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
};
l3 {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_l3_dcvs_hw>;
qcom,sampling-path = <&l3_dcvs_sp>;
qcom,miss-ev = <0x17>;
silver {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU0 &CPU1>;
qcom,cpufreq-memfreq-tbl =
< 307200 307200 >,
< 460800 384000 >,
< 556800 595200 >,
< 787200 710400 >,
< 902400 806400 >,
< 1017600 921600 >,
< 1132800 1017600 >,
< 1344000 1132800 >,
< 1536000 1363200 >,
< 1651200 1459200 >,
< 1747200 1555200 >,
< 1939200 1651200 >,
< 2131200 1728000 >;
qcom,sampling-enabled;
};
gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6>;
qcom,cpufreq-memfreq-tbl =
< 460800 307200 >,
< 576000 595200 >,
< 902400 806400 >,
< 1152000 1017600 >,
< 1382400 1132800 >,
< 1843200 1363200 >,
< 2073600 1459200 >,
< 2515200 1555200 >,
< 3187200 1728000 >;
qcom,sampling-enabled;
};
prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 460800 307200 >,
< 576000 595200 >,
< 902400 806400 >,
< 1152000 1017600 >,
< 1382400 1132800 >,
< 1843200 1363200 >,
< 2073600 1459200 >,
< 2515200 1555200 >,
< 3187200 1728000 >;
qcom,sampling-enabled;
};
prime-compute {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 307200 >,
< 3187200 1728000 >;
qcom,sampling-enabled;
qcom,compute-mon;
};
};
ddrqos {
compatible = "qcom,memlat-grp";
qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
qcom,sampling-path = <&ddrqos_dcvs_sp>;
qcom,miss-ev = <0x1000>;
ddrqos_gold_lat: gold {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpufreq-memfreq-tbl =
< 1958400 0 >,
< 3187200 1 >;
qcom,sampling-enabled;
};
ddrqos_prime_lat: prime {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 1382400 0 >,
< 3187200 1 >;
qcom,sampling-enabled;
};
ddrqos_prime_latfloor: prime-latfloor {
compatible = "qcom,memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,cpufreq-memfreq-tbl =
< 2073600 0 >,
< 3187200 1 >;
qcom,sampling-enabled;
};
};
};
bwmon_llcc: qcom,bwmon-llcc@240B7300 {
compatible = "qcom,bwmon4";
reg = <0x240B7400 0x300>, <0x240B7300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
};
bwmon_ddr: qcom,bwmon-ddr@24091000 {
compatible = "qcom,bwmon5";
reg = <0x24091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
bwmon_ubwcp: qcom,bwmon-ubwcp@240B5200 {
compatible = "qcom,bwmon4";
reg = <0x240B5300 0x300>, <0x240B5200 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,count-unit = <0x10000>;
qcom,target-dev = <&qcom_ubwcp_dcvs_hw>;
};
google,debug-kinfo {
compatible = "google,debug-kinfo";
memory-region = <&kinfo_mem>;
};
dmesg-dump {
compatible = "qcom,dmesg-dump";
qcom,primary-vm;
gunyah-label = <7>;
peer-name = <2>;
memory-region = <&vm_comm_mem>;
shared-buffer-size = <0x1000>;
};
qcom,qrtr-mhi-cnss {
compatible = "qcom,qrtr-mhi";
qcom,dev-id = <0x1107>;
qcom,net-id = <0>;
qcom,low-latency;
};
qcom,qrtr-gunyah-tuivm {
compatible = "qcom,qrtr-gunyah";
qcom,master;
gunyah-label = <3>;
peer-name = <2>;
};
qcom,qrtr-gunyah-oemvm {
compatible = "qcom,qrtr-gunyah";
qcom,master;
gunyah-label = <8>;
peer-name = <4>;
};
qcom,health_monitor {
compatible = "qcom,system-health-monitor";
qcom,modem {
qcom,subsys-name = "msm_mpss";
qcom,ssrestart-string = "mpss";
qcom,rproc_phandle = <&modem_pas>;
};
};
qcom,gunyah-panic-notifier {
compatible = "qcom,gh-panic-notifier";
qcom,primary-vm;
gunyah-label = <9>;
peer-name = <2>;
memory-region = <&vm_comm_mem>;
shared-buffer-size = <0x1000>;
};
qfprom: qfprom@221c2000 {
compatible = "qcom,qfprom";
reg = <0x221c2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
gpu_speed_bin: gpu_speed_bin@9b {
reg = <0x9b 0x1>;
bits = <4 3>;
};
};
};
&firmware {
qcom_scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x19000>;
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
gunyah_hyp_mem: gunyah_hyp_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0xe00000>;
};
cpusys_vm_mem: cpusys_vm_region@80e00000 {
no-map;
reg = <0x0 0x80e00000 0x0 0x400000>;
};
/*
* hyp_tags_mem is dynamically removed from the RAM
* partition tables before boot occurs. Size of region
* varies.
*/
/* hyp_reserved_mem doesn't correspond to an actual region. */
/* merged xbl_dtlog, xbl_ramdump and aop_image regions */
xbl_aop_merged_mem: xbl_aop_merged_region@81a00000 {
no-map;
reg = <0x0 0x81a00000 0x0 0x260000>;
};
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x81c60000 0x0 0x20000>;
};
/* merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
aop_tme_uefi_merged_mem: aop_tme_uefi_merged_region@81c80000 {
no-map;
reg = <0x0 0x81c80000 0x0 0x74000>;
};
chipinfo_mem: chipinfo_region@81cf4000 {
no-map;
reg = <0x0 0x81cf4000 0x0 0x1000>;
};
/* secdata region can be reused by apps */
smem_mem: smem_region@81d00000 {
compatible = "qcom,smem";
reg = <0x0 0x81d00000 0x0 0x200000>;
hwlocks = <&tcsr_mutex 3>;
no-map;
};
adsp_mhi_mem: adsp_mhi_region@81f00000 {
no-map;
reg = <0x0 0x81f00000 0x0 0x20000>;
};
pvmfw_mem: pvmfw_region@0x824a0000 {
no-map;
reg = <0x0 0x824a0000 0x0 0x100000>;
};
/* hyp_mem_database_mem is removed by HYP in the RAM partition table */
global_sync_mem: global_sync_region@82600000 {
no-map;
reg = <0x0 0x82600000 0x0 0x100000>;
};
tz_stat_mem: tz_stat_region@82700000 {
no-map;
reg = <0x0 0x82700000 0x0 0x100000>;
};
qdss_mem: qdss_region@82800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x82800000 0x0 0x2000000>;
reusable;
};
mpss_dsm_mem: mpss_dsm_region@86b00000 {
no-map;
reg = <0x0 0x86b00000 0x0 0x4900000>;
};
mpss_dsm_mem_2: mpss_dsm_region_2@8b400000 {
no-map;
reg = <0x0 0x8b400000 0x0 0x800000>;
};
mpss_mem: mpss_region@8bc00000 {
no-map;
reg = <0x0 0x8bc00000 0x0 0xf400000>;
};
q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
no-map;
reg = <0x0 0x9b000000 0x0 0x80000>;
};
ipa_fw_mem: ipa_fw_region@9b080000 {
no-map;
reg = <0x0 0x9b080000 0x0 0x10000>;
};
ipa_gsi_mem: ipa_gsi_region@9b090000 {
no-map;
reg = <0x0 0x9b090000 0x0 0xa000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qmc_dma_mem: qmc_dma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
size = <0x0 0xa400000>;
alignment = <0x0 0x400000>;
};
gpu_micro_code_mem: gpu_microcode_region@9b09a000 {
no-map;
reg = <0x0 0x9b09a000 0x0 0x2000>;
};
spss_region_mem: spss_region_region@9b0a0000 {
no-map;
reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
};
/* First part of the "SPU secure shared memory" region */
spu_tz_shared_mem: spu_secure_shared_memory_region@9b280000 {
no-map;
reg = <0x0 0x9b280000 0x0 0x60000>;
};
/* Second part of the "SPU secure shared memory" region */
spu_modem_shared_mem: spu_secure_shared_memory_region@9b2e0000 {
no-map;
reg = <0x0 0x9b2e0000 0x0 0x20000>;
};
camera_mem: camera_region@9b300000 {
no-map;
reg = <0x0 0x9b300000 0x0 0x800000>;
};
video_mem: video_region@9bb00000 {
no-map;
reg = <0x0 0x9bb00000 0x0 0x800000>;
};
cvp_mem: cvp_region@9c300000 {
no-map;
reg = <0x0 0x9c300000 0x0 0x700000>;
};
cdsp_mem: cdsp_region@9ca00000 {
no-map;
reg = <0x0 0x9ca00000 0x0 0x1400000>;
};
q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9de00000 {
no-map;
reg = <0x0 0x9de00000 0x0 0x80000>;
};
q6_adsp_dtb_mem: q6_adsp_dtb_region@9de80000 {
no-map;
reg = <0x0 0x9de80000 0x0 0x80000>;
};
adsp_slpi_mem: adspslpi_region@9df00000 {
no-map;
reg = <0x0 0x9df00000 0x0 0x4080000>;
};
/* uefi region can be reused by apps */
/* Linux kernel image is loaded at 0xa8000000 */
/* merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */
tz_merged_mem: tz_merged_region@d8000000 {
no-map;
reg = <0x0 0xd8000000 0x0 0x800000>;
};
/*
* ta/tags mem is dynamically removed from the RAM
* partition tables before boot occurs. Size of region
* varies.
*/
hwfence_shbuf: hwfence-shmem {
no-map;
reg = <0x0 0xe6440000 0x0 0x2dd000>;
};
vm_comm_mem: vm_comm_mem_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf3800000 0x0 0x4400000>;
reusable;
alignment = <0x0 0x400000>;
};
oem_vm_mem: oem_vm_region@f7c00000 {
compatible = "shared-dma-pool";
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
reusable;
alignment = <0x0 0x400000>;
};
llcc_lpi_mem: llcc_lpi_region@ff800000 {
no-map;
reg = <0x0 0xff800000 0x0 0x600000>;
};
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
cdsp_eva_mem: cdsp_eva_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
adsp_mem_heap: adsp_heap_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
system_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x4800000>;
};
kinfo_mem: debug_kinfo_region {
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x1000>;
no-map;
};
ramoops_mem: ramoops_region {
compatible = "ramoops";
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
size = <0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
};
#include "ipcc-test.dtsi"
#include "pineapple-gdsc.dtsi"
#include "pineapple-pinctrl.dtsi"
#include "pineapple-regulators.dtsi"
#include "msm-arm-smmu-pineapple.dtsi"
#include "pineapple-debug.dtsi"
#include "pineapple-dma-heaps.dtsi"
#include "pineapple-qupv3.dtsi"
#include "pineapple-usb.dtsi"
#include "pineapple-coresight.dtsi"
#include "pineapple-pcie.dtsi"
#include "msm-rdbg.dtsi"
#include "pineapple-thermal.dtsi"
&qupv3_se15_2uart {
status = "ok";
};
&qupv3_se3_i2c {
status = "ok";
wcd_usbss: wcd939x_i2c@e {
compatible = "qcom,wcd939x-i2c";
reg = <0xe>;
vdd-usb-cp-supply = <&L15B>;
};
};
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_ife_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_ife_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_ife_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_sbi_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_sfe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_sfe_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_sfe_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&cam_cc_titan_top_gdsc>;
status = "ok";
};
&cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
interconnect-names = "mmnoc";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
&disp_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&disp_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&apss_ubwcp_pwr_ctrl {
status = "ok";
};
&gcc_pcie_0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_0_phy_gdsc {
parent-supply = <&VDD_MXA_LEVEL>;
status = "ok";
};
&gcc_pcie_1_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_1_phy_gdsc {
parent-supply = <&VDD_MXA_LEVEL>;
status = "ok";
};
&gcc_ufs_mem_phy_gdsc {
parent-supply = <&VDD_MXA_LEVEL>;
status = "ok";
};
&gcc_ufs_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb30_prim_gdsc {
status = "ok";
};
&gcc_usb3_phy_gdsc {
parent-supply = <&VDD_MXA_LEVEL>;
status = "ok";
};
&gpu_cc_cx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_cc_gx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
status = "ok";
};
&video_cc_mvs0_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
&video_cc_mvs0c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
&video_cc_mvs1_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
&video_cc_mvs1c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
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