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android_kernel_samsung_sm87…/qcom/parrot-qupv3.dtsi
Swetha Chikkaboraiah 9a7dea76dd ARM: dts: msm: Update qup_iommu_region 
Update node qup_iommu_region for parrot and ravelin.

Change-Id: I488e3eb0a1577b7e1aafbdfd91efd6e12fdfd55b
Signed-off-by: Swetha Chikkaboraiah <quic_schikk@quicinc.com>
(cherry picked from commit f5dc7ce0a9)
2024-11-26 01:58:44 -08:00

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
&soc {
/* QUPv3 SE Instances
* Qup0 0: SE 0
* Qup0 1: SE 1
* Qup0 2: SE 2
* Qup0 3: SE 3
* Qup0 4: SE 4
* Qup0 5: SE 5
* Qup1 0: SE 6
* Qup1 1: SE 7
* Qup1 2: SE 8
* Qup1 3: SE 9
* Qup1 4: SE 10
* Qup1 5: SE 11
*/
qup_iommu_region0: qup_iommu_region {
iommu-addresses = <&gpi_dma0 0x0 0x100000>, <&gpi_dma0 0x200000 0xffe00000>,
<&qupv3_0 0x0 0x40000000>, <&qupv3_0 0x50000000 0xb0000000>;
};
/* GPI Instance */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x176 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x3f>;
qcom,ev-factor = <2>;
memory-region = <&qup_iommu_region0>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_0 wrapper instance */
qupv3_0: qcom,qupv3_0_geni_se@9C0000 {
compatible = "qcom,geni-se-qup";
reg = <0x9C0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
iommus = <&apps_smmu 0x163 0x0>;
memory-region = <&qup_iommu_region0>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
/* Debug UART Instance */
qupv3_se3_2uart: qcom,qup_uart@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0x98c000 0x4000>;
reg-names = "se_phys";
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
pinctrl-1 = <&qupv3_se3_2uart_sleep>;
status = "disabled";
};
qupv3_se0_i2c: i2c@980000 {
compatible = "qcom,i2c-geni";
reg = <0x980000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma0 0 0 3 64 0>,
<&gpi_dma0 1 0 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se0_spi: spi@980000 {
compatible = "qcom,spi-geni";
reg = <0x980000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma0 0 0 1 64 0>,
<&gpi_dma0 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se1_i2c: i2c@984000 {
compatible = "qcom,i2c-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
dmas = <&gpi_dma0 0 1 3 64 0>,
<&gpi_dma0 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se1_spi: spi@984000 {
compatible = "qcom,spi-geni";
reg = <0x984000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
pinctrl-1 = <&qupv3_se1_spi_sleep>;
dmas = <&gpi_dma0 0 1 1 64 0>,
<&gpi_dma0 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se2_i2c: i2c@988000 {
compatible = "qcom,i2c-geni";
reg = <0x988000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
dmas = <&gpi_dma0 0 2 3 64 0>,
<&gpi_dma0 1 2 3 64 0>;
dma-names = "tx", "rx";
qcom,shared;
status = "disabled";
};
qupv3_se2_spi: spi@988000 {
compatible = "qcom,spi-geni";
reg = <0x988000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
pinctrl-1 = <&qupv3_se2_spi_sleep>;
dmas = <&gpi_dma0 0 2 1 64 0>,
<&gpi_dma0 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se4_i2c: i2c@990000 {
compatible = "qcom,i2c-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
dmas = <&gpi_dma0 0 4 3 64 0>,
<&gpi_dma0 1 4 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se4_spi: spi@990000 {
compatible = "qcom,spi-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
pinctrl-1 = <&qupv3_se4_spi_sleep>;
dmas = <&gpi_dma0 0 4 1 64 0>,
<&gpi_dma0 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se5_i2c: i2c@994000 {
compatible = "qcom,i2c-geni";
reg = <0x994000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
dmas = <&gpi_dma0 0 5 3 64 0>,
<&gpi_dma0 1 5 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se5_spi: spi@994000 {
compatible = "qcom,spi-geni";
reg = <0x994000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_0>,
<&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
pinctrl-1 = <&qupv3_se5_spi_sleep>;
dmas = <&gpi_dma0 0 5 1 64 0>,
<&gpi_dma0 1 5 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
};
qup_iommu_region1: qup_iommu_region {
iommu-addresses = <&gpi_dma1 0x0 0x100000>, <&gpi_dma1 0x200000 0xffe00000>,
<&qupv3_1 0x0 0x40000000>, <&qupv3_1 0x50000000 0xb0000000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0xa00000 0x60000>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x416 0x0>;
qcom,max-num-gpii = <12>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x3e>;
qcom,ev-factor = <2>;
memory-region = <&qup_iommu_region1>;
dma-coherent;
qcom,gpi-ee-offset = <0x10000>;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x403 0x0>;
memory-region = <&qup_iommu_region1>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
dma-coherent;
ranges;
status = "ok";
qupv3_se6_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 0>,
<&gpi_dma1 1 0 3 64 0>;
dma-names = "tx", "rx";
};
qupv3_se6_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
<&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
pinctrl-1 = <&qupv3_se6_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 0>,
<&gpi_dma1 1 0 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se7_i2c: i2c@a84000 {
compatible = "qcom,i2c-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_i2c_sda_active>, <&qupv3_se7_i2c_scl_active>;
pinctrl-1 = <&qupv3_se7_i2c_sleep>;
dmas = <&gpi_dma1 0 1 3 64 0>,
<&gpi_dma1 1 1 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se7_spi: spi@a84000 {
compatible = "qcom,spi-geni";
reg = <0xa84000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se7_spi_mosi_active>, <&qupv3_se7_spi_miso_active>,
<&qupv3_se7_spi_clk_active>, <&qupv3_se7_spi_cs_active>;
pinctrl-1 = <&qupv3_se7_spi_sleep>;
dmas = <&gpi_dma1 0 1 1 64 0>,
<&gpi_dma1 1 1 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se8_i2c: i2c@a88000 {
compatible = "qcom,i2c-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma1 0 2 3 64 0>,
<&gpi_dma1 1 2 3 64 0>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se8_spi: spi@a88000 {
compatible = "qcom,spi-geni";
reg = <0xa88000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma1 0 2 1 64 0>,
<&gpi_dma1 1 2 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
qupv3_se9_i2c: i2c@a8c000 {
compatible = "qcom,i2c-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
pinctrl-1 = <&qupv3_se9_i2c_sleep>;
dmas = <&gpi_dma1 0 3 3 64 2>,
<&gpi_dma1 1 3 3 64 2>;
dma-names = "tx", "rx";
status = "disabled";
};
qupv3_se9_spi: spi@a8c000 {
compatible = "qcom,spi-geni";
reg = <0xa8c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
<&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
pinctrl-1 = <&qupv3_se9_spi_sleep>;
dmas = <&gpi_dma1 0 3 1 64 2>,
<&gpi_dma1 1 3 1 64 2>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
status = "disabled";
};
/* HS UART Instance */
qupv3_se11_4uart: qcom,qup_uart@a94000 {
compatible = "qcom,msm-geni-serial-hs";
reg = <0xa94000 0x4000>;
reg-names = "se_phys";
interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 17 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se-clk";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
interconnects =
<&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_QUP_1>,
<&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
pinctrl-names = "default", "active", "sleep", "shutdown";
pinctrl-0 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>,
<&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>;
pinctrl-1 = <&qupv3_se11_cts>, <&qupv3_se11_rts>,
<&qupv3_se11_tx>, <&qupv3_se11_rx>;
pinctrl-2 = <&qupv3_se11_cts>, <&qupv3_se11_rts>,
<&qupv3_se11_tx>, <&qupv3_se11_default_rx>;
pinctrl-3 = <&qupv3_se11_default_cts>, <&qupv3_se11_default_rts>,
<&qupv3_se11_default_tx>, <&qupv3_se11_default_rx>;
qcom,wakeup-byte = <0xFD>;
qcom,suspend-ignore-children;
status = "disabled";
};
};
};
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