25940 lines
676 KiB
Plaintext
25940 lines
676 KiB
Plaintext
/dts-v1/;
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/ {
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model = "Qualcomm Technologies, Inc. Sun SoC";
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compatible = "qcom,sun";
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qcom,msm-id = <0x26a 0x10000>;
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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qcom,board-id = <0x00 0x00>;
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memory {
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device_type = "memory";
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reg = <0x00 0x00 0x00 0x00>;
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};
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chosen {
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bootargs = "log_buf_len=512K loglevel=6 cpufreq.default_governor=performance sysctl.kernel.sched_pelt_multiplier=4 no-steal-acc kpti=0 swiotlb=0 loop.max_part=7 irqaffinity=0-1 pcie_ports=compat printk.console_no_auto_verbose=1 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kernel.panic_on_rcu_stall=1 disable_dma32=on cgroup_disable=pressure fw_devlink.strict=1 can.stats_timer=0 pci-msm-drv.pcie_sm_regs=0x1D07000,0x1040,0x1048,0x3000,0x1 ftrace_dump_on_oops memblock_memsize=procfs fault_around_bytes=32768 kswapd_cpumask=0x3f raise_min_free_kbytes=false restrict_cma_redirect cma_restrict_timeout=30";
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stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000:115200n8";
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phandle = <0x353>;
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};
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aliases {
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swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr";
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swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
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swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master";
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swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
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swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
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serial0 = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000";
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hsuart0 = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000";
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ufshc1 = "/soc/ufshc@1d84000";
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mmc1 = "/soc/sdhci@8804000";
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phandle = <0x354>;
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};
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firmware {
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phandle = <0x355>;
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qcom_scm {
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compatible = "qcom,scm";
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qcom,dload-mode = <0x02 0x19000>;
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phandle = <0xf8>;
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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qcom_mem_object {
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compatible = "qcom,mem-object";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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};
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cpus {
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#address-cells = <0x02>;
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#size-cells = <0x00>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x00>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x04>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x10>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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phandle = <0x05>;
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};
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x100>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x07>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x11>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x200>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x08>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x12>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x300>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x09>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x13>;
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};
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cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x400>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x0a>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x14>;
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};
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cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x500>;
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enable-method = "psci";
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cpu-idle-states = <0x03>;
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power-domains = <0x0b>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x700>;
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dynamic-power-coefficient = <0xee>;
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next-level-cache = <0x05>;
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clocks = <0x06 0x00>;
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phandle = <0x15>;
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};
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cpu@10000 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x10000>;
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enable-method = "psci";
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cpu-idle-states = <0x0c>;
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power-domains = <0x0d>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x766>;
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dynamic-power-coefficient = <0x24c>;
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next-level-cache = <0x0e>;
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clocks = <0x06 0x01>;
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phandle = <0x16>;
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l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <0x02>;
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phandle = <0x0e>;
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};
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};
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cpu@10100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x00 0x10100>;
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enable-method = "psci";
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cpu-idle-states = <0x0c>;
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power-domains = <0x0f>;
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power-domain-names = "psci";
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#cooling-cells = <0x02>;
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capacity-dmips-mhz = <0x766>;
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dynamic-power-coefficient = <0x24c>;
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next-level-cache = <0x0e>;
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clocks = <0x06 0x01>;
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phandle = <0x17>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x10>;
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};
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core1 {
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cpu = <0x11>;
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};
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core2 {
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cpu = <0x12>;
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};
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core3 {
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cpu = <0x13>;
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};
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core4 {
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cpu = <0x14>;
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};
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core5 {
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cpu = <0x15>;
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};
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};
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cluster1 {
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core0 {
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cpu = <0x16>;
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};
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core1 {
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cpu = <0x17>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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medium-cluster0-c4 {
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compatible = "arm,idle-state";
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idle-state-name = "ret";
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entry-latency-us = <0x5d>;
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exit-latency-us = <0x81>;
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min-residency-us = <0x230>;
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arm,psci-suspend-param = <0x04>;
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phandle = <0x03>;
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};
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large-cluster1-c4 {
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compatible = "arm,idle-state";
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idle-state-name = "ret";
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entry-latency-us = <0xac>;
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exit-latency-us = <0x82>;
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min-residency-us = <0x2ae>;
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arm,psci-suspend-param = <0x04>;
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phandle = <0x0c>;
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};
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medium-cluster-cl5 {
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compatible = "domain-idle-state";
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idle-state-name = "ret-pll-off";
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entry-latency-us = <0x866>;
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exit-latency-us = <0x7bf>;
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min-residency-us = <0x23b8>;
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arm,psci-suspend-param = <0x1000054>;
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phandle = <0x1d>;
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};
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large-cluster-cl5 {
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compatible = "domain-idle-state";
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idle-state-name = "ret-pll-off";
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entry-latency-us = <0x866>;
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exit-latency-us = <0x7bf>;
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min-residency-us = <0x23b8>;
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arm,psci-suspend-param = <0x1000054>;
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phandle = <0x1e>;
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};
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cluster-ss3 {
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compatible = "domain-idle-state";
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idle-state-name = "apps-pc";
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entry-latency-us = <0xaf0>;
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exit-latency-us = <0x1130>;
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min-residency-us = <0x27a6>;
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arm,psci-suspend-param = <0x200c354>;
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phandle = <0x1f>;
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};
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};
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};
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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ranges;
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phandle = <0x356>;
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gunyah_hyp_region@80000000 {
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no-map;
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reg = <0x00 0x80000000 0x00 0x1200000>;
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phandle = <0x357>;
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};
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cpucp_pdp_region@81200000 {
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no-map;
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reg = <0x00 0x81200000 0x00 0x200000>;
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phandle = <0x358>;
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};
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xbl_dtlog_region@81a00000 {
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no-map;
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reg = <0x00 0x81a00000 0x00 0x40000>;
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phandle = <0x359>;
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};
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aop_image_region@81c00000 {
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no-map;
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reg = <0x00 0x81c00000 0x00 0x60000>;
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phandle = <0x35a>;
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};
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aop_cmd_db_region@81c60000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x00 0x81c60000 0x00 0x20000>;
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phandle = <0x35b>;
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};
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sp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
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reusable;
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alignment = <0x00 0x400000>;
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size = <0x00 0x1000000>;
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phandle = <0xfc>;
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};
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qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
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reusable;
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alignment = <0x00 0x400000>;
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size = <0x00 0x1400000>;
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phandle = <0xfa>;
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};
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qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
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reusable;
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alignment = <0x00 0x400000>;
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size = <0x00 0x1400000>;
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phandle = <0xfb>;
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};
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aop_tme_uefi_merged_region@81c80000 {
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no-map;
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reg = <0x00 0x81c80000 0x00 0x74000>;
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phandle = <0x35c>;
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};
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smem_region@81d00000 {
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compatible = "qcom,smem";
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reg = <0x00 0x81d00000 0x00 0x200000>;
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hwlocks = <0x18 0x03>;
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no-map;
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phandle = <0x35d>;
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};
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pdp_ns_shared_region@81f00000 {
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no-map;
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reg = <0x00 0x81f00000 0x00 0x100000>;
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phandle = <0x35e>;
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};
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cpucp_scandump_region@82000000 {
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no-map;
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reg = <0x00 0x82000000 0x00 0x380000>;
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phandle = <0x35f>;
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};
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adsp_mhi_region@82380000 {
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no-map;
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reg = <0x00 0x82380000 0x00 0x20000>;
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phandle = <0x360>;
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};
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soccp_sdi_region@823a0000 {
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no-map;
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reg = <0x00 0x823a0000 0x00 0x40000>;
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phandle = <0x361>;
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};
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pmic_minii_dump_region@823e0000 {
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no-map;
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reg = <0x00 0x823e0000 0x00 0x80000>;
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phandle = <0x362>;
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};
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pvm_fw_region@824a0000 {
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no-map;
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reg = <0x00 0x824a0000 0x00 0x100000>;
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phandle = <0x363>;
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};
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global_sync_region@82600000 {
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no-map;
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reg = <0x00 0x82600000 0x00 0x100000>;
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phandle = <0x95>;
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};
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tz_stat_region@82700000 {
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no-map;
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reg = <0x00 0x82700000 0x00 0x100000>;
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phandle = <0x364>;
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};
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qdss_apps_region@82800000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0x82800000 0x00 0x2000000>;
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reusable;
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phandle = <0x257>;
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};
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dsm_partition_1_region@84a00000 {
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no-map;
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reg = <0x00 0x84a00000 0x00 0x4900000>;
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phandle = <0x8e>;
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};
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dsm_partition_2_region@89300000 {
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no-map;
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reg = <0x00 0x89300000 0x00 0xa80000>;
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phandle = <0x8f>;
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};
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mpss_region@8ba00000 {
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no-map;
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reg = <0x00 0x8ba00000 0x00 0xf600000>;
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phandle = <0x8b>;
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};
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q6_mpss_dtb_region@9b000000 {
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no-map;
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reg = <0x00 0x9b000000 0x00 0x80000>;
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phandle = <0x8c>;
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};
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ipa_fw_region@9b080000 {
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no-map;
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reg = <0x00 0x9b080000 0x00 0x10000>;
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phandle = <0x365>;
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};
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ipa_gsi_region@9b090000 {
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no-map;
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reg = <0x00 0x9b090000 0x00 0xa000>;
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phandle = <0x366>;
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};
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gpu_microcode_region@9b09a000 {
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no-map;
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reg = <0x00 0x9b09a000 0x00 0x2000>;
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phandle = <0x367>;
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};
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lost_reg_mem {
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no-map;
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reg = <0x00 0x9b09c000 0x00 0x4000>;
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};
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spss_region_region@9b0a0000 {
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no-map;
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reg = <0x00 0x9b0a0000 0x00 0x1e0000>;
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phandle = <0x43>;
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};
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spu_secure_shared_memory_region@9b280000 {
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no-map;
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reg = <0x00 0x9b280000 0x00 0x40000>;
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phandle = <0xfd>;
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};
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spu_secure_shared_memory_region@9b2c0000 {
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no-map;
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reg = <0x00 0x9b2c0000 0x00 0x40000>;
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phandle = <0xfe>;
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};
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camera_region@9b300000 {
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no-map;
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reg = <0x00 0x9b300000 0x00 0x800000>;
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phandle = <0x368>;
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};
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camera_2_region@9bb00000 {
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no-map;
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reg = <0x00 0x9bb00000 0x00 0x800000>;
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phandle = <0x369>;
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};
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video_region@9c300000 {
|
|
no-map;
|
|
reg = <0x00 0x9c300000 0x00 0x800000>;
|
|
phandle = <0x36a>;
|
|
};
|
|
|
|
cvp_region@9cb00000 {
|
|
no-map;
|
|
reg = <0x00 0x9cb00000 0x00 0x700000>;
|
|
phandle = <0x36b>;
|
|
};
|
|
|
|
cdsp_region@9d200000 {
|
|
no-map;
|
|
reg = <0x00 0x9d200000 0x00 0x1900000>;
|
|
phandle = <0x93>;
|
|
};
|
|
|
|
q6_cdsp_dtb_region@9eb00000 {
|
|
no-map;
|
|
reg = <0x00 0x9eb00000 0x00 0x80000>;
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
lost_reg_mem2 {
|
|
no-map;
|
|
reg = <0x00 0x9eb80000 0x00 0x80000>;
|
|
};
|
|
|
|
soccp_region@9ec00000 {
|
|
no-map;
|
|
reg = <0x00 0x9ec00000 0x00 0x180000>;
|
|
phandle = <0xf5>;
|
|
};
|
|
|
|
q6_adsp_dtb_region@9ed80000 {
|
|
no-map;
|
|
reg = <0x00 0x9ed80000 0x00 0x80000>;
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
adspslpi_region@9ee00000 {
|
|
no-map;
|
|
reg = <0x00 0x9ee00000 0x00 0x3a80000>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
xbl_ramdump_region@b8000000 {
|
|
no-map;
|
|
reg = <0x00 0xb8000000 0x00 0x1c0000>;
|
|
phandle = <0x36c>;
|
|
};
|
|
|
|
reg_dump_region@D7000000 {
|
|
no-map;
|
|
reg = <0x00 0xd7000000 0x00 0x2000>;
|
|
phandle = <0x36d>;
|
|
};
|
|
|
|
hwfence-shmem {
|
|
no-map;
|
|
reg = <0x00 0xd4e23000 0x00 0x2dd000>;
|
|
phandle = <0x36e>;
|
|
};
|
|
|
|
tz_merged_region@d8000000 {
|
|
no-map;
|
|
reg = <0x00 0xd8000000 0x00 0x600000>;
|
|
phandle = <0x36f>;
|
|
};
|
|
|
|
trust_ui_vm_dump@0xf37ff000 {
|
|
no-map;
|
|
reg = <0x00 0xf37ff000 0x00 0x1000>;
|
|
phandle = <0xe4>;
|
|
};
|
|
|
|
trust_ui_vm_region@f3800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x00 0xf3800000 0x00 0x4400000>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
late_activate;
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
vm_comm_mem_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x800000>;
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
llcc_lpi_region@ff800000 {
|
|
no-map;
|
|
reg = <0x00 0xff800000 0x00 0x800000>;
|
|
phandle = <0x370>;
|
|
};
|
|
|
|
linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x2400000>;
|
|
linux,cma-default;
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
cdsp_eva_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x400000>;
|
|
late_activate;
|
|
phandle = <0x371>;
|
|
};
|
|
|
|
adsp_heap_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0xc00000>;
|
|
late_activate;
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
non_secure_display_region {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
size = <0x00 0xc800000>;
|
|
alignment = <0x00 0x400000>;
|
|
phandle = <0xf9>;
|
|
};
|
|
|
|
debug_kinfo_region {
|
|
alloc-ranges = <0x00 0x00 0xffffffff 0xffffffff>;
|
|
size = <0x00 0x1000>;
|
|
no-map;
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
va_md_mem_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
ramoops-region {
|
|
alloc-ranges = <0x01 0x00 0xfffffffe 0xffffffff>;
|
|
size = <0x00 0x200000>;
|
|
no-map;
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
qmc_dma_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x1000000>;
|
|
phandle = <0x41>;
|
|
};
|
|
|
|
secure_cdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x00 0x400000>;
|
|
size = <0x00 0x4800000>;
|
|
phandle = <0xff>;
|
|
};
|
|
|
|
dump_mem_region {
|
|
alloc-ranges = <0x01 0x00 0xfffffffe 0xffffffff>;
|
|
size = <0x00 0x5a00000>;
|
|
phandle = <0x268>;
|
|
};
|
|
};
|
|
|
|
mem-offline {
|
|
compatible = "qcom,mem-offline";
|
|
status = "disabled";
|
|
offline-sizes = <0x02 0xc0000000 0x01 0x00>;
|
|
granule = <0x200>;
|
|
qcom,qmp = <0x19>;
|
|
};
|
|
|
|
soc {
|
|
interrupt-parent = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges = <0x00 0x00 0x00 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
phandle = <0x372>;
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
cpu-pd0 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
cpu-pd1 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x07>;
|
|
};
|
|
|
|
cpu-pd2 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x08>;
|
|
};
|
|
|
|
cpu-pd3 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x09>;
|
|
};
|
|
|
|
cpu-pd4 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x0a>;
|
|
};
|
|
|
|
cpu-pd5 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1a>;
|
|
phandle = <0x0b>;
|
|
};
|
|
|
|
cpu-pd6 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1b>;
|
|
phandle = <0x0d>;
|
|
};
|
|
|
|
cpu-pd7 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1b>;
|
|
phandle = <0x0f>;
|
|
};
|
|
|
|
cluster-pd0 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1c>;
|
|
domain-idle-states = <0x1d>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
cluster-pd1 {
|
|
#power-domain-cells = <0x00>;
|
|
power-domains = <0x1c>;
|
|
domain-idle-states = <0x1e>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
cluster-pd2 {
|
|
#power-domain-cells = <0x00>;
|
|
domain-idle-states = <0x1f>;
|
|
phandle = <0x1c>;
|
|
};
|
|
};
|
|
|
|
qcom,ipcc@406000 {
|
|
compatible = "qcom,ipcc";
|
|
reg = <0x406000 0x1000>;
|
|
interrupts = <0x00 0xe5 0x04>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
#mbox-cells = <0x02>;
|
|
phandle = <0x21>;
|
|
};
|
|
|
|
syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <0x20 0x00 0x1000>;
|
|
#hwlock-cells = <0x01>;
|
|
phandle = <0x18>;
|
|
};
|
|
|
|
interrupt-controller@b220000 {
|
|
compatible = "qcom,sun-pdc\0qcom,pdc";
|
|
reg = <0xb220000 0x10000 0x164400f0 0x64>;
|
|
qcom,pdc-ranges = <0x00 0x2e9 0x33 0x33 0x20f 0x2f 0x62 0x261 0x20 0x82 0x2cd 0x0c 0x8e 0xfb 0x05 0x93 0x31c 0x10>;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupt-controller;
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
pdc@b360000 {
|
|
compatible = "qcom,sun-pcie-pdc\0qcom,pcie-pdc";
|
|
reg = <0xb360000 0x10000>;
|
|
phandle = <0x373>;
|
|
};
|
|
|
|
power-controller@c300000 {
|
|
compatible = "qcom,aoss-qmp";
|
|
reg = <0xc300000 0x400>;
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x00 0x00 0x01>;
|
|
mboxes = <0x21 0x00 0x00>;
|
|
#power-domain-cells = <0x01>;
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
qcom,qmp-tme {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,remote-pid = <0x0e>;
|
|
mboxes = <0x21 0x17 0x00>;
|
|
mbox-names = "tme_qmp";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x17 0x00 0x01>;
|
|
label = "tme";
|
|
qcom,early-boot;
|
|
priority = <0x00>;
|
|
mbox-desc-offset = <0x00>;
|
|
#mbox-cells = <0x01>;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
qcom,tmecom-qmp-client {
|
|
compatible = "qcom,tmecom-qmp-client";
|
|
mboxes = <0x22 0x00>;
|
|
mbox-names = "tmecom";
|
|
label = "tmecom";
|
|
depends-on-supply = <0x22>;
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1bb 0x1ad>;
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x03 0x02 0x01>;
|
|
mboxes = <0x21 0x03 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x02>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x23>;
|
|
};
|
|
|
|
qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x34f>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x350>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x5e 0x1b0>;
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x06 0x02 0x01>;
|
|
mboxes = <0x21 0x06 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x05>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x351>;
|
|
};
|
|
|
|
qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x352>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x1b3 0x1ac>;
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x02 0x02 0x01>;
|
|
mboxes = <0x21 0x02 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x01>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x374>;
|
|
};
|
|
|
|
qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x375>;
|
|
};
|
|
|
|
qcom,smp2p-smem-mailbox-1-out {
|
|
qcom,entry-name = "smem-mailbox";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0x376>;
|
|
};
|
|
|
|
qcom,smp2p-smem-mailbox-1-in {
|
|
qcom,entry-name = "smem-mailbox";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x377>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-soccp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <0x269 0x268>;
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x2e 0x02 0x01>;
|
|
mboxes = <0x21 0x2e 0x02>;
|
|
qcom,local-pid = <0x00>;
|
|
qcom,remote-pid = <0x13>;
|
|
|
|
master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <0x01>;
|
|
phandle = <0xf7>;
|
|
};
|
|
|
|
slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xf6>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <0x23 0x00>;
|
|
interrupt-parent = <0x24>;
|
|
interrupts = <0x00 0x00>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-ctrl-cdsp {
|
|
qcom,glinkpkt-edge = "cdsp";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_CDSP";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_cdsp";
|
|
};
|
|
|
|
qcom,glinkpkt-data-cdsp {
|
|
qcom,glinkpkt-edge = "cdsp";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_CDSP";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_data_cdsp";
|
|
};
|
|
|
|
qcom,glinkpkt-ctrl-lpass {
|
|
qcom,glinkpkt-edge = "lpass";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_LPASS";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_lpass";
|
|
};
|
|
|
|
qcom,glinkpkt-data-lpass {
|
|
qcom,glinkpkt-edge = "lpass";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_LPASS";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_data_lpass";
|
|
};
|
|
|
|
qcom,glinkpkt-ctrl-mpss {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_CTL_MPSS";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_ctrl_mpss";
|
|
};
|
|
|
|
qcom,glinkpkt-data-mpss {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "LOOPBACK_DATA_MPSS";
|
|
qcom,glinkpkt-dev-name = "glink_pkt_data_mpss";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
qcom,glinkpkt-qmc-dma {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
|
|
qcom,glinkpkt-dev-name = "qmc_dma";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-qmc-cma {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
|
|
qcom,glinkpkt-dev-name = "qmc_cma";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-ims-sub-1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "Ims_dc_sub1";
|
|
qcom,glinkpkt-dev-name = "ims_dc_sub1";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-ims-sub-2 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "Ims_dc_sub2";
|
|
qcom,glinkpkt-dev-name = "ims_dc_sub2";
|
|
qcom,glinkpkt-enable-ch-close;
|
|
};
|
|
|
|
qcom,glinkpkt-xpan_control {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "bt_cp_ctrl";
|
|
qcom,glinkpkt-dev-name = "bt_cp_ctrl";
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
};
|
|
|
|
qcom,qsee_ipc_irq_bridge {
|
|
compatible = "qcom,qsee-ipc-irq-bridge";
|
|
|
|
qcom,qsee-ipc-irq-spss {
|
|
qcom,dev-name = "qsee_ipc_irq_spss";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x10 0x01 0x01>;
|
|
label = "spss";
|
|
};
|
|
};
|
|
|
|
tz-log@14680720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x14680720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
tmecrashdump-address-offset = <0x81ca0000>;
|
|
phandle = <0x378>;
|
|
};
|
|
|
|
sys-pm-vx@c320000 {
|
|
compatible = "qcom,sys-pm-violators\0qcom,sys-pm-sun";
|
|
reg = <0xc320000 0x400>;
|
|
qcom,qmp = <0x19>;
|
|
};
|
|
|
|
pinctrl@f000000 {
|
|
compatible = "qcom,sun-tlmm";
|
|
reg = <0xf000000 0x202000>;
|
|
interrupts = <0x00 0xd0 0x04>;
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
wakeup-parent = <0x25>;
|
|
qcom,gpios-reserved = <0x24 0x25 0x26 0x27 0x4a>;
|
|
phandle = <0x26>;
|
|
|
|
qupv3_se7_2uart_pins {
|
|
phandle = <0x379>;
|
|
|
|
qupv3_se7_2uart_tx_active {
|
|
phandle = <0x2b9>;
|
|
|
|
mux {
|
|
pins = "gpio62";
|
|
function = "qup1_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio62";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_2uart_rx_active {
|
|
phandle = <0x2ba>;
|
|
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "qup1_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio63";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_2uart_sleep {
|
|
phandle = <0x2bb>;
|
|
|
|
mux {
|
|
pins = "gpio62\0gpio63";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio62\0gpio63";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_sck {
|
|
|
|
i2s0_sck_sleep {
|
|
phandle = <0x37a>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sck_active {
|
|
phandle = <0x37b>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "i2s0_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_ws {
|
|
|
|
i2s0_ws_sleep {
|
|
phandle = <0x37c>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_ws_active {
|
|
phandle = <0x37d>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "i2s0_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
trigout_a {
|
|
phandle = <0x267>;
|
|
|
|
mux {
|
|
pins = "gpio73";
|
|
function = "qdss_cti";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio78";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
i2s0_sd0 {
|
|
|
|
i2s0_sd0_sleep {
|
|
phandle = <0x37e>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sd0_active {
|
|
phandle = <0x37f>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "i2s0_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s0_sd1 {
|
|
|
|
i2s0_sd1_sleep {
|
|
phandle = <0x380>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s0_sd1_active {
|
|
phandle = <0x381>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "i2s0_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sck {
|
|
|
|
i2s1_sck_sleep {
|
|
phandle = <0x382>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sck_active {
|
|
phandle = <0x383>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "i2s1_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_ws {
|
|
|
|
i2s1_ws_sleep {
|
|
phandle = <0x384>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_ws_active {
|
|
phandle = <0x385>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "i2s1_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sd0 {
|
|
|
|
i2s1_sd0_sleep {
|
|
phandle = <0x386>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sd0_active {
|
|
phandle = <0x387>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "i2s1_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
i2s1_sd1 {
|
|
|
|
i2s1_sd1_sleep {
|
|
phandle = <0x388>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
i2s1_sd1_active {
|
|
phandle = <0x389>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "i2s1_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_clk {
|
|
|
|
tdm0_clk_sleep {
|
|
phandle = <0x38a>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_clk_active {
|
|
phandle = <0x38b>;
|
|
|
|
mux {
|
|
pins = "gpio126";
|
|
function = "i2s0_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio126";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_ws {
|
|
|
|
tdm0_ws_sleep {
|
|
phandle = <0x38c>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_ws_active {
|
|
phandle = <0x38d>;
|
|
|
|
mux {
|
|
pins = "gpio129";
|
|
function = "i2s0_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio129";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_sd0 {
|
|
|
|
tdm0_sd0_sleep {
|
|
phandle = <0x38e>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_sd0_active {
|
|
phandle = <0x38f>;
|
|
|
|
mux {
|
|
pins = "gpio127";
|
|
function = "i2s0_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio127";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm0_sd1 {
|
|
|
|
tdm0_sd1_sleep {
|
|
phandle = <0x390>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm0_sd1_active {
|
|
phandle = <0x391>;
|
|
|
|
mux {
|
|
pins = "gpio128";
|
|
function = "i2s0_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio128";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_clk {
|
|
|
|
tdm1_clk_sleep {
|
|
phandle = <0x392>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_clk_active {
|
|
phandle = <0x393>;
|
|
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "i2s1_sck";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_ws {
|
|
|
|
tdm1_ws_sleep {
|
|
phandle = <0x394>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_ws_active {
|
|
phandle = <0x395>;
|
|
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "i2s1_ws";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_sd0 {
|
|
|
|
tdm1_sd0_sleep {
|
|
phandle = <0x396>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_sd0_active {
|
|
phandle = <0x397>;
|
|
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "i2s1_data0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
tdm1_sd1 {
|
|
|
|
tdm1_sd1_sleep {
|
|
phandle = <0x398>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
tdm1_sd1_active {
|
|
phandle = <0x399>;
|
|
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "i2s1_data1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <0x08>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie0 {
|
|
|
|
pcie0_perst_default {
|
|
phandle = <0x34a>;
|
|
|
|
mux {
|
|
pins = "gpio102";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio102";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_default {
|
|
phandle = <0x34b>;
|
|
|
|
mux {
|
|
pins = "gpio103";
|
|
function = "pcie0_clk_req_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio103";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_default {
|
|
phandle = <0x34c>;
|
|
|
|
mux {
|
|
pins = "gpio104";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio104";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_sleep {
|
|
phandle = <0x34d>;
|
|
|
|
mux {
|
|
pins = "gpio103";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio103";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
sdc2_on {
|
|
phandle = <0x39a>;
|
|
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x10>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x0a>;
|
|
};
|
|
|
|
sd-cd {
|
|
pins = "gpio55";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
sdc2_off {
|
|
phandle = <0x39b>;
|
|
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
|
|
sd-cd {
|
|
pins = "gpio55";
|
|
bias-pull-up;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
wcd939x_reset_active {
|
|
phandle = <0x39c>;
|
|
|
|
mux {
|
|
pins = "gpio101";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101";
|
|
drive-strength = <0x10>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
wcd939x_reset_sleep {
|
|
phandle = <0x39d>;
|
|
|
|
mux {
|
|
pins = "gpio101";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio101";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-low;
|
|
};
|
|
};
|
|
|
|
spkr_02_sd_n {
|
|
|
|
spkr_02_sd_n_sleep {
|
|
phandle = <0x39e>;
|
|
|
|
mux {
|
|
pins = "gpio76";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_02_sd_n_active {
|
|
phandle = <0x39f>;
|
|
|
|
mux {
|
|
pins = "gpio76";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
spkr_13_sd_n {
|
|
|
|
spkr_13_sd_n_sleep {
|
|
phandle = <0x3a0>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
spkr_13_sd_n_active {
|
|
phandle = <0x3a1>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x10>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se14_4uart_pins {
|
|
phandle = <0x3a2>;
|
|
|
|
qupv3_se14_default_cts {
|
|
phandle = <0x30d>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_rts {
|
|
phandle = <0x30e>;
|
|
|
|
mux {
|
|
pins = "gpio25";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio25";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_tx {
|
|
phandle = <0x30f>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_default_rx {
|
|
phandle = <0x310>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_cts {
|
|
phandle = <0x311>;
|
|
|
|
mux {
|
|
pins = "gpio24";
|
|
function = "qup2_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio24";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_rts {
|
|
phandle = <0x312>;
|
|
|
|
mux {
|
|
pins = "gpio25";
|
|
function = "qup2_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio25";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_tx {
|
|
phandle = <0x313>;
|
|
|
|
mux {
|
|
pins = "gpio26";
|
|
function = "qup2_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio26";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_rx_active {
|
|
phandle = <0x314>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "qup2_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se14_rx_wake {
|
|
phandle = <0x315>;
|
|
|
|
mux {
|
|
pins = "gpio27";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio27";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_pins {
|
|
phandle = <0x3a3>;
|
|
|
|
qupv3_se0_i2c_sda_active {
|
|
phandle = <0x271>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "qup1_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_scl_active {
|
|
phandle = <0x272>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "qup1_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_sleep {
|
|
phandle = <0x273>;
|
|
|
|
mux {
|
|
pins = "gpio32\0gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32\0gpio33";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_pins {
|
|
phandle = <0x3a4>;
|
|
|
|
qupv3_se0_i3c_sda_active {
|
|
phandle = <0x279>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_scl_active {
|
|
phandle = <0x27a>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_sda_sleep {
|
|
phandle = <0x27b>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_scl_sleep {
|
|
phandle = <0x27c>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i3c_disable {
|
|
phandle = <0x27d>;
|
|
|
|
mux {
|
|
pins = "gpio32\0gpio33";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32\0gpio33";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_pins {
|
|
phandle = <0x3a5>;
|
|
|
|
qupv3_se0_spi_miso_active {
|
|
phandle = <0x275>;
|
|
|
|
mux {
|
|
pins = "gpio32";
|
|
function = "qup1_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_mosi_active {
|
|
phandle = <0x274>;
|
|
|
|
mux {
|
|
pins = "gpio33";
|
|
function = "qup1_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio33";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_clk_active {
|
|
phandle = <0x276>;
|
|
|
|
mux {
|
|
pins = "gpio34";
|
|
function = "qup1_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio34";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_cs_active {
|
|
phandle = <0x277>;
|
|
|
|
mux {
|
|
pins = "gpio35";
|
|
function = "qup1_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio35";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_sleep {
|
|
phandle = <0x278>;
|
|
|
|
mux {
|
|
pins = "gpio32\0gpio33\0gpio34\0gpio35";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio32\0gpio33\0gpio34\0gpio35";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_pins {
|
|
phandle = <0x3a6>;
|
|
|
|
qupv3_se1_i2c_sda_active {
|
|
phandle = <0x27e>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "qup1_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_scl_active {
|
|
phandle = <0x27f>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "qup1_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i2c_sleep {
|
|
phandle = <0x280>;
|
|
|
|
mux {
|
|
pins = "gpio36\0gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36\0gpio37";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_pins {
|
|
phandle = <0x3a7>;
|
|
|
|
qupv3_se1_spi_miso_active {
|
|
phandle = <0x282>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "qup1_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_mosi_active {
|
|
phandle = <0x281>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "qup1_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_clk_active {
|
|
phandle = <0x283>;
|
|
|
|
mux {
|
|
pins = "gpio38";
|
|
function = "qup1_se1_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio38";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_cs_active {
|
|
phandle = <0x284>;
|
|
|
|
mux {
|
|
pins = "gpio39";
|
|
function = "qup1_se1_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio39";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_spi_sleep {
|
|
phandle = <0x285>;
|
|
|
|
mux {
|
|
pins = "gpio36\0gpio37\0gpio38\0gpio39";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36\0gpio37\0gpio38\0gpio39";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i3c_pins {
|
|
phandle = <0x3a8>;
|
|
|
|
qupv3_se1_i3c_sda_active {
|
|
phandle = <0x286>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i3c_scl_active {
|
|
phandle = <0x287>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i3c_sda_sleep {
|
|
phandle = <0x288>;
|
|
|
|
mux {
|
|
pins = "gpio36";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i3c_scl_sleep {
|
|
phandle = <0x289>;
|
|
|
|
mux {
|
|
pins = "gpio37";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio37";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_i3c_disable {
|
|
phandle = <0x28a>;
|
|
|
|
mux {
|
|
pins = "gpio36\0gpio37";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio36\0gpio37";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_pins {
|
|
phandle = <0x3a9>;
|
|
|
|
qupv3_se2_i2c_sda_active {
|
|
phandle = <0x28b>;
|
|
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_scl_active {
|
|
phandle = <0x28c>;
|
|
|
|
mux {
|
|
pins = "gpio41";
|
|
function = "qup1_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio41";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_sleep {
|
|
phandle = <0x28d>;
|
|
|
|
mux {
|
|
pins = "gpio40\0gpio41";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40\0gpio41";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_pins {
|
|
phandle = <0x3aa>;
|
|
|
|
qupv3_se2_spi_miso_active {
|
|
phandle = <0x28f>;
|
|
|
|
mux {
|
|
pins = "gpio40";
|
|
function = "qup1_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_mosi_active {
|
|
phandle = <0x28e>;
|
|
|
|
mux {
|
|
pins = "gpio41";
|
|
function = "qup1_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio41";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_clk_active {
|
|
phandle = <0x290>;
|
|
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "qup1_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_cs_active {
|
|
phandle = <0x291>;
|
|
|
|
mux {
|
|
pins = "gpio43";
|
|
function = "qup1_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_sleep {
|
|
phandle = <0x292>;
|
|
|
|
mux {
|
|
pins = "gpio40\0gpio41\0gpio42\0gpio43";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio40\0gpio41\0gpio42\0gpio43";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_pins {
|
|
phandle = <0x3ab>;
|
|
|
|
qupv3_se3_i2c_sda_active {
|
|
phandle = <0x293>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "qup1_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_scl_active {
|
|
phandle = <0x294>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "qup1_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_sleep {
|
|
phandle = <0x295>;
|
|
|
|
mux {
|
|
pins = "gpio44\0gpio45";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44\0gpio45";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_pins {
|
|
phandle = <0x3ac>;
|
|
|
|
qupv3_se3_spi_miso_active {
|
|
phandle = <0x298>;
|
|
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "qup1_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_mosi_active {
|
|
phandle = <0x297>;
|
|
|
|
mux {
|
|
pins = "gpio45";
|
|
function = "qup1_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio45";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_clk_active {
|
|
phandle = <0x299>;
|
|
|
|
mux {
|
|
pins = "gpio46";
|
|
function = "qup1_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio46";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_cs_active {
|
|
phandle = <0x29a>;
|
|
|
|
mux {
|
|
pins = "gpio47";
|
|
function = "qup1_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio47";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_sleep {
|
|
phandle = <0x29b>;
|
|
|
|
mux {
|
|
pins = "gpio44\0gpio45\0gpio46\0gpio47";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44\0gpio45\0gpio46\0gpio47";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_pins {
|
|
phandle = <0x3ad>;
|
|
|
|
qupv3_se4_i2c_sda_active {
|
|
phandle = <0x29c>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "qup1_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_scl_active {
|
|
phandle = <0x29d>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "qup1_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i2c_sleep {
|
|
phandle = <0x29e>;
|
|
|
|
mux {
|
|
pins = "gpio48\0gpio49";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48\0gpio49";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_pins {
|
|
phandle = <0x3ae>;
|
|
|
|
qupv3_se4_i3c_sda_active {
|
|
phandle = <0x2a4>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_scl_active {
|
|
phandle = <0x2a5>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_sda_sleep {
|
|
phandle = <0x2a6>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_scl_sleep {
|
|
phandle = <0x2a7>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_i3c_disable {
|
|
phandle = <0x2a8>;
|
|
|
|
mux {
|
|
pins = "gpio48\0gpio49";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48\0gpio49";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_pins {
|
|
phandle = <0x3af>;
|
|
|
|
qupv3_se4_spi_miso_active {
|
|
phandle = <0x2a0>;
|
|
|
|
mux {
|
|
pins = "gpio48";
|
|
function = "qup1_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_mosi_active {
|
|
phandle = <0x29f>;
|
|
|
|
mux {
|
|
pins = "gpio49";
|
|
function = "qup1_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio49";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_clk_active {
|
|
phandle = <0x2a1>;
|
|
|
|
mux {
|
|
pins = "gpio50";
|
|
function = "qup1_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio50";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_cs_active {
|
|
phandle = <0x2a2>;
|
|
|
|
mux {
|
|
pins = "gpio51";
|
|
function = "qup1_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio51";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_spi_sleep {
|
|
phandle = <0x2a3>;
|
|
|
|
mux {
|
|
pins = "gpio48\0gpio49\0gpio50\0gpio51";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio48\0gpio49\0gpio50\0gpio51";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_pins {
|
|
phandle = <0x3b0>;
|
|
|
|
qupv3_se5_i2c_sda_active {
|
|
phandle = <0x2a9>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup1_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_scl_active {
|
|
phandle = <0x2aa>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup1_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_sleep {
|
|
phandle = <0x2ab>;
|
|
|
|
mux {
|
|
pins = "gpio52\0gpio53";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52\0gpio53";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_pins {
|
|
phandle = <0x3b1>;
|
|
|
|
qupv3_se5_spi_miso_active {
|
|
phandle = <0x2ad>;
|
|
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup1_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_mosi_active {
|
|
phandle = <0x2ac>;
|
|
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup1_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_clk_active {
|
|
phandle = <0x2ae>;
|
|
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup1_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_cs_active {
|
|
phandle = <0x2af>;
|
|
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup1_se5_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_spi_sleep {
|
|
phandle = <0x2b0>;
|
|
|
|
mux {
|
|
pins = "gpio52\0gpio53\0gpio54\0gpio55";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52\0gpio53\0gpio54\0gpio55";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_pins {
|
|
phandle = <0x3b2>;
|
|
|
|
qupv3_se6_i2c_sda_active {
|
|
phandle = <0x2b1>;
|
|
|
|
mux {
|
|
pins = "gpio56";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_scl_active {
|
|
phandle = <0x2b2>;
|
|
|
|
mux {
|
|
pins = "gpio57";
|
|
function = "qup1_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio57";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_sleep {
|
|
phandle = <0x2b3>;
|
|
|
|
mux {
|
|
pins = "gpio56\0gpio57";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56\0gpio57";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_pins {
|
|
phandle = <0x3b3>;
|
|
|
|
qupv3_se6_spi_miso_active {
|
|
phandle = <0x2b5>;
|
|
|
|
mux {
|
|
pins = "gpio56";
|
|
function = "qup1_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_mosi_active {
|
|
phandle = <0x2b4>;
|
|
|
|
mux {
|
|
pins = "gpio57";
|
|
function = "qup1_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio57";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_clk_active {
|
|
phandle = <0x2b6>;
|
|
|
|
mux {
|
|
pins = "gpio58";
|
|
function = "qup1_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio58";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_cs_active {
|
|
phandle = <0x2b7>;
|
|
|
|
mux {
|
|
pins = "gpio59";
|
|
function = "qup1_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio59";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep {
|
|
phandle = <0x2b8>;
|
|
|
|
mux {
|
|
pins = "gpio56\0gpio57\0gpio58\0gpio59";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio56\0gpio57\0gpio58\0gpio59";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_pins {
|
|
phandle = <0x3b4>;
|
|
|
|
qupv3_se8_i2c_sda_active {
|
|
phandle = <0x2c0>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_scl_active {
|
|
phandle = <0x2c1>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i2c_sleep {
|
|
phandle = <0x2c2>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_pins {
|
|
phandle = <0x3b5>;
|
|
|
|
qupv3_se8_spi_miso_active {
|
|
phandle = <0x2c4>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_mosi_active {
|
|
phandle = <0x2c3>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_clk_active {
|
|
phandle = <0x2c5>;
|
|
|
|
mux {
|
|
pins = "gpio2";
|
|
function = "qup2_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio2";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_cs_active {
|
|
phandle = <0x2c6>;
|
|
|
|
mux {
|
|
pins = "gpio3";
|
|
function = "qup2_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio3";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_spi_sleep {
|
|
phandle = <0x2c7>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1\0gpio2\0gpio3";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_pins {
|
|
phandle = <0x3b6>;
|
|
|
|
qupv3_se8_i3c_sda_active {
|
|
phandle = <0x2c8>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_scl_active {
|
|
phandle = <0x2c9>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,apps;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_sda_sleep {
|
|
phandle = <0x2ca>;
|
|
|
|
mux {
|
|
pins = "gpio0";
|
|
function = "qup2_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,remote;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_scl_sleep {
|
|
phandle = <0x2cb>;
|
|
|
|
mux {
|
|
pins = "gpio1";
|
|
function = "qup2_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio1";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
qcom,remote;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_i3c_disable {
|
|
phandle = <0x2cc>;
|
|
|
|
mux {
|
|
pins = "gpio0\0gpio1";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio0\0gpio1";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_pins {
|
|
phandle = <0x3b7>;
|
|
|
|
qupv3_se9_i2c_sda_active {
|
|
phandle = <0x2cd>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_scl_active {
|
|
phandle = <0x2ce>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i2c_sleep {
|
|
phandle = <0x2cf>;
|
|
|
|
mux {
|
|
pins = "gpio4\0gpio5";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4\0gpio5";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_pins {
|
|
phandle = <0x3b8>;
|
|
|
|
qupv3_se9_spi_miso_active {
|
|
phandle = <0x2d1>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "qup2_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_mosi_active {
|
|
phandle = <0x2d0>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "qup2_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_clk_active {
|
|
phandle = <0x2d2>;
|
|
|
|
mux {
|
|
pins = "gpio6";
|
|
function = "qup2_se1_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio6";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_cs_active {
|
|
phandle = <0x2d3>;
|
|
|
|
mux {
|
|
pins = "gpio7";
|
|
function = "qup2_se1_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio7";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_spi_sleep {
|
|
phandle = <0x2d4>;
|
|
|
|
mux {
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4\0gpio5\0gpio6\0gpio7";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i3c_pins {
|
|
phandle = <0x3b9>;
|
|
|
|
qupv3_se9_i3c_sda_active {
|
|
phandle = <0x2d5>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i3c_scl_active {
|
|
phandle = <0x2d6>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i3c_sda_sleep {
|
|
phandle = <0x2d7>;
|
|
|
|
mux {
|
|
pins = "gpio4";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i3c_scl_sleep {
|
|
phandle = <0x2d8>;
|
|
|
|
mux {
|
|
pins = "gpio5";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio5";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se9_i3c_disable {
|
|
phandle = <0x2d9>;
|
|
|
|
mux {
|
|
pins = "gpio4\0gpio5";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio4\0gpio5";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_pins {
|
|
phandle = <0x3ba>;
|
|
|
|
qupv3_se10_i2c_sda_active {
|
|
phandle = <0x2da>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_scl_active {
|
|
phandle = <0x2db>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i2c_sleep {
|
|
phandle = <0x2dc>;
|
|
|
|
mux {
|
|
pins = "gpio8\0gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8\0gpio9";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_pins {
|
|
phandle = <0x3bb>;
|
|
|
|
qupv3_se10_spi_miso_active {
|
|
phandle = <0x2de>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup2_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_mosi_active {
|
|
phandle = <0x2dd>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup2_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_clk_active {
|
|
phandle = <0x2df>;
|
|
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup2_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_cs_active {
|
|
phandle = <0x2e0>;
|
|
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "qup2_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_spi_sleep {
|
|
phandle = <0x2e1>;
|
|
|
|
mux {
|
|
pins = "gpio8\0gpio9\0gpio10\0gpio11";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8\0gpio9\0gpio10\0gpio11";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_pins {
|
|
phandle = <0x3bc>;
|
|
|
|
qupv3_se10_i3c_sda_active {
|
|
phandle = <0x2e2>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_scl_active {
|
|
phandle = <0x2e3>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_sda_sleep {
|
|
phandle = <0x2e4>;
|
|
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_scl_sleep {
|
|
phandle = <0x2e5>;
|
|
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se10_i3c_disable {
|
|
phandle = <0x2e6>;
|
|
|
|
mux {
|
|
pins = "gpio8\0gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8\0gpio9";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_pins {
|
|
phandle = <0x3bd>;
|
|
|
|
qupv3_se11_i2c_sda_active {
|
|
phandle = <0x2e7>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_scl_active {
|
|
phandle = <0x2e8>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i2c_sleep {
|
|
phandle = <0x2e9>;
|
|
|
|
mux {
|
|
pins = "gpio12\0gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12\0gpio13";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_pins {
|
|
phandle = <0x3be>;
|
|
|
|
qupv3_se11_spi_miso_active {
|
|
phandle = <0x2eb>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup2_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_mosi_active {
|
|
phandle = <0x2ea>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup2_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_clk_active {
|
|
phandle = <0x2ec>;
|
|
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "qup2_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_cs_active {
|
|
phandle = <0x2ed>;
|
|
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "qup2_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_spi_sleep {
|
|
phandle = <0x2ee>;
|
|
|
|
mux {
|
|
pins = "gpio12\0gpio13\0gpio14\0gpio15";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12\0gpio13\0gpio14\0gpio15";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_pins {
|
|
phandle = <0x3bf>;
|
|
|
|
qupv3_se11_i3c_sda_active {
|
|
phandle = <0x2ef>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_scl_active {
|
|
phandle = <0x2f0>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_sda_sleep {
|
|
phandle = <0x2f1>;
|
|
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_scl_sleep {
|
|
phandle = <0x2f2>;
|
|
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se11_i3c_disable {
|
|
phandle = <0x2f3>;
|
|
|
|
mux {
|
|
pins = "gpio12\0gpio13";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12\0gpio13";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_pins {
|
|
phandle = <0x3c0>;
|
|
|
|
qupv3_se12_i2c_sda_active {
|
|
phandle = <0x2f4>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_scl_active {
|
|
phandle = <0x2f5>;
|
|
|
|
mux {
|
|
pins = "gpio17";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_i2c_sleep {
|
|
phandle = <0x2f6>;
|
|
|
|
mux {
|
|
pins = "gpio16\0gpio17";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16\0gpio17";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_pins {
|
|
phandle = <0x3c1>;
|
|
|
|
qupv3_se12_spi_miso_active {
|
|
phandle = <0x2f8>;
|
|
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "qup2_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_mosi_active {
|
|
phandle = <0x2f7>;
|
|
|
|
mux {
|
|
pins = "gpio17";
|
|
function = "qup2_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_clk_active {
|
|
phandle = <0x2f9>;
|
|
|
|
mux {
|
|
pins = "gpio18";
|
|
function = "qup2_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio18";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_cs_active {
|
|
phandle = <0x2fa>;
|
|
|
|
mux {
|
|
pins = "gpio19";
|
|
function = "qup2_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio19";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se12_spi_sleep {
|
|
phandle = <0x2fb>;
|
|
|
|
mux {
|
|
pins = "gpio16\0gpio17\0gpio18\0gpio19";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16\0gpio17\0gpio18\0gpio19";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_pins {
|
|
phandle = <0x3c2>;
|
|
|
|
qupv3_se13_i2c_sda_active {
|
|
phandle = <0x2fc>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_scl_active {
|
|
phandle = <0x2fd>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_i2c_sleep {
|
|
phandle = <0x2fe>;
|
|
|
|
mux {
|
|
pins = "gpio20\0gpio21";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20\0gpio21";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_pins {
|
|
phandle = <0x3c3>;
|
|
|
|
qupv3_se13_spi_miso_active {
|
|
phandle = <0x300>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_mosi_active {
|
|
phandle = <0x2ff>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_clk_active {
|
|
phandle = <0x301>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "qup2_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_cs_active {
|
|
phandle = <0x302>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "qup2_se5_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x06>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_sleep {
|
|
phandle = <0x303>;
|
|
|
|
mux {
|
|
pins = "gpio20\0gpio21\0gpio22";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20\0gpio21\0gpio22";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_spi_cs_sleep {
|
|
phandle = <0x304>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_pins {
|
|
phandle = <0x3c4>;
|
|
|
|
qupv3_se13_q2spi_default {
|
|
phandle = <0x306>;
|
|
|
|
mux {
|
|
pins = "gpio21\0gpio22\0gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21\0gpio22\0gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_default {
|
|
phandle = <0x305>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_active {
|
|
phandle = <0x308>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "qup2_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_mosi_active {
|
|
phandle = <0x307>;
|
|
|
|
mux {
|
|
pins = "gpio21";
|
|
function = "qup2_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio21";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_clk_active {
|
|
phandle = <0x309>;
|
|
|
|
mux {
|
|
pins = "gpio22";
|
|
function = "qup2_se5_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio22";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_doorbell_active {
|
|
phandle = <0x30a>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "qup2_se5_l6";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x06>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_doorbell_sleep {
|
|
phandle = <0x30c>;
|
|
|
|
mux {
|
|
pins = "gpio23";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio23";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se13_q2spi_miso_sleep {
|
|
phandle = <0x30b>;
|
|
|
|
mux {
|
|
pins = "gpio20";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio20";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_pins {
|
|
phandle = <0x3c5>;
|
|
|
|
qupv3_se15_i2c_sda_active {
|
|
phandle = <0x316>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "qup2_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_scl_active {
|
|
phandle = <0x317>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "qup2_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i2c_sleep {
|
|
phandle = <0x318>;
|
|
|
|
mux {
|
|
pins = "gpio28\0gpio29";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28\0gpio29";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_pins {
|
|
phandle = <0x3c6>;
|
|
|
|
qupv3_se15_spi_miso_active {
|
|
phandle = <0x31a>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "qup2_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_mosi_active {
|
|
phandle = <0x319>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "qup2_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_clk_active {
|
|
phandle = <0x31b>;
|
|
|
|
mux {
|
|
pins = "gpio30";
|
|
function = "qup2_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio30";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_cs_active {
|
|
phandle = <0x31c>;
|
|
|
|
mux {
|
|
pins = "gpio31";
|
|
function = "qup2_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio31";
|
|
drive-strength = <0x06>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_spi_sleep {
|
|
phandle = <0x31d>;
|
|
|
|
mux {
|
|
pins = "gpio28\0gpio29\0gpio30\0gpio31";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28\0gpio29\0gpio30\0gpio31";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i3c_pins {
|
|
phandle = <0x3c7>;
|
|
|
|
qupv3_se15_i3c_sda_active {
|
|
phandle = <0x31e>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i3c_scl_active {
|
|
phandle = <0x31f>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i3c_sda_sleep {
|
|
phandle = <0x320>;
|
|
|
|
mux {
|
|
pins = "gpio28";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i3c_scl_sleep {
|
|
phandle = <0x321>;
|
|
|
|
mux {
|
|
pins = "gpio29";
|
|
function = "ibi_i3c";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio29";
|
|
drive-strength = <0x10>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se15_i3c_disable {
|
|
phandle = <0x322>;
|
|
|
|
mux {
|
|
pins = "gpio28\0gpio29";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio28\0gpio29";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_pins {
|
|
phandle = <0x3c8>;
|
|
|
|
qupv3_hub_i2c0_sda_active {
|
|
phandle = <0x323>;
|
|
|
|
mux {
|
|
pins = "gpio64";
|
|
function = "i2chub0_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_scl_active {
|
|
phandle = <0x324>;
|
|
|
|
mux {
|
|
pins = "gpio65";
|
|
function = "i2chub0_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio65";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c0_sleep {
|
|
phandle = <0x325>;
|
|
|
|
mux {
|
|
pins = "gpio64\0gpio65";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64\0gpio65";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_pins {
|
|
phandle = <0x3c9>;
|
|
|
|
qupv3_hub_i2c1_sda_active {
|
|
phandle = <0x326>;
|
|
|
|
mux {
|
|
pins = "gpio66";
|
|
function = "i2chub0_se1_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_scl_active {
|
|
phandle = <0x327>;
|
|
|
|
mux {
|
|
pins = "gpio67";
|
|
function = "i2chub0_se1_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio67";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c1_sleep {
|
|
phandle = <0x328>;
|
|
|
|
mux {
|
|
pins = "gpio66\0gpio67";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio66\0gpio67";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_pins {
|
|
phandle = <0x3ca>;
|
|
|
|
qupv3_hub_i2c2_sda_active {
|
|
phandle = <0x329>;
|
|
|
|
mux {
|
|
pins = "gpio68";
|
|
function = "i2chub0_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio68";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_scl_active {
|
|
phandle = <0x32a>;
|
|
|
|
mux {
|
|
pins = "gpio69";
|
|
function = "i2chub0_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio69";
|
|
drive-strength = <0x02>;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c2_sleep {
|
|
phandle = <0x32b>;
|
|
|
|
mux {
|
|
pins = "gpio68\0gpio69";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio68\0gpio69";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_pins {
|
|
phandle = <0x3cb>;
|
|
|
|
qupv3_hub_i2c3_sda_active {
|
|
phandle = <0x32c>;
|
|
|
|
mux {
|
|
pins = "gpio70";
|
|
function = "i2chub0_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_scl_active {
|
|
phandle = <0x32d>;
|
|
|
|
mux {
|
|
pins = "gpio71";
|
|
function = "i2chub0_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio71";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c3_sleep {
|
|
phandle = <0x32e>;
|
|
|
|
mux {
|
|
pins = "gpio70\0gpio71";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio70\0gpio71";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_pins {
|
|
phandle = <0x3cc>;
|
|
|
|
qupv3_hub_i2c4_sda_active {
|
|
phandle = <0x32f>;
|
|
|
|
mux {
|
|
pins = "gpio72";
|
|
function = "i2chub0_se4_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio72";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_scl_active {
|
|
phandle = <0x330>;
|
|
|
|
mux {
|
|
pins = "gpio73";
|
|
function = "i2chub0_se4_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio73";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c4_sleep {
|
|
phandle = <0x331>;
|
|
|
|
mux {
|
|
pins = "gpio72\0gpio73";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio72\0gpio73";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_pins {
|
|
phandle = <0x3cd>;
|
|
|
|
qupv3_hub_i2c5_sda_active {
|
|
phandle = <0x332>;
|
|
|
|
mux {
|
|
pins = "gpio74";
|
|
function = "i2chub0_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio74";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_scl_active {
|
|
phandle = <0x333>;
|
|
|
|
mux {
|
|
pins = "gpio75";
|
|
function = "i2chub0_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio75";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c5_sleep {
|
|
phandle = <0x334>;
|
|
|
|
mux {
|
|
pins = "gpio74\0gpio75";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio74\0gpio75";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_pins {
|
|
phandle = <0x3ce>;
|
|
|
|
qupv3_hub_i2c6_sda_active {
|
|
phandle = <0x335>;
|
|
|
|
mux {
|
|
pins = "gpio76";
|
|
function = "i2chub0_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_scl_active {
|
|
phandle = <0x336>;
|
|
|
|
mux {
|
|
pins = "gpio77";
|
|
function = "i2chub0_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio77";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c6_sleep {
|
|
phandle = <0x337>;
|
|
|
|
mux {
|
|
pins = "gpio76\0gpio77";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio76\0gpio77";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_pins {
|
|
phandle = <0x3cf>;
|
|
|
|
qupv3_hub_i2c7_sda_active {
|
|
phandle = <0x338>;
|
|
|
|
mux {
|
|
pins = "gpio82";
|
|
function = "i2chub0_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio82";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_scl_active {
|
|
phandle = <0x339>;
|
|
|
|
mux {
|
|
pins = "gpio83";
|
|
function = "i2chub0_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio83";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c7_sleep {
|
|
phandle = <0x33a>;
|
|
|
|
mux {
|
|
pins = "gpio82\0gpio83";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio82\0gpio83";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_pins {
|
|
phandle = <0x3d0>;
|
|
|
|
qupv3_hub_i2c8_sda_active {
|
|
phandle = <0x33b>;
|
|
|
|
mux {
|
|
pins = "gpio206";
|
|
function = "i2chub0_se8_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio206";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_scl_active {
|
|
phandle = <0x33c>;
|
|
|
|
mux {
|
|
pins = "gpio207";
|
|
function = "i2chub0_se8_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio207";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c8_sleep {
|
|
phandle = <0x33d>;
|
|
|
|
mux {
|
|
pins = "gpio206\0gpio207";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio206\0gpio207";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_pins {
|
|
phandle = <0x3d1>;
|
|
|
|
qupv3_hub_i2c9_sda_active {
|
|
phandle = <0x33e>;
|
|
|
|
mux {
|
|
pins = "gpio80";
|
|
function = "i2chub0_se9_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_scl_active {
|
|
phandle = <0x33f>;
|
|
|
|
mux {
|
|
pins = "gpio81";
|
|
function = "i2chub0_se9_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio81";
|
|
drive-strength = <0x02>;
|
|
bias-pull-up;
|
|
qcom,i2c_pull;
|
|
};
|
|
};
|
|
|
|
qupv3_hub_i2c9_sleep {
|
|
phandle = <0x340>;
|
|
|
|
mux {
|
|
pins = "gpio80\0gpio81";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio80\0gpio81";
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_phy_ps {
|
|
phandle = <0x3d2>;
|
|
|
|
usb3phy_portselect_default {
|
|
phandle = <0x348>;
|
|
|
|
mux {
|
|
pins = "gpio61";
|
|
function = "usb_phy";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio61";
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
};
|
|
};
|
|
|
|
usb3phy_portselect_gpio {
|
|
phandle = <0x3d3>;
|
|
|
|
mux {
|
|
pins = "gpio61";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio61";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
input-enable;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_active {
|
|
|
|
ts_active {
|
|
phandle = <0x3d4>;
|
|
|
|
mux {
|
|
pins = "gpio161\0gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161\0gpio162";
|
|
drive-strength = <0x08>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_reset_suspend {
|
|
|
|
ts_reset_suspend {
|
|
phandle = <0x3d5>;
|
|
|
|
mux {
|
|
pins = "gpio161";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_int_suspend {
|
|
|
|
ts_int_suspend {
|
|
phandle = <0x3d6>;
|
|
|
|
mux {
|
|
pins = "gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio162";
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmx_ts_release {
|
|
|
|
ts_release {
|
|
phandle = <0x3d7>;
|
|
|
|
mux {
|
|
pins = "gpio161\0gpio162";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio161\0gpio162";
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
nfc {
|
|
|
|
nfc_int_active {
|
|
phandle = <0x55e>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio75";
|
|
};
|
|
|
|
config {
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
pins = "gpio75";
|
|
};
|
|
};
|
|
|
|
nfc_int_suspend {
|
|
phandle = <0x55f>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio75";
|
|
};
|
|
|
|
config {
|
|
bias-pull-down;
|
|
drive-strength = <0x02>;
|
|
pins = "gpio75";
|
|
};
|
|
};
|
|
|
|
nfc_enable_active {
|
|
phandle = <0x560>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio34\0gpio35";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
pins = "gpio34\0gpio35";
|
|
};
|
|
};
|
|
|
|
nfc_enable_suspend {
|
|
phandle = <0x561>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio34\0gpio35";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x02>;
|
|
pins = "gpio34\0gpio35";
|
|
};
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda0_active {
|
|
phandle = <0x5a3>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda0";
|
|
pins = "gpio113";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio113";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda0_suspend {
|
|
phandle = <0x5a5>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda0";
|
|
pins = "gpio113";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio113";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl0_active {
|
|
phandle = <0x5a2>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl0";
|
|
pins = "gpio114";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio114";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl0_suspend {
|
|
phandle = <0x5a4>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl0";
|
|
pins = "gpio114";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio114";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda1_active {
|
|
phandle = <0x5a7>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda1";
|
|
pins = "gpio115";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio115";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda1_suspend {
|
|
phandle = <0x5a9>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda1";
|
|
pins = "gpio115";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio115";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl1_active {
|
|
phandle = <0x5a6>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl1";
|
|
pins = "gpio116";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio116";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl1_suspend {
|
|
phandle = <0x5a8>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl1";
|
|
pins = "gpio116";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio116";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda2_active {
|
|
phandle = <0x5ab>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda2";
|
|
pins = "gpio117";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio117";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda2_suspend {
|
|
phandle = <0x5ad>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda2";
|
|
pins = "gpio117";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio117";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl2_active {
|
|
phandle = <0x5aa>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl2";
|
|
pins = "gpio118";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio118";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl2_suspend {
|
|
phandle = <0x5ac>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl2";
|
|
pins = "gpio118";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio118";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl3_active {
|
|
phandle = <0x5ae>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl3";
|
|
pins = "gpio164";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio164";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda3_suspend {
|
|
phandle = <0x5b1>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda3";
|
|
pins = "gpio111";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio111";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda3_active {
|
|
phandle = <0x5af>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda3";
|
|
pins = "gpio111";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio111";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl3_suspend {
|
|
phandle = <0x5b0>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl3";
|
|
pins = "gpio164";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio164";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda4_active {
|
|
phandle = <0x5b3>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda4";
|
|
pins = "gpio112";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio112";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda4_suspend {
|
|
phandle = <0x5b5>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda4";
|
|
pins = "gpio112";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio112";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl4_active {
|
|
phandle = <0x5b2>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl4";
|
|
pins = "gpio153";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio153";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl4_suspend {
|
|
phandle = <0x5b4>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl4";
|
|
pins = "gpio153";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio153";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda5_active {
|
|
phandle = <0x5b7>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda5";
|
|
pins = "gpio119";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio119";
|
|
};
|
|
};
|
|
|
|
cci_i2c_sda5_suspend {
|
|
phandle = <0x5b9>;
|
|
|
|
mux {
|
|
function = "cci_i2c_sda5";
|
|
pins = "gpio119";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio119";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl5_active {
|
|
phandle = <0x5b6>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl5";
|
|
pins = "gpio120";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
qcom,i2c_pull;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio120";
|
|
};
|
|
};
|
|
|
|
cci_i2c_scl5_suspend {
|
|
phandle = <0x5b8>;
|
|
|
|
mux {
|
|
function = "cci_i2c_scl5";
|
|
pins = "gpio120";
|
|
};
|
|
|
|
config {
|
|
bias-disable;
|
|
drive-strength = <0x06>;
|
|
pins = "gpio120";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_active {
|
|
phandle = <0x5d5>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio89";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio89";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk0_suspend {
|
|
phandle = <0x5d6>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio89";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio89";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_active {
|
|
phandle = <0x5d7>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio90";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio90";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk1_suspend {
|
|
phandle = <0x5d8>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio90";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio90";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_active {
|
|
phandle = <0x5d9>;
|
|
|
|
mux {
|
|
function = "cam_asc_mclk2";
|
|
pins = "gpio91";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio91";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk2_suspend {
|
|
phandle = <0x5da>;
|
|
|
|
mux {
|
|
function = "cam_asc_mclk2";
|
|
pins = "gpio91";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio91";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_active {
|
|
phandle = <0x5db>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio92";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio92";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk3_suspend {
|
|
phandle = <0x5dc>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio92";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio92";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk4_active {
|
|
phandle = <0x5dd>;
|
|
|
|
mux {
|
|
function = "cam_asc_mclk4";
|
|
pins = "gpio93";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio93";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk4_suspend {
|
|
phandle = <0x5de>;
|
|
|
|
mux {
|
|
function = "cam_asc_mclk4";
|
|
pins = "gpio93";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio93";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk5_active {
|
|
phandle = <0x5df>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio94";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio94";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk5_suspend {
|
|
phandle = <0x5e0>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio94";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio94";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk6_active {
|
|
phandle = <0x5e1>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio96";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio96";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk6_suspend {
|
|
phandle = <0x5e2>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio96";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio96";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk7_active {
|
|
phandle = <0x5e3>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio95";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio95";
|
|
};
|
|
};
|
|
|
|
cam_sensor_mclk7_suspend {
|
|
phandle = <0x5e4>;
|
|
|
|
mux {
|
|
function = "cam_mclk";
|
|
pins = "gpio95";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio95";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst0 {
|
|
phandle = <0x5e5>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio13";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio13";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst0 {
|
|
phandle = <0x5e6>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio13";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio13";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst1 {
|
|
phandle = <0x5e7>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio15";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio15";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst1 {
|
|
phandle = <0x5e8>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio15";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio15";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst2 {
|
|
phandle = <0x5e9>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio3";
|
|
};
|
|
|
|
config {
|
|
qcom,apps;
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio3";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst2 {
|
|
phandle = <0x5ea>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio3";
|
|
};
|
|
|
|
config {
|
|
qcom,remote;
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio3";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst3 {
|
|
phandle = <0x5eb>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio109";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio109";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst3 {
|
|
phandle = <0x5ec>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio109";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio109";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst4 {
|
|
phandle = <0x5ed>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio7";
|
|
};
|
|
|
|
config {
|
|
qcom,apps;
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio7";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst4 {
|
|
phandle = <0x5ee>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio7";
|
|
};
|
|
|
|
config {
|
|
qcom,remote;
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio7";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst5 {
|
|
phandle = <0x5ef>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio110";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio110";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst5 {
|
|
phandle = <0x5f0>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio110";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio110";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst6 {
|
|
phandle = <0x5f1>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio111";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio111";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst6 {
|
|
phandle = <0x5f2>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio111";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio111";
|
|
};
|
|
};
|
|
|
|
cam_sensor_active_rst7 {
|
|
phandle = <0x5f3>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio164";
|
|
};
|
|
|
|
config {
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio164";
|
|
};
|
|
};
|
|
|
|
cam_sensor_suspend_rst7 {
|
|
phandle = <0x5f4>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio164";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio164";
|
|
};
|
|
};
|
|
|
|
cam_sensor_i3cSelect_active {
|
|
phandle = <0x5f5>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio6";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio6";
|
|
};
|
|
};
|
|
|
|
cam_sensor_i3cSelect_suspend {
|
|
phandle = <0x5f6>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio6";
|
|
};
|
|
|
|
config {
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio6";
|
|
};
|
|
};
|
|
|
|
cam_sensor_ponv_rear_active {
|
|
phandle = <0x5f7>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio2";
|
|
};
|
|
|
|
config {
|
|
qcom,apps;
|
|
drive-strength = <0x02>;
|
|
bias-disable;
|
|
pins = "gpio2";
|
|
};
|
|
};
|
|
|
|
cam_sensor_ponv_rear_suspend {
|
|
phandle = <0x5f8>;
|
|
|
|
mux {
|
|
function = "gpio";
|
|
pins = "gpio2";
|
|
};
|
|
|
|
config {
|
|
qcom,remote;
|
|
output-low;
|
|
drive-strength = <0x02>;
|
|
bias-pull-down;
|
|
pins = "gpio2";
|
|
};
|
|
};
|
|
};
|
|
|
|
tlmm-vm-mem-access {
|
|
compatible = "qcom,tlmm-vm-mem-access";
|
|
qcom,master;
|
|
|
|
tuivm {
|
|
qcom,label = <0x08>;
|
|
qcom,vmid = <0x2d>;
|
|
tlmm-vm-gpio-list = <0x26 0x56 0x00 0x26 0x57 0x00 0x26 0x62 0x00 0x26 0x61 0x00 0x26 0x30 0x00 0x26 0x31 0x00 0x26 0x32 0x00 0x26 0x33 0x00 0x26 0xa1 0x00 0x26 0xa2 0x00 0x26 0x64 0x00 0x26 0x1c 0x00 0x26 0x1d 0x00 0x26 0x1e 0x00 0x26 0x1f 0x00 0x26 0x58 0x00>;
|
|
};
|
|
};
|
|
|
|
tlmm-vm-test {
|
|
compatible = "qcom,tlmm-vm-test";
|
|
qcom,master;
|
|
tlmm-vm-gpio-list = <0x26 0x56 0x00 0x26 0x57 0x00 0x26 0x62 0x00 0x26 0x61 0x00 0x26 0x30 0x00 0x26 0x31 0x00 0x26 0x32 0x00 0x26 0x33 0x00 0x26 0xa1 0x00 0x26 0xa2 0x00 0x26 0x64 0x00 0x26 0x1c 0x00 0x26 0x1d 0x00 0x26 0x1e 0x00 0x26 0x1f 0x00 0x26 0x58 0x00>;
|
|
};
|
|
|
|
bamdma@6C04000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
qcom,controlled-remotely;
|
|
reg = <0x6c04000 0x20000 0x6c8f000 0x1000>;
|
|
reg-names = "bam\0bam_remote_mem";
|
|
num-channels = <0x1f>;
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
#dma-cells = <0x01>;
|
|
qcom,ee = <0x01>;
|
|
qcom,num-ees = <0x02>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
slim@6C40000 {
|
|
compatible = "qcom,slim-ngd-v1.5.0";
|
|
reg = <0x6c40000 0x2c000 0x6c8e000 0x1000>;
|
|
reg-names = "ctrl\0slimbus_remote_mem";
|
|
interrupts = <0x00 0xa3 0x04>;
|
|
qcom,apps-ch-pipes = <0x00>;
|
|
qcom,ea-pc = <0x4e0>;
|
|
dmas = <0x27 0x03 0x27 0x04>;
|
|
dma-names = "rx\0tx";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x3d8>;
|
|
};
|
|
|
|
show_resume_irqs@16000000 {
|
|
compatible = "qcom,show-resume-irqs";
|
|
reg = <0x16000000 0x10000>;
|
|
};
|
|
|
|
interrupt-controller@16000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
ranges;
|
|
#redistributor-regions = <0x01>;
|
|
redistributor-stride = <0x00 0x40000>;
|
|
reg = <0x16000000 0x10000 0x16080000 0x200000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
phandle = <0x01>;
|
|
|
|
msi-controller@0x16040000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
#msi-cells = <0x01>;
|
|
reg = <0x16040000 0x20000>;
|
|
phandle = <0x7c>;
|
|
};
|
|
};
|
|
|
|
timer@16800000 {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x16800000 0x1000>;
|
|
clock-frequency = <0x124f800>;
|
|
phandle = <0x3d9>;
|
|
|
|
frame@16801000 {
|
|
frame-number = <0x00>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x06 0x04>;
|
|
reg = <0x16801000 0x1000 0x16802000 0x1000>;
|
|
};
|
|
|
|
frame@16803000 {
|
|
frame-number = <0x01>;
|
|
interrupts = <0x00 0x09 0x04>;
|
|
reg = <0x16803000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@16805000 {
|
|
frame-number = <0x02>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0x16805000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@16807000 {
|
|
frame-number = <0x03>;
|
|
interrupts = <0x00 0x0b 0x04>;
|
|
reg = <0x16807000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@16809000 {
|
|
frame-number = <0x04>;
|
|
interrupts = <0x00 0x0c 0x04>;
|
|
reg = <0x16809000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1680b000 {
|
|
frame-number = <0x05>;
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
reg = <0x1680b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1680d000 {
|
|
frame-number = <0x06>;
|
|
interrupts = <0x00 0x0e 0x04>;
|
|
reg = <0x1680d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupt-parent = <0x25>;
|
|
interrupts = <0x0b 0x04>;
|
|
reg = <0x88e0000 0x2000 0x88e2000 0x1000>;
|
|
reg-names = "eud_base\0eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-utmi-delay = [00 ff];
|
|
status = "ok";
|
|
phandle = <0x341>;
|
|
};
|
|
|
|
cache-controller@24800000 {
|
|
compatible = "qcom,sun-llcc";
|
|
reg = <0x24800000 0x200000 0x25800000 0x200000 0x24c00000 0x200000 0x25c00000 0x200000 0x26800000 0x200000 0x26c00000 0x200000>;
|
|
reg-names = "llcc0_base\0llcc1_base\0llcc2_base\0llcc3_base\0llcc_broadcast_or_base\0llcc_broadcast_and_base";
|
|
interrupts = <0x00 0x10a 0x04>;
|
|
cap-based-alloc-and-pwr-collapse;
|
|
|
|
llcc_perfmon {
|
|
compatible = "qcom,llcc-perfmon";
|
|
clocks = <0x19 0x00>;
|
|
clock-names = "qdss_clk";
|
|
};
|
|
|
|
scid_heuristics {
|
|
compatible = "qcom,scid-heuristics";
|
|
qcom,heuristics-scid = <0x20>;
|
|
qcom,freq-threshold-idx = <0x0b 0x0a>;
|
|
qcom,frequency-threshold-residency = <0x1388 0x1388>;
|
|
qcom,scid-heuristics-enabled;
|
|
};
|
|
};
|
|
|
|
gic-interrupt-router {
|
|
compatible = "qcom,gic-intr-routing";
|
|
qcom,gic-class0-cpus = <0x10 0x11>;
|
|
qcom,gic-class1-cpus = <0x12 0x13 0x14 0x15 0x16 0x17>;
|
|
};
|
|
|
|
qcom,secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
qcom,vmid-cp-camera-preview-ro;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <0x03>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
qcom,msgq-names = "trusted_vm";
|
|
};
|
|
|
|
qcom,hdcp {
|
|
compatible = "qcom,hdcp";
|
|
qcom,use-smcinvoke = <0x01>;
|
|
};
|
|
|
|
qti,smmu-proxy {
|
|
compatible = "smmu-proxy-sender";
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>;
|
|
clock-frequency = <0x124f800>;
|
|
phandle = <0x3da>;
|
|
};
|
|
|
|
bcm_voter@0 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "pcie_crm";
|
|
qcom,crm-client-idx = <0x00>;
|
|
qcom,crm-pwr-states = <0x05>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
bcm_voter@1 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x00>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
bcm_voter@2 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x01>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
bcm_voter@3 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x02>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
bcm_voter@4 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x03>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
bcm_voter@5 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x04>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
bcm_voter@6 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-client-idx = <0x05>;
|
|
qcom,crm-pwr-states = <0x02>;
|
|
phandle = <0x32>;
|
|
};
|
|
|
|
bcm_voter@7 {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,crm-name = "disp_crm";
|
|
qcom,crm-sw-client;
|
|
qcom,crm-client-idx = <0x00>;
|
|
qcom,crm-pwr-states = <0x01>;
|
|
phandle = <0x33>;
|
|
};
|
|
|
|
interconnect@0 {
|
|
compatible = "qcom,sun-clk_virt";
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0";
|
|
qcom,bcm-voters = <0x28 0x29>;
|
|
phandle = <0x270>;
|
|
};
|
|
|
|
interconnect@1 {
|
|
compatible = "qcom,sun-mc_virt";
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0disp_crm_hw_0\0disp_crm_hw_1\0disp_crm_hw_2\0disp_crm_hw_3\0disp_crm_hw_4\0disp_crm_hw_5\0disp_crm_sw_0";
|
|
qcom,bcm-voters = <0x28 0x2a 0x2b 0x2c 0x29 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33>;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
interconnect@1600000 {
|
|
compatible = "qcom,sun-cnoc_cfg";
|
|
reg = <0x1600000 0x6200>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x79>;
|
|
};
|
|
|
|
interconnect@1500000 {
|
|
compatible = "qcom,sun-cnoc_main";
|
|
reg = <0x1500000 0x16080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0xf4>;
|
|
};
|
|
|
|
interconnect@1680000 {
|
|
compatible = "qcom,sun-system_noc";
|
|
reg = <0x1680000 0x1d080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x269>;
|
|
};
|
|
|
|
interconnect@16c0000 {
|
|
compatible = "qcom,sun-pcie_anoc";
|
|
reg = <0x16c0000 0x11400>;
|
|
#interconnect-cells = <0x01>;
|
|
clocks = <0x34 0x00 0x34 0x0a>;
|
|
qcom,bcm-voter-names = "hlos\0pcie_crm_hw_0";
|
|
qcom,bcm-voters = <0x28 0x29>;
|
|
phandle = <0x26a>;
|
|
};
|
|
|
|
interconnect@16e0000 {
|
|
compatible = "qcom,sun-aggre1_noc";
|
|
reg = <0x16e0000 0x16400>;
|
|
#interconnect-cells = <0x01>;
|
|
clocks = <0x34 0x01 0x34 0x03>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
interconnect@1700000 {
|
|
compatible = "qcom,sun-aggre2_noc";
|
|
reg = <0x1700000 0x1f400>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
clocks = <0x35 0x0c>;
|
|
phandle = <0x44>;
|
|
};
|
|
|
|
interconnect@1780000 {
|
|
compatible = "qcom,sun-mmss_noc";
|
|
reg = <0x1780000 0x5b800>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos\0cam_ife_0\0cam_ife_1\0cam_ife_2\0disp_crm_hw_0\0disp_crm_hw_1\0disp_crm_hw_2\0disp_crm_hw_3\0disp_crm_hw_4\0disp_crm_hw_5\0disp_crm_sw_0";
|
|
qcom,bcm-voters = <0x28 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
interconnect@24100000 {
|
|
compatible = "qcom,sun-gem_noc";
|
|
reg = <0x24100000 0x14b080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos\0cam_ife_0\0cam_ife_1\0cam_ife_2\0pcie_crm_hw_0\0disp_crm_hw_0\0disp_crm_hw_1\0disp_crm_hw_2\0disp_crm_hw_3\0disp_crm_hw_4\0disp_crm_hw_5\0disp_crm_sw_0";
|
|
qcom,bcm-voters = <0x28 0x2a 0x2b 0x2c 0x29 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33>;
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
interconnect@320c0000 {
|
|
compatible = "qcom,sun-nsp_noc";
|
|
reg = <0x320c0000 0x13080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
interconnect@7e40000 {
|
|
compatible = "qcom,sun-lpass_ag_noc";
|
|
reg = <0x7e40000 0xe080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x3db>;
|
|
};
|
|
|
|
interconnect@7400000 {
|
|
compatible = "qcom,sun-lpass_lpiaon_noc";
|
|
reg = <0x7400000 0x19080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x3dc>;
|
|
};
|
|
|
|
interconnect@7420000 {
|
|
compatible = "qcom,sun-lpass_lpicx_noc";
|
|
reg = <0x7420000 0x44080>;
|
|
#interconnect-cells = <0x01>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <0x28>;
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
rsc@16500000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x16500000 0x10000 0x16510000 0x10000 0x16520000 0x10000>;
|
|
reg-names = "drv-0\0drv-1\0drv-2";
|
|
qcom,drv-count = <0x03>;
|
|
interrupts = <0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04>;
|
|
power-domains = <0x1c>;
|
|
phandle = <0x3dd>;
|
|
|
|
drv@2 {
|
|
qcom,drv-id = <0x02>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,tcs-distance = <0x2a0>;
|
|
phandle = <0x3de>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x03 0x00 0x02 0x01 0x02 0x03 0x00 0x04 0x01>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
clock-controller {
|
|
compatible = "qcom,sun-rpmh-clk";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x35>;
|
|
};
|
|
|
|
qcom,dcvs-fp {
|
|
compatible = "qcom,dcvs-fp";
|
|
qcom,ddr-bcm-name = "MC4";
|
|
qcom,llcc-bcm-name = "SH5";
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
rpmh-regulator-gfxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "gfx.lvl";
|
|
proxy-supply = <0x36>;
|
|
|
|
regulator-pm-v8d-s5-level {
|
|
regulator-name = "pm_v8d_s5_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x40 0xffff>;
|
|
phandle = <0x36>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-gmxclvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "gmxc.lvl";
|
|
|
|
regulator-pm-v8d-s2-level {
|
|
regulator-name = "pm_v8d_s2_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3df>;
|
|
};
|
|
|
|
regulator-pm-v8d-s2-gfx-voter-level {
|
|
regulator-name = "pm_v8d_s2_gfx_voter_level";
|
|
pm_v8d_s2_gfx_voter_level-parent-supply = <0x36>;
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0x51>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mx.lvl";
|
|
proxy-supply = <0x37>;
|
|
|
|
regulator-vdd-mxa-level {
|
|
regulator-name = "pm_v6f_s6_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
regulator-vdd-mxa-level-ao {
|
|
regulator-name = "pm_v6f_s6_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3e0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ebilvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "ebi.lvl";
|
|
|
|
regulator-pm-v8g-s2-level {
|
|
regulator-name = "pm_v8g_s2_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3e1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-msslvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mss.lvl";
|
|
|
|
regulator-pm-v8g-s5-level {
|
|
regulator-name = "pm_v8g_s5_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x8a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-nsplvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "nsp.lvl";
|
|
|
|
regulator-pm-v8g-s7-level {
|
|
regulator-name = "pm_v8g_s7_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x92>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-nsp2lvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "nsp2.lvl";
|
|
|
|
regulator-pm-v8i-s1-level {
|
|
regulator-name = "pm_v8i_s1_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3e2>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-cxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "cx.lvl";
|
|
proxy-supply = <0x38>;
|
|
|
|
regulator-pm-v6j-s1-level {
|
|
regulator-name = "pm_v6j_s1_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
regulator-pm-v6j-s1-level-ao {
|
|
regulator-name = "pm_v6j_s1_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3e3>;
|
|
};
|
|
|
|
regulator-pm-v6j-s1-mmcx-sup-level {
|
|
regulator-name = "pm_v6j_s1_mmcx_sup_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0x3a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mmcxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mmcx.lvl";
|
|
proxy-supply = <0x39>;
|
|
|
|
regulator-pm-v8i-s3-level {
|
|
regulator-name = "pm_v8i_s3_level";
|
|
qcom,set = <0x03>;
|
|
pm_v8i_s3_level-parent-supply = <0x3a>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
regulator-pm-v8i-s3-level-ao {
|
|
regulator-name = "pm_v8i_s3_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x38>;
|
|
phandle = <0x3e4>;
|
|
};
|
|
|
|
regulator-pm-v8i-s3-level-so {
|
|
regulator-name = "pm_v8i_s3_level_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0x38>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x38>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-lcxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "lcx.lvl";
|
|
|
|
regulator-pm-v8i-s5-level {
|
|
regulator-name = "pm_v8i_s5_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x83>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-mxclvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "mxc.lvl";
|
|
proxy-supply = <0x3b>;
|
|
|
|
regulator-pm-v8i-s6-level {
|
|
regulator-name = "pm_v8i_s6_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x180>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,proxy-consumer-voltage = <0x180 0xffff>;
|
|
phandle = <0x3b>;
|
|
};
|
|
|
|
regulator-pm-v8i-s6-level-ao {
|
|
regulator-name = "pm_v8i_s6_level_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x3e5>;
|
|
};
|
|
|
|
regulator-pm-v8i-s6-mmcx-voter-level {
|
|
regulator-name = "pm_v8i_s6_mmcx_voter_level";
|
|
pm_v8i_s6_mmcx_voter_level-parent-supply = <0x39>;
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x30>;
|
|
phandle = <0x52>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-lmxlvl {
|
|
compatible = "qcom,rpmh-arc-regulator";
|
|
qcom,resource-name = "lmx.lvl";
|
|
|
|
regulator-pm-v6j-l3-level {
|
|
regulator-name = "pm_v6j_l3_level";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10>;
|
|
regulator-max-microvolt = <0xffff>;
|
|
qcom,init-voltage-level = <0x10>;
|
|
phandle = <0x84>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l1 {
|
|
regulator-name = "pm_humu_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3e6>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l2 {
|
|
regulator-name = "pm_humu_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = <0x2e8240>;
|
|
qcom,init-voltage = <0x2de600>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3e7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l4 {
|
|
regulator-name = "pm_humu_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3e8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l5 {
|
|
regulator-name = "pm_humu_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2f4d60>;
|
|
regulator-max-microvolt = <0x3008e0>;
|
|
qcom,init-voltage = "\0/]";
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3e9>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l6 {
|
|
regulator-name = "pm_humu_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ea>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob7";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l7 {
|
|
regulator-name = "pm_humu_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3eb>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob8 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob8";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l8 {
|
|
regulator-name = "pm_humu_l8";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ec>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob9 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob9";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l9 {
|
|
regulator-name = "pm_humu_l9";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x2d2a80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ed>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob10 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob10";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l10 {
|
|
regulator-name = "pm_humu_l10";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ee>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob11 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob11";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l11 {
|
|
regulator-name = "pm_humu_l11";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x103c40>;
|
|
regulator-max-microvolt = <0x13b6e0>;
|
|
qcom,init-voltage = <0x103c40>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3ef>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob12 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob12";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l12 {
|
|
regulator-name = "pm_humu_l12";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3f0>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob13 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob13";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l13 {
|
|
regulator-name = "pm_humu_l13";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2dc6c0>;
|
|
regulator-max-microvolt = <0x2dc6c0>;
|
|
qcom,init-voltage = <0x2dc6c0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3f1>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob14 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob14";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l14 {
|
|
regulator-name = "pm_humu_l14";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x30d400>;
|
|
regulator-max-microvolt = <0x30d400>;
|
|
qcom,init-voltage = <0x30d400>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3f2>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob15 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob15";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-humu-l15 {
|
|
regulator-name = "pm_humu_l15";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x296>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob16 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob16";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l16 {
|
|
regulator-name = "pm_humu_l16";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3f3>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldob17 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldob17";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x2710>;
|
|
|
|
regulator-pm-humu-l17 {
|
|
regulator-name = "pm_humu_l17";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x263540>;
|
|
regulator-max-microvolt = <0x263540>;
|
|
qcom,init-voltage = <0x263540>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3f4>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-bobb1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "bobb1";
|
|
|
|
regulator-pm-humu-bob1 {
|
|
regulator-name = "pm_humu_bob1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2de600>;
|
|
regulator-max-microvolt = "\0=\t";
|
|
qcom,init-voltage = "\02K";
|
|
phandle = <0x3f5>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-bobb2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "bobb2";
|
|
|
|
regulator-pm-humu-bob2 {
|
|
regulator-name = "pm_humu_bob2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x294280>;
|
|
regulator-max-microvolt = <0x2de600>;
|
|
qcom,init-voltage = <0x298100>;
|
|
phandle = <0x3f6>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpd1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpd1";
|
|
|
|
regulator-pm-v8d-s1 {
|
|
regulator-name = "pm_v8d_s1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
qcom,init-voltage = <0xee480>;
|
|
phandle = <0x3f7>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpd3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpd3";
|
|
|
|
regulator-pm-v8d-s3 {
|
|
regulator-name = "pm_v8d_s3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x13d620>;
|
|
qcom,init-voltage = <0x12ad40>;
|
|
phandle = <0x3f8>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpd4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpd4";
|
|
|
|
regulator-pm-v8d-s4 {
|
|
regulator-name = "pm_v8d_s4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0xfcee0>;
|
|
qcom,init-voltage = <0xd0020>;
|
|
phandle = <0x3f9>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldod1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldod1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8d-l1 {
|
|
regulator-name = "pm_v8d_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3fa>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldod2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldod2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8d-l2 {
|
|
regulator-name = "pm_v8d_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x346>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldod3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldod3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8d-l3 {
|
|
regulator-name = "pm_v8d_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x3fb>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpf5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpf5";
|
|
phandle = <0x3fc>;
|
|
|
|
regulator-pm-v8f-s5 {
|
|
regulator-name = "pm_v8f_s5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0xf4240>;
|
|
qcom,init-voltage = <0xd0020>;
|
|
phandle = <0x3fd>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldof1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
qcom,send-defaults;
|
|
|
|
regulator-pm-vxf-l1 {
|
|
regulator-name = "pm_v6f_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x347>;
|
|
};
|
|
|
|
regulator-pm-vxf-l1-ao {
|
|
regulator-name = "pm_v6f_l1_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
regulator-always-on;
|
|
phandle = <0x3fe>;
|
|
};
|
|
|
|
regulator-pm-vxf-l1-so {
|
|
regulator-name = "pm_v6f_l1_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x02>;
|
|
qcom,init-enable = <0x00>;
|
|
phandle = <0x3ff>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldof2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-vxf-l2 {
|
|
regulator-name = "pm_v6f_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x02>;
|
|
regulator-always-on;
|
|
phandle = <0x400>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldof3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldof3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-vxf-l3 {
|
|
regulator-name = "pm_v6f_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x02>;
|
|
phandle = <0x401>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpg1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpg1";
|
|
|
|
regulator-pm-v8g-s1 {
|
|
regulator-name = "pm_v8g_s1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x493e0>;
|
|
regulator-max-microvolt = <0xaae60>;
|
|
qcom,init-voltage = <0x7a120>;
|
|
phandle = <0x402>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpg3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpg3";
|
|
|
|
regulator-pm-v8g-s3 {
|
|
regulator-name = "pm_v8g_s3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1c5200>;
|
|
regulator-max-microvolt = <0x1e8480>;
|
|
qcom,init-voltage = <0x1c5200>;
|
|
phandle = <0x403>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpg4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpg4";
|
|
|
|
regulator-pm-v8g-s4 {
|
|
regulator-name = "pm_v8g_s4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x493e0>;
|
|
regulator-max-microvolt = <0xdbba0>;
|
|
qcom,init-voltage = <0xb7980>;
|
|
phandle = <0x404>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8g-l1 {
|
|
regulator-name = "pm_v8g_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdea80>;
|
|
regulator-max-microvolt = <0xe4840>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x405>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8g-l2 {
|
|
regulator-name = "pm_v8g_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x1c61a0>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x406>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldog3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldog3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
proxy-supply = <0x3c>;
|
|
qcom,send-defaults;
|
|
|
|
regulator-pm-v8g-l3 {
|
|
regulator-name = "pm_v8g_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x132a40>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
qcom,proxy-consumer-enable;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
regulator-pm-v8g-l3-ao {
|
|
regulator-name = "pm_v8g_l3_ao";
|
|
qcom,set = <0x01>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x132a40>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
regulator-always-on;
|
|
phandle = <0x407>;
|
|
};
|
|
|
|
regulator-pm-v8g-l3-so {
|
|
regulator-name = "pm_v8g_l3_so";
|
|
qcom,set = <0x02>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x132a40>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x02>;
|
|
qcom,init-enable = <0x00>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpi7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpi7";
|
|
qcom,regulator-type = "pmic5-ftsmps";
|
|
qcom,supported-modes = <0x01 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x30d40>;
|
|
|
|
regulator-pm-v8i-s7 {
|
|
regulator-name = "pm_v8i_s7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x12ad40>;
|
|
regulator-max-microvolt = <0x147260>;
|
|
qcom,init-voltage = <0x132a40>;
|
|
qcom,init-mode = <0x01>;
|
|
phandle = <0x408>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpi8 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpi8";
|
|
|
|
regulator-pm-v8i-s8 {
|
|
regulator-name = "pm_v8i_s8";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdbba0>;
|
|
regulator-max-microvolt = <0xed4e0>;
|
|
qcom,init-voltage = <0xdcb40>;
|
|
phandle = <0x409>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8i-l1 {
|
|
regulator-name = "pm_v8i_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x40a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x01 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v8i-l2 {
|
|
regulator-name = "pm_v8i_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x40b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoi3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoi3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
proxy-supply = <0x3d>;
|
|
|
|
regulator-pm-v8i-l3 {
|
|
regulator-name = "pm_v8i_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xdea80>;
|
|
qcom,init-voltage = <0xd6d80>;
|
|
qcom,init-mode = <0x04>;
|
|
qcom,proxy-consumer-enable;
|
|
phandle = <0x3d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpj2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpj2";
|
|
|
|
regulator-pm-v6j-s2 {
|
|
regulator-name = "pm_v6j_s2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
qcom,init-voltage = <0x107ac0>;
|
|
phandle = <0x40c>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpj3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpj3";
|
|
|
|
regulator-pm-v6j-s3 {
|
|
regulator-name = "pm_v6j_s3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xf4240>;
|
|
regulator-max-microvolt = <0x10c8e0>;
|
|
qcom,init-voltage = <0x100d60>;
|
|
phandle = <0x40d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-smpj4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "smpj4";
|
|
phandle = <0x40e>;
|
|
|
|
regulator-pm-v6j-s4 {
|
|
regulator-name = "pm_v6j_s4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x7a120>;
|
|
regulator-max-microvolt = <0xf4240>;
|
|
qcom,init-voltage = <0xd0020>;
|
|
phandle = <0x40f>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoj1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoj1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6j-l1 {
|
|
regulator-name = "pm_v6j_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xd6d80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x410>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldoj2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldoj2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x01 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm-v6j-l2 {
|
|
regulator-name = "pm_v6j_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x42>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l1 {
|
|
regulator-name = "pmr_nalojr_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x61a80>;
|
|
regulator-max-microvolt = <0xe09c0>;
|
|
qcom,init-voltage = <0xd0fc0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x411>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l2 {
|
|
regulator-name = "pmr_nalojr_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xdea80>;
|
|
regulator-max-microvolt = <0xf4240>;
|
|
qcom,init-voltage = <0xdea80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x412>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok3";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l3 {
|
|
regulator-name = "pmr_nalojr_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x413>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok4";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l4 {
|
|
regulator-name = "pmr_nalojr_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x124f80>;
|
|
regulator-max-microvolt = <0x124f80>;
|
|
qcom,init-voltage = <0x124f80>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x414>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok5";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l5 {
|
|
regulator-name = "pmr_nalojr_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0xe86c0>;
|
|
regulator-max-microvolt = <0xee480>;
|
|
qcom,init-voltage = <0xe86c0>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x415>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok6";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l6 {
|
|
regulator-name = "pmr_nalojr_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b1980>;
|
|
regulator-max-microvolt = <0x1c61a0>;
|
|
qcom,init-voltage = <0x1b1980>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x416>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldok7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldok7";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pmr-nalojr-l7 {
|
|
regulator-name = "pmr_nalojr_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = "\0\f5";
|
|
regulator-max-microvolt = "\0\f5";
|
|
qcom,init-voltage = "\0\f5";
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x417>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010m-l1 {
|
|
regulator-name = "pm8010m_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10d880>;
|
|
regulator-max-microvolt = <0x10d880>;
|
|
qcom,init-voltage = <0x10d880>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x418>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010m-l2 {
|
|
regulator-name = "pm8010m_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x101d00>;
|
|
regulator-max-microvolt = <0x101d00>;
|
|
qcom,init-voltage = <0x101d00>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x419>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom3";
|
|
|
|
regulator-pm8010m-l3 {
|
|
regulator-name = "pm8010m_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x41a>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom4";
|
|
|
|
regulator-pm8010m-l4 {
|
|
regulator-name = "pm8010m_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x41b>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom5";
|
|
|
|
regulator-pm8010m-l5 {
|
|
regulator-name = "pm8010m_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x41c>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom6";
|
|
|
|
regulator-pm8010m-l6 {
|
|
regulator-name = "pm8010m_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x41d>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldom7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldom7";
|
|
|
|
regulator-pm8010m-l7 {
|
|
regulator-name = "pm8010m_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2d2a80>;
|
|
regulator-max-microvolt = <0x2d2a80>;
|
|
qcom,init-voltage = <0x2d2a80>;
|
|
phandle = <0x41e>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon1 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon1";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010n-l1 {
|
|
regulator-name = "pm8010n_l1";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10d880>;
|
|
regulator-max-microvolt = <0x10d880>;
|
|
qcom,init-voltage = <0x10d880>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x41f>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon2 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon2";
|
|
qcom,regulator-type = "pmic5-ldo";
|
|
qcom,supported-modes = <0x02 0x04>;
|
|
qcom,mode-threshold-currents = <0x00 0x7530>;
|
|
|
|
regulator-pm8010n-l2 {
|
|
regulator-name = "pm8010n_l2";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x10d880>;
|
|
regulator-max-microvolt = <0x10d880>;
|
|
qcom,init-voltage = <0x10d880>;
|
|
qcom,init-mode = <0x04>;
|
|
phandle = <0x420>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon3 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon3";
|
|
|
|
regulator-pm8010n-l3 {
|
|
regulator-name = "pm8010n_l3";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x421>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon4 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon4";
|
|
|
|
regulator-pm8010n-l4 {
|
|
regulator-name = "pm8010n_l4";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x1b7740>;
|
|
regulator-max-microvolt = <0x1b7740>;
|
|
qcom,init-voltage = <0x1b7740>;
|
|
phandle = <0x422>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon5 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon5";
|
|
|
|
regulator-pm8010n-l5 {
|
|
regulator-name = "pm8010n_l5";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x423>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon6 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon6";
|
|
|
|
regulator-pm8010n-l6 {
|
|
regulator-name = "pm8010n_l6";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x2ab980>;
|
|
regulator-max-microvolt = <0x2ab980>;
|
|
qcom,init-voltage = <0x2ab980>;
|
|
phandle = <0x424>;
|
|
};
|
|
};
|
|
|
|
rpmh-regulator-ldon7 {
|
|
compatible = "qcom,rpmh-vrm-regulator";
|
|
qcom,resource-name = "ldon7";
|
|
|
|
regulator-pm8010n-l7 {
|
|
regulator-name = "pm8010n_l7";
|
|
qcom,set = <0x03>;
|
|
regulator-min-microvolt = <0x326a40>;
|
|
regulator-max-microvolt = <0x326a40>;
|
|
qcom,init-voltage = <0x326a40>;
|
|
phandle = <0x425>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rsc@adc8000 {
|
|
label = "cam_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xadc8000 0x1000 0xadc9000 0x1000 0xadca000 0x1000>;
|
|
reg-names = "drv-0\0drv-1\0drv-2";
|
|
qcom,drv-count = <0x03>;
|
|
qcom,hw-channel;
|
|
interrupts = <0x00 0x170 0x04 0x00 0x171 0x04 0x00 0x172 0x04>;
|
|
clocks = <0x3e 0x33>;
|
|
phandle = <0x426>;
|
|
|
|
drv@0 {
|
|
qcom,drv-id = <0x00>;
|
|
qcom,tcs-offset = <0x520>;
|
|
qcom,tcs-distance = <0x150>;
|
|
phandle = <0x427>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x2a>;
|
|
};
|
|
};
|
|
|
|
drv@1 {
|
|
qcom,drv-id = <0x01>;
|
|
qcom,tcs-offset = <0x520>;
|
|
qcom,tcs-distance = <0x150>;
|
|
phandle = <0x428>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x2b>;
|
|
};
|
|
};
|
|
|
|
drv@2 {
|
|
qcom,drv-id = <0x02>;
|
|
qcom,tcs-offset = <0x520>;
|
|
qcom,tcs-distance = <0x150>;
|
|
phandle = <0x429>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
channel@1 {
|
|
qcom,tcs-config = <0x02 0x00 0x01 0x01 0x00 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
|
|
bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,no-amc;
|
|
phandle = <0x2c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x1000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <0x01>;
|
|
interrupts = <0x00 0x81 0x04>;
|
|
clocks = <0x3f 0x4c>;
|
|
phandle = <0x42a>;
|
|
|
|
drv@0 {
|
|
qcom,drv-id = <0x00>;
|
|
qcom,tcs-offset = <0x520>;
|
|
qcom,tcs-distance = <0x150>;
|
|
phandle = <0x42b>;
|
|
|
|
channel@0 {
|
|
qcom,tcs-config = <0x02 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x04 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
crm@af21000 {
|
|
label = "disp_crm";
|
|
compatible = "qcom,disp-crm-v2";
|
|
reg = <0xaf21000 0x6000 0xaf27000 0x400 0xaf27400 0x400 0xaf27800 0x2000 0xaf29800 0x700 0xaf29f00 0x100>;
|
|
reg-names = "base\0crm_b\0crm_b_pt\0crm_c\0crm_v\0common";
|
|
interrupts = <0x00 0x2bf 0x01 0x00 0x2c4 0x01 0x00 0x2ca 0x01 0x00 0x44 0x01 0x00 0x60 0x01 0x00 0xf9 0x01>;
|
|
interrupt-names = "disp_crm_drv0\0disp_crm_drv1\0disp_crm_drv2\0disp_crm_drv3\0disp_crm_drv4\0disp_crm_drv5";
|
|
clocks = <0x3f 0x06>;
|
|
qcom,hw-drv-ids = <0x00 0x01 0x02 0x03 0x04 0x05>;
|
|
qcom,sw-drv-ids = <0x00 0x02 0x03>;
|
|
phandle = <0x42c>;
|
|
};
|
|
|
|
crm@adcb000 {
|
|
label = "cam_crm";
|
|
compatible = "qcom,cam-crm-v2";
|
|
reg = <0xadcb000 0x1e00 0xadcce00 0x400 0xadcd200 0x400 0xadcd600 0x2000 0xadcf600 0x700 0xadcfd00 0x100>;
|
|
reg-names = "base\0crm_b\0crm_b_pt\0crm_c\0crm_v\0common";
|
|
interrupts = <0x00 0x79 0x01>;
|
|
interrupt-names = "cam_crm_drv0";
|
|
clocks = <0x3e 0x33>;
|
|
qcom,hw-drv-ids = <0x00 0x01 0x02>;
|
|
qcom,sw-drv-ids = <0x00>;
|
|
phandle = <0x42d>;
|
|
};
|
|
|
|
crm@1d01000 {
|
|
label = "pcie_crm";
|
|
compatible = "qcom,pcie-crm-v2";
|
|
reg = <0x1d01000 0x2000 0x1d03000 0x400 0x1d03400 0x400 0x1d03800 0x2000 0x1d05800 0x700 0x1d05f00 0x100>;
|
|
reg-names = "base\0crm_b\0crm_b_pt\0crm_c\0crm_v\0common";
|
|
interrupts = <0x00 0x281 0x01>;
|
|
interrupt-names = "pcie_crm_drv0";
|
|
clocks = <0x40>;
|
|
qcom,hw-drv-ids = <0x00 0x01>;
|
|
qcom,sw-drv-ids = <0x00>;
|
|
phandle = <0x42e>;
|
|
};
|
|
|
|
qcom,msm-imem@14680000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x14680000 0x1000>;
|
|
ranges = <0x00 0x14680000 0x1000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x08>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x04>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x04>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0x0c>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
pil@6dc {
|
|
compatible = "qcom,msm-imem-pil-disable-timeout";
|
|
reg = <0x6dc 0x04>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
|
|
modem_dsm@c98 {
|
|
compatible = "qcom,msm-imem-mss-dsm";
|
|
reg = <0xc98 0x10>;
|
|
};
|
|
|
|
sys_dbg@af8 {
|
|
compatible = "qcom,msm-imem-gpu-dump-skip";
|
|
reg = <0xb0c 0x04>;
|
|
};
|
|
};
|
|
|
|
cluster-device0 {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <0x1a>;
|
|
qcom,pred-prem-cnt = <0x02>;
|
|
qcom,sample-invalid-time = <0x2625a00>;
|
|
};
|
|
|
|
cluster-device1 {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <0x1b>;
|
|
qcom,pred-prem-cnt = <0x02>;
|
|
qcom,sample-invalid-time = <0x2625a00>;
|
|
qcom,use-cluster-bias-timer;
|
|
};
|
|
|
|
cluster-device2 {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <0x1c>;
|
|
qcom,pred-prem-cnt = <0x02>;
|
|
qcom,sample-invalid-time = <0x2625a00>;
|
|
};
|
|
|
|
qcom,memshare {
|
|
compatible = "qcom,memshare";
|
|
|
|
qcom,client_1 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x00>;
|
|
qcom,client-id = <0x00>;
|
|
qcom,allocate-boot-time;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_2 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x00>;
|
|
qcom,client-id = <0x02>;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_3 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x500000>;
|
|
qcom,client-id = <0x01>;
|
|
qcom,allocate-on-request;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_qmc_dma {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x1000000>;
|
|
qcom,client-id = <0x05>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
memory-region = <0x41>;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_qmc_cma {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x400000>;
|
|
qcom,client-id = <0x06>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_ims_1 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x100000>;
|
|
qcom,client-id = <0x07>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_ims_2 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x100000>;
|
|
qcom,client-id = <0x08>;
|
|
qcom,allocate-on-request;
|
|
qcom,shared;
|
|
label = "modem";
|
|
};
|
|
};
|
|
|
|
remoteproc-spss@1880000 {
|
|
compatible = "qcom,sun-spss-pas";
|
|
ranges;
|
|
reg = <0x188101c 0x04 0x1881024 0x04 0x1881028 0x04 0x188103c 0x04 0x1881100 0x04 0x1882014 0x04>;
|
|
reg-names = "sp2soc_irq_status\0sp2soc_irq_clr\0sp2soc_irq_mask\0rmb_err\0rmb_general_purpose\0rmb_err_spare2";
|
|
interrupts = <0x00 0x160 0x01>;
|
|
cx-supply = <0x38>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
sensors-supply = <0x42>;
|
|
sensors-uV-uA = <0x124f80 0x186a0>;
|
|
clocks = <0x35 0x00>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
status = "ok";
|
|
qcom,qmp = <0x19>;
|
|
memory-region = <0x43>;
|
|
qcom,spss-scsr-bits = <0x18 0x19>;
|
|
qcom,extra-size = <0x1000>;
|
|
interconnects = <0x44 0x29 0x45 0x201>;
|
|
interconnect-names = "crypto_ddr";
|
|
phandle = <0x46>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x08>;
|
|
mboxes = <0x21 0x10 0x00>;
|
|
mbox-names = "spss_spss";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x10 0x00 0x01>;
|
|
reg = <0x1885008 0x08 0x1885010 0x04>;
|
|
reg-names = "qcom,spss-addr\0qcom,spss-size";
|
|
label = "spss";
|
|
qcom,glink-label = "spss";
|
|
};
|
|
};
|
|
|
|
qcom,spcom {
|
|
compatible = "qcom,spcom";
|
|
qcom,rproc-handle = <0x46>;
|
|
qcom,boot-enabled;
|
|
qcom,spcom-ch-names = "sp_kernel\0sp_ssr";
|
|
qcom,spcom-sp2soc-rmb-reg-addr = <0x1881020>;
|
|
qcom,spcom-sp2soc-rmb-initdone-bit = <0x18>;
|
|
qcom,spcom-sp2soc-rmb-pbldone-bit = <0x19>;
|
|
qcom,spcom-soc2sp-rmb-reg-addr = <0x1881030>;
|
|
qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0x00>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,spss_utils {
|
|
compatible = "qcom,spss-utils";
|
|
qcom,rproc-handle = <0x46>;
|
|
qcom,spss-fuse1-addr = <0x221c8214>;
|
|
qcom,spss-fuse1-bit = <0x08>;
|
|
qcom,spss-fuse2-addr = <0x221c8214>;
|
|
qcom,spss-fuse2-bit = <0x07>;
|
|
qcom,spss-dev-firmware-name = "spss1d.mdt";
|
|
qcom,spss-test-firmware-name = "spss1t.mdt";
|
|
qcom,spss-prod-firmware-name = "spss1p.mdt";
|
|
qcom,spss-debug-reg-addr = <0x1886020>;
|
|
qcom,spss-debug-reg-addr1 = <0x1888020>;
|
|
qcom,spss-debug-reg-addr3 = <0x188c020>;
|
|
qcom,spss-emul-type-reg-addr = <0x1fc8004>;
|
|
pil-mem = <0x43>;
|
|
qcom,pil-size = <0xf0000>;
|
|
status = "ok";
|
|
phandle = <0x42f>;
|
|
};
|
|
|
|
clocks {
|
|
|
|
xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x493e000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x430>;
|
|
};
|
|
|
|
sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x7d00>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x40>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x4e>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0x3e8>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0x00>;
|
|
phandle = <0x4f>;
|
|
};
|
|
};
|
|
|
|
cpuss-sleep-stats@17850000 {
|
|
compatible = "qcom,cpuss-sleep-stats-v4";
|
|
reg = <0x17850000 0x4000>;
|
|
reg-names = "base";
|
|
};
|
|
|
|
ram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats-v4";
|
|
reg = <0xc3f0000 0x400>;
|
|
qcom,qmp = <0x19>;
|
|
qcom,rproc-handle = <0x47>;
|
|
ss-name = "modem\0adsp\0adsp_island\0cdsp\0apss";
|
|
};
|
|
|
|
qcom,cpufreq-thermal {
|
|
compatible = "qcom,cpufreq-thermal";
|
|
mboxes = <0x48 0x05 0x48 0x06>;
|
|
qcom,policy-cpus = <0x00 0x06>;
|
|
phandle = <0x431>;
|
|
};
|
|
|
|
clock-controller@1760000 {
|
|
compatible = "qcom,sun-cambistmclkcc\0syscon";
|
|
reg = <0x1760000 0x6000>;
|
|
reg-name = "cc_base";
|
|
vdd_mx-supply = <0x37>;
|
|
clocks = <0x35 0x00 0x49 0x34 0x05>;
|
|
clock-names = "bi_tcxo\0sleep_clk\0iface";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
syscon@0adcd600 {
|
|
compatible = "syscon";
|
|
reg = <0xadcd600 0x2000>;
|
|
phandle = <0x4a>;
|
|
};
|
|
|
|
clock-controller@ade0000 {
|
|
compatible = "qcom,sun-camcc\0syscon";
|
|
reg = <0xade0000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x39>;
|
|
vdd_mx-supply = <0x37>;
|
|
vdd_mxc-supply = <0x3b>;
|
|
clocks = <0x35 0x00 0x35 0x01 0x49 0x34 0x06>;
|
|
clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface";
|
|
qcom,cam_crm-crmc = <0x4a>;
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
syscon@af27800 {
|
|
compatible = "syscon";
|
|
reg = <0xaf27800 0x2000>;
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
clock-controller@af00000 {
|
|
compatible = "qcom,sun-dispcc\0syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x39>;
|
|
vdd_mx-supply = <0x37>;
|
|
clocks = <0x35 0x00 0x35 0x01 0x49 0x34 0x0f>;
|
|
clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface";
|
|
qcom,disp_crm-crmc = <0x4b>;
|
|
#clock-cells = <0x01>;
|
|
#power-domain-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x3f>;
|
|
|
|
clock-controller@af02000 {
|
|
compatible = "qcom,sun-dispcc_mx";
|
|
vdd_mxa-supply = <0x37>;
|
|
clocks = <0x35 0x00 0x49>;
|
|
clock-names = "bi_tcxo\0sleep_clk";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x432>;
|
|
};
|
|
};
|
|
|
|
clock-controller@abf0000 {
|
|
compatible = "qcom,sun-evacc\0syscon";
|
|
reg = <0xabf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x39>;
|
|
vdd_mxc-supply = <0x3b>;
|
|
clocks = <0x35 0x00 0x35 0x01 0x49 0x34 0x11>;
|
|
clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
clock-controller@100000 {
|
|
compatible = "qcom,sun-gcc\0syscon";
|
|
reg = <0x100000 0x1f4200>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <0x38>;
|
|
vdd_mx-supply = <0x37>;
|
|
clocks = <0x35 0x00 0x40 0x49 0x4c 0x4d 0x4e 0x4f>;
|
|
clock-names = "bi_tcxo\0pcie_0_pipe_clk\0sleep_clk\0ufs_phy_rx_symbol_0_clk\0ufs_phy_rx_symbol_1_clk\0ufs_phy_tx_symbol_0_clk\0usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
clock-controller@3d90000 {
|
|
compatible = "qcom,sun-gpucc\0syscon";
|
|
reg = <0x3d90000 0x9800>;
|
|
reg-name = "cc_base";
|
|
vdd_cx-supply = <0x38>;
|
|
vdd_mx-supply = <0x37>;
|
|
clocks = <0x35 0x00 0x34 0x23 0x34 0x24>;
|
|
clock-names = "bi_tcxo\0gpll0_out_main\0gpll0_out_main_div";
|
|
#clock-cells = <0x01>;
|
|
#power-domain-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x50>;
|
|
};
|
|
|
|
clock-controller@3d68024 {
|
|
compatible = "qcom,sun-gx_clkctl";
|
|
reg = <0x3d68024 0x08>;
|
|
reg-name = "cc_base";
|
|
power-domains = <0x50 0x00>;
|
|
vdd_gx-supply = <0x51>;
|
|
#power-domain-cells = <0x01>;
|
|
phandle = <0x59>;
|
|
};
|
|
|
|
clock-controller@f204008 {
|
|
compatible = "qcom,sun-tcsrcc\0syscon";
|
|
reg = <0xf204008 0x3004>;
|
|
reg-name = "cc_base";
|
|
#clock-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
clock-controller@aaf0000 {
|
|
compatible = "qcom,sun-videocc\0syscon";
|
|
reg = <0xaaf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <0x39>;
|
|
vdd_mxc-supply = <0x3b>;
|
|
vdd_mm_mxc_voter-supply = <0x52>;
|
|
clocks = <0x35 0x00 0x35 0x01 0x49 0x34 0xa7>;
|
|
clock-names = "bi_tcxo\0bi_tcxo_ao\0sleep_clk\0iface";
|
|
#clock-cells = <0x01>;
|
|
#power-domain-cells = <0x01>;
|
|
#reset-cells = <0x01>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
syscon@16450000 {
|
|
compatible = "syscon";
|
|
reg = <0x16450000 0x7000>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
syscon@240ba000 {
|
|
compatible = "syscon";
|
|
reg = <0x240ba000 0x800>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
syscon@3d64000 {
|
|
compatible = "syscon";
|
|
reg = <0x3d64000 0x6000>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
qcom,cc-debug {
|
|
compatible = "qcom,sun-debugcc";
|
|
qcom,apsscc = <0x53>;
|
|
qcom,gcc = <0x34>;
|
|
qcom,gpucc = <0x50>;
|
|
qcom,gxclkctl = <0x54>;
|
|
qcom,videocc = <0x55>;
|
|
qcom,evacc = <0x56>;
|
|
qcom,dispcc = <0x3f>;
|
|
qcom,camcc = <0x3e>;
|
|
qcom,cambistmclkcc = <0x57>;
|
|
qcom,mccc = <0x58>;
|
|
clocks = <0x35 0x00 0x57 0x00 0x3e 0x00 0x3f 0x00 0x56 0x00 0x34 0x00 0x50 0x00 0x59 0x00 0x5a 0x00 0x55 0x00>;
|
|
clock-names = "xo_clk_src\0cambistmclkcc\0camcc\0dispcc\0evacc\0gcc\0gpucc\0gxclkctl\0tcsrcc\0videocc";
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x433>;
|
|
};
|
|
|
|
qcom,gdsc@adf017c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf017c 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
regulator-name = "cam_cc_ipe_0_gdsc";
|
|
parent-supply = <0x5b>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x434>;
|
|
};
|
|
|
|
qcom,gdsc@adf00c8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf00c8 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
regulator-name = "cam_cc_ofe_gdsc";
|
|
parent-supply = <0x5b>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x435>;
|
|
};
|
|
|
|
qcom,gdsc@adf1004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf1004 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
regulator-name = "cam_cc_tfe_0_gdsc";
|
|
parent-supply = <0x5b>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x436>;
|
|
};
|
|
|
|
qcom,gdsc@adf1084 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf1084 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
regulator-name = "cam_cc_tfe_1_gdsc";
|
|
parent-supply = <0x5b>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x437>;
|
|
};
|
|
|
|
qcom,gdsc@adf10ec {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf10ec 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
regulator-name = "cam_cc_tfe_2_gdsc";
|
|
parent-supply = <0x5b>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x438>;
|
|
};
|
|
|
|
qcom,gdsc@adf134c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xadf134c 0x04>;
|
|
clocks = <0x34 0x06>;
|
|
interconnects = <0x5c 0x0a 0x5c 0x22d>;
|
|
interconnect-names = "mmnoc";
|
|
regulator-name = "cam_cc_titan_top_gdsc";
|
|
parent-supply = <0x52>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
qcom,gdsc@af09000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf09000 0x04>;
|
|
clocks = <0x34 0x0f>;
|
|
regulator-name = "disp_cc_mdss_core_gdsc";
|
|
parent-supply = <0x39>;
|
|
proxy-supply = <0x5d>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
qcom,gdsc@af0b000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf0b000 0x04>;
|
|
clocks = <0x34 0x0f>;
|
|
regulator-name = "disp_cc_mdss_core_int2_gdsc";
|
|
parent-supply = <0x39>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x439>;
|
|
};
|
|
|
|
qcom,gdsc@abf8068 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf8068 0x04>;
|
|
clocks = <0x34 0x11>;
|
|
regulator-name = "eva_cc_mvs0_gdsc";
|
|
parent-supply = <0x5e>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x43a>;
|
|
};
|
|
|
|
qcom,gdsc@abf8034 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf8034 0x04>;
|
|
clocks = <0x34 0x11>;
|
|
regulator-name = "eva_cc_mvs0c_gdsc";
|
|
parent-supply = <0x52>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
syscon@15214c {
|
|
compatible = "syscon";
|
|
reg = <0x15214c 0x04>;
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16b004 0x04>;
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
|
parent-supply = <0x38>;
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0x5f 0x00>;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x43b>;
|
|
};
|
|
|
|
qcom,gdsc@16c000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16c000 0x04>;
|
|
regulator-name = "gcc_pcie_0_phy_gdsc";
|
|
parent-supply = <0x37>;
|
|
qcom,retain-regs;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,collapse-vote = <0x5f 0x02>;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x34e>;
|
|
};
|
|
|
|
qcom,gdsc@19e000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x19e000 0x04>;
|
|
regulator-name = "gcc_ufs_mem_phy_gdsc";
|
|
parent-supply = <0x37>;
|
|
proxy-supply = <0x60>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x177004 0x04>;
|
|
regulator-name = "gcc_ufs_phy_gdsc";
|
|
parent-supply = <0x38>;
|
|
proxy-supply = <0x61>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
qcom,gdsc@139004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x139004 0x04>;
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
|
proxy-supply = <0x62>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
qcom,gdsc@150018 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x150018 0x04>;
|
|
regulator-name = "gcc_usb3_phy_gdsc";
|
|
parent-supply = <0x37>;
|
|
proxy-supply = <0x63>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
syscon@3d99094 {
|
|
compatible = "syscon";
|
|
reg = <0x3d99094 0x04>;
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
qcom,gdsc@3d99080 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d99080 0x04>;
|
|
clocks = <0x34 0x21>;
|
|
regulator-name = "gpu_cc_cx_gdsc";
|
|
parent-supply = <0x38>;
|
|
proxy-supply = <0x64>;
|
|
hw-ctrl-addr = <0x65>;
|
|
qcom,proxy-consumer-enable;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
qcom,gdsc@3d68024 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d68024 0x04>;
|
|
clocks = <0x50 0x0e>;
|
|
regulator-name = "gx_clkctl_gx_gdsc";
|
|
parent-supply = <0x51>;
|
|
reg-supply = <0x64>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x43c>;
|
|
};
|
|
|
|
qcom,gdsc@aaf8068 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf8068 0x04>;
|
|
clocks = <0x34 0xa7>;
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
|
parent-supply = <0x66>;
|
|
qcom,retain-regs;
|
|
qcom,support-hw-trigger;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x43d>;
|
|
};
|
|
|
|
qcom,gdsc@aaf8034 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaaf8034 0x04>;
|
|
clocks = <0x34 0xa7>;
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
|
parent-supply = <0x52>;
|
|
qcom,retain-regs;
|
|
qcom,support-cfg-gdscr;
|
|
status = "disabled";
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
google,debug-kinfo {
|
|
compatible = "google,debug-kinfo";
|
|
memory-region = <0x67>;
|
|
};
|
|
|
|
mini_dump_mode {
|
|
compatible = "qcom,minidump";
|
|
status = "ok";
|
|
};
|
|
|
|
va_mini_dump {
|
|
compatible = "qcom,va-minidump";
|
|
memory-region = <0x68>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom_ramoops {
|
|
compatible = "qcom,ramoops";
|
|
memory-region = <0x69>;
|
|
pmsg-size = <0x200000>;
|
|
mem-type = <0x02>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <0x8000>;
|
|
};
|
|
|
|
trust_ui_vm_vblk0_ring {
|
|
size = <0x4000>;
|
|
gunyah-label = <0x11>;
|
|
phandle = <0x6a>;
|
|
};
|
|
|
|
trust_ui_vm_vblk1_ring {
|
|
size = <0x4000>;
|
|
gunyah-label = <0x10>;
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
trust_ui_vm_vsock_ring {
|
|
size = <0xc000>;
|
|
gunyah-label = <0x15>;
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
trust_ui_vm_swiotlb {
|
|
size = <0x400000>;
|
|
gunyah-label = <0x12>;
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
qcom,trust_ui_vm {
|
|
vm_name = "trustedvm";
|
|
shared-buffers-size = "\0A@";
|
|
shared-buffers = <0x6a 0x6b 0x6c 0x6d>;
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
trust_ui_vm_virt_be0@11 {
|
|
qcom,vm = <0x6e>;
|
|
qcom,label = <0x11>;
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
trust_ui_vm_virt_be1@10 {
|
|
qcom,vm = <0x6e>;
|
|
qcom,label = <0x10>;
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
trust_ui_vm_virt_be2@15 {
|
|
qcom,vm = <0x6e>;
|
|
qcom,label = <0x15>;
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
gh-rm-booster {
|
|
compatible = "qcom,gh-rm-booster";
|
|
qcom,rm-vmid = <0xff>;
|
|
qcom,rm-affinity-default = <0x00>;
|
|
};
|
|
|
|
gh-secure-vm-loader@0 {
|
|
compatible = "qcom,gh-secure-vm-loader";
|
|
qcom,pas-id = <0x1c>;
|
|
qcom,vmid = <0x2d>;
|
|
qcom,firmware-name = "trustedvm";
|
|
qcom,keep-running;
|
|
memory-region = <0x6f 0x70>;
|
|
virtio-backends = <0x71 0x72 0x73>;
|
|
};
|
|
|
|
ufsphy_mem@1d80000 {
|
|
reg = <0x1d80000 0x2000>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0x00>;
|
|
lanes-per-direction = <0x02>;
|
|
clock-names = "ref_clk_src\0ref_aux_clk\0qref_clk\0rx_sym0_mux_clk\0rx_sym1_mux_clk\0tx_sym0_mux_clk\0rx_sym0_phy_clk\0rx_sym1_phy_clk\0tx_sym0_phy_clk";
|
|
clocks = <0x35 0x1b 0x34 0x90 0x5a 0x01 0x34 0x94 0x34 0x96 0x34 0x98 0x34 0x93 0x34 0x95 0x34 0x97>;
|
|
resets = <0x74 0x00>;
|
|
status = "disabled";
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
shared_ice {
|
|
phandle = <0x7b>;
|
|
|
|
alg1 {
|
|
alg-name = "alg1";
|
|
rx-alloc-percent = <0x3c>;
|
|
status = "disabled";
|
|
};
|
|
|
|
alg2 {
|
|
alg-name = "alg2";
|
|
status = "disabled";
|
|
};
|
|
|
|
alg3 {
|
|
alg-name = "alg3";
|
|
num-core = <0x1c 0x1c 0x0f 0x0d>;
|
|
status = "ok";
|
|
};
|
|
};
|
|
|
|
qcedev@1de0000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x1de0000 0x20000 0x1dc4000 0x28000>;
|
|
reg-names = "crypto-base\0crypto-bam-base";
|
|
interrupts = <0x00 0x110 0x04>;
|
|
qcom,bam-pipe-pair = <0x02>;
|
|
qcom,offload-ops-support;
|
|
qcom,bam-pipe-offload-cpb-hlos = <0x01>;
|
|
qcom,bam-pipe-offload-hlos-cpb = <0x03>;
|
|
qcom,bam-pipe-offload-hlos-cpb-1 = <0x08>;
|
|
qcom,bam-pipe-offload-hlos-hlos = <0x04>;
|
|
qcom,bam-pipe-offload-hlos-hlos-1 = <0x09>;
|
|
qcom,ce-hw-instance = <0x00>;
|
|
qcom,ce-device = <0x00>;
|
|
qcom,ce-hw-shared;
|
|
qcom,bam-ee = <0x00>;
|
|
qcom,smmu-s1-enable;
|
|
qcom,no-clock-support;
|
|
qcom,no-clk-gating;
|
|
interconnect-names = "data_path";
|
|
interconnects = <0x44 0x29 0x45 0x201>;
|
|
iommus = <0x75 0x480 0x00 0x75 0x481 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
dma-coherent;
|
|
phandle = <0x43e>;
|
|
|
|
qcom_cedev_ns_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "ns_context";
|
|
iommus = <0x75 0x481 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom_cedev_s_cb {
|
|
compatible = "qcom,qcedev,context-bank";
|
|
label = "secure_context";
|
|
iommus = <0x75 0x483 0x00>;
|
|
qcom,iommu-vmid = <0x09>;
|
|
qcom,secure-context-bank;
|
|
dma-noncoherent;
|
|
};
|
|
};
|
|
|
|
rng@10c3000 {
|
|
compatible = "qcom,trng";
|
|
reg = <0x10c3000 0x1000>;
|
|
phandle = <0x43f>;
|
|
};
|
|
|
|
ufshc_dma_resv_region {
|
|
iommu-addresses = <0x74 0x00 0x1000>;
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000 0x1d88000 0x18000 0x1da5000 0x2000 0x1da4000 0x10>;
|
|
reg-names = "ufs_mem\0ice\0mcq_sqd\0mcq_vs";
|
|
interrupts = <0x00 0x109 0x04>;
|
|
phys = <0x76>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <0x01>;
|
|
qcom,ice-use-hwkm;
|
|
qcom,prime-mask = <0xc0>;
|
|
qcom,silver-mask = <0x3f>;
|
|
qcom,esi-affinity-mask = <0x04 0x05 0x03 0x04 0x05 0x03 0x07 0x07>;
|
|
lanes-per-direction = <0x02>;
|
|
dev-ref-clk-freq = <0x00>;
|
|
clock-names = "core_clk\0bus_aggr_clk\0iface_clk\0core_clk_unipro\0core_clk_ice\0ref_clk\0tx_lane0_sync_clk\0rx_lane0_sync_clk\0rx_lane1_sync_clk";
|
|
clocks = <0x34 0x8a 0x34 0x01 0x34 0x89 0x34 0x99 0x34 0x8d 0x35 0x04 0x34 0x97 0x34 0x93 0x34 0x95>;
|
|
freq-table-hz = <0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x5f5e100 0x18054ac0 0x5f5e100 0x18054ac0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
interconnects = <0x77 0x34 0x45 0x201 0x78 0x02 0x79 0x220>;
|
|
interconnect-names = "ufs-ddr\0cpu-ufs";
|
|
depends-on-supply = <0x75>;
|
|
iommus = <0x75 0x60 0x00>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-msi-size = <0x1000>;
|
|
memory-region = <0x7a>;
|
|
shared-ice-cfg = <0x7b>;
|
|
dma-coherent;
|
|
qcom,bypass-pbl-rst-wa;
|
|
qcom,max-cpus = <0x08>;
|
|
msi-parent = <0x7c 0x60>;
|
|
status = "disabled";
|
|
phandle = <0x74>;
|
|
|
|
qos0 {
|
|
mask = <0xc0>;
|
|
vote = <0x2c>;
|
|
perf;
|
|
cpu_freq_vote = <0x06>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x3f>;
|
|
vote = <0x2c>;
|
|
cpu_freq_vote = <0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
sdhc2-opp-table {
|
|
compatible = "operating-points-v2";
|
|
phandle = <0x7f>;
|
|
|
|
opp-100000000 {
|
|
opp-hz = <0x00 0x5f5e100>;
|
|
opp-peak-kBps = <0x27100 0x186a0>;
|
|
opp-avg-kBps = <0xc350 0x00>;
|
|
};
|
|
|
|
opp-202000000 {
|
|
opp-hz = <0x00 0xc0a4680>;
|
|
opp-peak-kBps = <0x30d40 0x1d4c0>;
|
|
opp-avg-kBps = <0x19640 0x00>;
|
|
};
|
|
};
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x00 0x400000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x01>;
|
|
};
|
|
|
|
sdhc_2_dma_resv_region {
|
|
iommu-addresses = <0x7d 0x00 0x40000000 0x7d 0x50000000 0xb0000000>;
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
sdhci@8804000 {
|
|
status = "disabled";
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc";
|
|
interrupts = <0x00 0xcf 0x04 0x00 0xdf 0x04>;
|
|
interrupt-names = "hc_irq\0pwr_irq";
|
|
bus-width = <0x04>;
|
|
no-sdio;
|
|
no-mmc;
|
|
qcom,restore-after-cx-collapse;
|
|
clocks = <0x34 0x83 0x34 0x84>;
|
|
clock-names = "iface\0core";
|
|
qcom,dll-hsr-list = <0x7442c 0x00 0x10 0x294106c0 0x80040868>;
|
|
iommus = <0x75 0x540 0x00>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
memory-region = <0x7e>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
interconnects = <0x44 0x32 0x45 0x201 0x78 0x02 0x79 0x219>;
|
|
interconnect-names = "sdhc-ddr\0cpu-sdhc";
|
|
operating-points-v2 = <0x7f>;
|
|
phandle = <0x7d>;
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <0x2c>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <0x2c>;
|
|
};
|
|
};
|
|
|
|
cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <0x01 0x07 0x04>;
|
|
phandle = <0x440>;
|
|
};
|
|
|
|
qcom,kgsl-3d0@3d00000 {
|
|
nvmem-cell-names = "speed_bin";
|
|
nvmem-cells = <0x467>;
|
|
qcom,bus-table-ddr = <0x00 0xbebc2 0x209a8e 0x50a524 0x5caf6a 0x65ce03 0x7cb163 0xa3140c 0xbdf5c2 0xdbb3e5 0xfbc520 0x11bc718>;
|
|
qcom,bus-table-cnoc = <0x00 0x64>;
|
|
interconnect-names = "gpu_icc_path";
|
|
interconnects = <0x78 0x10 0x45 0x201>;
|
|
qcom,tzone-names = "gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7";
|
|
qcom,gpu-qdss-stm = <0x37000000 0x40000>;
|
|
qcom,ubwc-mode = <0x05>;
|
|
qcom,min-access-length = <0x20>;
|
|
qcom,chipid = <0x44050000>;
|
|
qcom,gpu-model = "Adreno830";
|
|
clock-names = "gcc_gpu_memnoc_gfx\0gpu_cc_ahb\0apb_pclk";
|
|
clocks = <0x34 0x22 0x50 0x00 0x19 0x00>;
|
|
interrupt-names = "kgsl_3d0_irq\0cx_host_irq";
|
|
interrupts = <0x00 0x12c 0x04 0x00 0x50 0x04>;
|
|
reg-names = "kgsl_3d0_reg_memory\0rscc\0cx_dbgc\0cx_misc\0qdss_gfx\0qdss_etr\0qdss_tmc";
|
|
reg = <0x3d00000 0x40000 0x3d50000 0x10000 0x3d61000 0x3000 0x3d9e000 0x2000 0x10900000 0x80000 0x10048000 0x8000 0x10b05000 0x1000>;
|
|
status = "ok";
|
|
compatible = "qcom,adreno-gpu-gen8-0-0\0qcom,kgsl-3d0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xd0>;
|
|
|
|
zap-shader {
|
|
memory-region = <0x367>;
|
|
};
|
|
|
|
qcom,gpu-mempools {
|
|
compatible = "qcom,gpu-mempools";
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-mempool@0 {
|
|
qcom,mempool-reserved = <0x800>;
|
|
qcom,mempool-page-size = <0x1000>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-mempool@1 {
|
|
qcom,mempool-reserved = <0x400>;
|
|
qcom,mempool-page-size = <0x2000>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-mempool@2 {
|
|
qcom,mempool-reserved = <0x100>;
|
|
qcom,mempool-page-size = <0x10000>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-mempool@3 {
|
|
qcom,mempool-reserved = <0x80>;
|
|
qcom,mempool-page-size = <0x20000>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-mempool@4 {
|
|
qcom,mempool-reserved = <0x50>;
|
|
qcom,mempool-page-size = <0x40000>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-mempool@5 {
|
|
qcom,mempool-reserved = <0x20>;
|
|
qcom,mempool-page-size = <0x100000>;
|
|
reg = <0x05>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevel-bins {
|
|
compatible = "qcom,gpu-pwrlevels-bins";
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevels-0 {
|
|
qcom,sku-codes = <0x02 0x03>;
|
|
qcom,initial-min-pwrlevel = <0x0a>;
|
|
qcom,initial-pwrlevel = <0x0a>;
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0b>;
|
|
qcom,bus-min = <0x0b>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,level = <0x140>;
|
|
qcom,gpu-freq = <0x35a4e900>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,level = <0x100>;
|
|
qcom,gpu-freq = <0x31975000>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,level = <0xe0>;
|
|
qcom,gpu-freq = <0x2e6e98c0>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
qcom,acd-level = <0xa82b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0xc0>;
|
|
qcom,gpu-freq = <0x2bbff380>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
qcom,acd-level = <0x882d5ffd>;
|
|
qcom,bus-max = <0x08>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x90>;
|
|
qcom,gpu-freq = <0x2756cd00>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
qcom,acd-level = <0xa82e5ffd>;
|
|
qcom,bus-max = <0x08>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x80>;
|
|
qcom,gpu-freq = <0x242e15c0>;
|
|
reg = <0x05>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
qcom,acd-level = <0xc0285ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x50>;
|
|
qcom,gpu-freq = <0x1f4add40>;
|
|
reg = <0x06>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
qcom,acd-level = <0xe02d5ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x40>;
|
|
qcom,gpu-freq = <0x1a67a4c0>;
|
|
reg = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
qcom,acd-level = <0xe02f5ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x3c>;
|
|
qcom,gpu-freq = <0x172fab40>;
|
|
reg = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@9 {
|
|
qcom,acd-level = <0xe8285ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x38>;
|
|
qcom,gpu-freq = <0x14628180>;
|
|
reg = <0x09>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@10 {
|
|
qcom,acd-level = <0xe82f5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0xd3b7380>;
|
|
reg = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@11 {
|
|
qcom,bus-max = <0x02>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x02>;
|
|
qcom,level = <0x32>;
|
|
qcom,gpu-freq = <0x7735940>;
|
|
reg = <0x0b>;
|
|
};
|
|
};
|
|
|
|
qcom,gpu-pwrlevels-1 {
|
|
qcom,sku-codes = <0x00>;
|
|
qcom,initial-min-pwrlevel = <0x0d>;
|
|
qcom,initial-pwrlevel = <0x0d>;
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
qcom,gpu-pwrlevel@0 {
|
|
qcom,acd-level = <0x88295ffd>;
|
|
qcom,bus-max = <0x0b>;
|
|
qcom,bus-min = <0x0b>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,level = <0x1c4>;
|
|
qcom,gpu-freq = <0x448b9b80>;
|
|
reg = <0x00>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@1 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x0b>;
|
|
qcom,bus-min = <0x0b>;
|
|
qcom,bus-freq = <0x0b>;
|
|
qcom,level = <0x1c0>;
|
|
qcom,gpu-freq = <0x3e95ba80>;
|
|
reg = <0x01>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@2 {
|
|
qcom,acd-level = <0x882a5ffd>;
|
|
qcom,bus-max = <0x0b>;
|
|
qcom,bus-min = <0x0a>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,level = <0x1a0>;
|
|
qcom,gpu-freq = <0x39a33fc0>;
|
|
reg = <0x02>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@3 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,level = <0x140>;
|
|
qcom,gpu-freq = <0x35a4e900>;
|
|
reg = <0x03>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@4 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x0a>;
|
|
qcom,level = <0x100>;
|
|
qcom,gpu-freq = <0x31975000>;
|
|
reg = <0x04>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@5 {
|
|
qcom,acd-level = <0x882b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x07>;
|
|
qcom,bus-freq = <0x09>;
|
|
qcom,level = <0xe0>;
|
|
qcom,gpu-freq = <0x2e6e98c0>;
|
|
reg = <0x05>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@6 {
|
|
qcom,acd-level = <0xa82b5ffd>;
|
|
qcom,bus-max = <0x0a>;
|
|
qcom,bus-min = <0x06>;
|
|
qcom,bus-freq = <0x08>;
|
|
qcom,level = <0xc0>;
|
|
qcom,gpu-freq = <0x2bbff380>;
|
|
reg = <0x06>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@7 {
|
|
qcom,acd-level = <0x882d5ffd>;
|
|
qcom,bus-max = <0x08>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x90>;
|
|
qcom,gpu-freq = <0x2756cd00>;
|
|
reg = <0x07>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@8 {
|
|
qcom,acd-level = <0xa82e5ffd>;
|
|
qcom,bus-max = <0x08>;
|
|
qcom,bus-min = <0x04>;
|
|
qcom,bus-freq = <0x06>;
|
|
qcom,level = <0x80>;
|
|
qcom,gpu-freq = <0x242e15c0>;
|
|
reg = <0x08>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@9 {
|
|
qcom,acd-level = <0xc0285ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x50>;
|
|
qcom,gpu-freq = <0x1f4add40>;
|
|
reg = <0x09>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@10 {
|
|
qcom,acd-level = <0xe02d5ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x40>;
|
|
qcom,gpu-freq = <0x1a67a4c0>;
|
|
reg = <0x0a>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@11 {
|
|
qcom,acd-level = <0xe02f5ffd>;
|
|
qcom,bus-max = <0x06>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x04>;
|
|
qcom,level = <0x3c>;
|
|
qcom,gpu-freq = <0x172fab40>;
|
|
reg = <0x0b>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@12 {
|
|
qcom,acd-level = <0xe8285ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x38>;
|
|
qcom,gpu-freq = <0x14628180>;
|
|
reg = <0x0c>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@13 {
|
|
qcom,acd-level = <0xe82f5ffd>;
|
|
qcom,bus-max = <0x03>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x03>;
|
|
qcom,level = <0x34>;
|
|
qcom,gpu-freq = <0xd3b7380>;
|
|
reg = <0x0d>;
|
|
};
|
|
|
|
qcom,gpu-pwrlevel@14 {
|
|
qcom,bus-max = <0x02>;
|
|
qcom,bus-min = <0x02>;
|
|
qcom,bus-freq = <0x02>;
|
|
qcom,level = <0x32>;
|
|
qcom,gpu-freq = <0x7735940>;
|
|
reg = <0x0e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,spmi@c42d000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc42d000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4c0000 0x10000>;
|
|
reg-names = "cnfg\0core\0chnls\0obsrvr\0intr";
|
|
interrupts-extended = <0x25 0x01 0x04>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
cell-index = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,bus-id = <0x00>;
|
|
phandle = <0x80>;
|
|
};
|
|
|
|
qcom,spmi@c432000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc432000 0x4000 0xc400000 0x3000 0xc500000 0x400000 0xc440000 0x80000 0xc4d0000 0x10000>;
|
|
reg-names = "cnfg\0core\0chnls\0obsrvr\0intr";
|
|
interrupts-extended = <0x25 0x03 0x04>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x04>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
cell-index = <0x00>;
|
|
qcom,channel = <0x00>;
|
|
qcom,ee = <0x00>;
|
|
qcom,bus-id = <0x01>;
|
|
depends-on-supply = <0x80>;
|
|
status = "disabled";
|
|
phandle = <0x441>;
|
|
};
|
|
|
|
spmi-debug@10b14000 {
|
|
compatible = "qcom,spmi-pmic-arb-debug";
|
|
reg = <0x10b14000 0x60 0x221c8784 0x04>;
|
|
reg-names = "core\0fuse";
|
|
clocks = <0x19>;
|
|
clock-names = "core_clk";
|
|
qcom,fuse-enable-bit = <0x12>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
depends-on-supply = <0x80>;
|
|
phandle = <0x442>;
|
|
|
|
pmk8550@0 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x00 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550@1 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x01 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550ve@3 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x03 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pmd802x@4 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x04 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550vs@5 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x05 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550ve@6 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x06 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550ve@8 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x08 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8550vs@9 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x09 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pmr735d@a {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0a 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8010@c {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0c 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
|
|
pm8010@d {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x0d 0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
qcom,can-sleep;
|
|
};
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <0x81>;
|
|
restrict-access;
|
|
};
|
|
|
|
adsp-sleepmon {
|
|
compatible = "qcom,adsp-sleepmon";
|
|
qcom,rproc-handle = <0x82>;
|
|
phandle = <0x443>;
|
|
};
|
|
|
|
remoteproc-adsp@03000000 {
|
|
compatible = "qcom,sun-adsp-pas";
|
|
reg = <0x3000000 0x10000>;
|
|
status = "ok";
|
|
cx-supply = <0x83>;
|
|
cx-uV-uA = <0x180 0x00>;
|
|
mx-supply = <0x84>;
|
|
mx-uV-uA = <0x180 0x00>;
|
|
reg-names = "cx\0mx";
|
|
clocks = <0x35 0x00>;
|
|
clock-names = "xo";
|
|
qcom,qmp = <0x19>;
|
|
interconnects = <0x85 0x14 0x45 0x201 0x44 0x29 0x45 0x201>;
|
|
interconnect-names = "rproc_ddr\0crypto_ddr";
|
|
firmware-name = "adsp.mdt\0adsp_dtb.mdt";
|
|
memory-region = <0x86 0x87>;
|
|
interrupts-extended = <0x25 0x06 0x01 0x88 0x00 0x00 0x88 0x02 0x00 0x88 0x01 0x00 0x88 0x03 0x00 0x88 0x07 0x00>;
|
|
interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack";
|
|
qcom,smem-states = <0x89 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0x82>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x02>;
|
|
transport = "smem";
|
|
mboxes = <0x21 0x03 0x00>;
|
|
mbox-names = "adsp_smem";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x03 0x00 0x01>;
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
phandle = <0x444>;
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,net-id = <0x02>;
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
qcom,no-wake-svc = <0x190>;
|
|
};
|
|
|
|
qcom,pmic_glink_rpmsg {
|
|
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
|
|
};
|
|
|
|
qcom,pmic_glink_log_rpmsg {
|
|
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
|
|
qcom,intents = <0x800 0x05 0xc00 0x03 0x2000 0x01>;
|
|
};
|
|
|
|
qcom,fastrpc {
|
|
qcom,vmids = <0x16 0x25>;
|
|
memory-region = <0x81>;
|
|
label = "adsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
compatible = "qcom,fastrpc";
|
|
|
|
compute-cb@1 {
|
|
pd-type = <0x01>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1003 0x80 0x75 0x1043 0x20>;
|
|
reg = <0x03>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@2 {
|
|
pd-type = <0x03>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,nsessions = <0x08>;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1004 0x80 0x75 0x1044 0x20>;
|
|
reg = <0x04>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@3 {
|
|
pd-type = <0x02>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1005 0x80 0x75 0x1045 0x20>;
|
|
reg = <0x05>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@4 {
|
|
pd-type = <0x05>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1006 0x80 0x75 0x1046 0x20>;
|
|
reg = <0x06>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@5 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1007 0x40 0x75 0x1067 0x00 0x75 0x1087 0x00>;
|
|
reg = <0x07>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@6 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1008 0x80 0x75 0x1048 0x20>;
|
|
reg = <0x08>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
};
|
|
|
|
qcom,gpr {
|
|
phandle = <0x59a>;
|
|
reg = <0x02>;
|
|
qcom,ch-sched-rt;
|
|
qcom,intents = <0x200 0x14>;
|
|
qcom,glink-channels = "adsp_apps";
|
|
compatible = "qcom,gpr";
|
|
|
|
spf_core {
|
|
reg = <0x03>;
|
|
compatible = "qcom,spf_core";
|
|
};
|
|
|
|
audio-pkt {
|
|
reg = <0x17>;
|
|
qcom,audiopkt-ch-name = "apr_audio_svc";
|
|
compatible = "qcom,audio-pkt";
|
|
};
|
|
|
|
q6prm {
|
|
phandle = <0x59b>;
|
|
reg = <0x07>;
|
|
qcom,sleep-api-supported = <0x01>;
|
|
compatible = "qcom,audio_prm";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc-mss@04080000 {
|
|
compatible = "qcom,sun-modem-pas";
|
|
reg = <0x4080000 0x10000>;
|
|
status = "ok";
|
|
clocks = <0x35 0x00>;
|
|
clock-names = "xo";
|
|
cx-supply = <0x38>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
mx-supply = <0x8a>;
|
|
mx-uV-uA = <0x140 0x186a0>;
|
|
reg-names = "cx\0mx";
|
|
qcom,qmp = <0x19>;
|
|
interconnects = <0x45 0x03 0x45 0x201 0x44 0x29 0x45 0x201>;
|
|
interconnect-names = "rproc_ddr\0crypto_ddr";
|
|
memory-region = <0x8b 0x8c 0x8d 0x8e 0x8f>;
|
|
firmware-name = "modem.mdt\0modem_dtb.mdt";
|
|
interrupts-extended = <0x01 0x00 0x108 0x01 0x90 0x00 0x00 0x90 0x02 0x00 0x90 0x01 0x00 0x90 0x03 0x00 0x90 0x07 0x00>;
|
|
interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack";
|
|
qcom,smem-states = <0x91 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0x445>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x01>;
|
|
transport = "smem";
|
|
mboxes = <0x21 0x02 0x00>;
|
|
mbox-names = "mpss_smem";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x02 0x00 0x01>;
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 0x02>;
|
|
};
|
|
};
|
|
};
|
|
|
|
remoteproc-cdsp@32300000 {
|
|
compatible = "qcom,sun-cdsp-pas";
|
|
reg = <0x32300000 0x10000>;
|
|
status = "ok";
|
|
cx-supply = <0x38>;
|
|
cx-uV-uA = <0x180 0x186a0>;
|
|
mx-supply = <0x3b>;
|
|
mx-uV-uA = <0x180 0x186a0>;
|
|
nsp-supply = <0x92>;
|
|
nsp-uV-uA = <0x180 0x186a0>;
|
|
reg-names = "cx\0mx\0nsp";
|
|
firmware-name = "cdsp.mdt\0cdsp_dtb.mdt";
|
|
memory-region = <0x93 0x94 0x95>;
|
|
clocks = <0x35 0x00>;
|
|
clock-names = "xo";
|
|
qcom,qmp = <0x19>;
|
|
interconnects = <0x96 0x19 0x45 0x201 0x44 0x29 0x45 0x201>;
|
|
interconnect-names = "rproc_ddr\0crypto_ddr";
|
|
interrupts-extended = <0x01 0x00 0x242 0x01 0x97 0x00 0x00 0x97 0x02 0x00 0x97 0x01 0x00 0x97 0x03 0x00 0x97 0x07 0x00>;
|
|
interrupt-names = "wdog\0fatal\0handover\0ready\0stop-ack\0shutdown-ack";
|
|
qcom,smem-states = <0x98 0x00>;
|
|
qcom,smem-state-names = "stop";
|
|
phandle = <0x47>;
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <0x05>;
|
|
transport = "smem";
|
|
mboxes = <0x21 0x06 0x00>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupt-parent = <0x21>;
|
|
interrupts = <0x06 0x00 0x01>;
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
phandle = <0x446>;
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 0x05 0x2000 0x03 0x4400 0x02>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 0x0c 0xf00 0x0c>;
|
|
|
|
qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-cores = <0x00 0x01>;
|
|
qcom,qos-latency-us = <0x46>;
|
|
qcom,qos-maxhold-ms = <0x14>;
|
|
phandle = <0x447>;
|
|
};
|
|
};
|
|
|
|
qcom,fastrpc {
|
|
qcom,single-core-latency-vote;
|
|
qcom,rpc-latency-us = <0xeb>;
|
|
qcom,fastrpc-gids = <0xb5c>;
|
|
label = "cdsp";
|
|
qcom,intents = <0x64 0x40>;
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
compatible = "qcom,fastrpc";
|
|
|
|
compute-cb@1 {
|
|
pd-type = <0x01>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x19c1 0x00 0x75 0xc21 0x00 0x75 0xc01 0x40>;
|
|
reg = <0x01>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@2 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1962 0x00 0x75 0xc02 0x20 0x75 0xc42 0x00 0x75 0x19c2 0x00>;
|
|
reg = <0x02>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@3 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1963 0x00 0x75 0xc23 0x00 0x75 0xc03 0x40 0x75 0x19c3 0x00>;
|
|
reg = <0x03>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@4 {
|
|
pd-type = <0x07>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1964 0x00 0x75 0xc24 0x00 0x75 0xc04 0x40 0x75 0x19c4 0x00>;
|
|
reg = <0x04>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@5 {
|
|
alloc-size-range = <0x4000000 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1965 0x00 0x75 0xc25 0x00 0x75 0xc05 0x40 0x75 0x19c5 0x00>;
|
|
reg = <0x05>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@6 {
|
|
alloc-size-range = <0x4000000 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1966 0x00 0x75 0xc06 0x20 0x75 0xc46 0x00 0x75 0x19c6 0x00>;
|
|
reg = <0x06>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@7 {
|
|
alloc-size-range = <0x1000000 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1967 0x00 0x75 0xc27 0x00 0x75 0xc07 0x40 0x75 0x19c7 0x00>;
|
|
reg = <0x07>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@8 {
|
|
alloc-size-range = <0x1000000 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1968 0x00 0x75 0xc08 0x20 0x75 0xc48 0x00 0x75 0x19c8 0x00>;
|
|
reg = <0x08>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@9 {
|
|
pd-type = <0x06>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,nsessions = <0x03>;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x1969 0x00 0x75 0xc29 0x00 0x75 0xc09 0x40 0x75 0x19c9 0x00>;
|
|
qcom,secure-context-bank;
|
|
reg = <0x09>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@10 {
|
|
alloc-size-range = <0x00 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x196c 0x00 0x75 0xc2c 0x00 0x75 0xc0c 0x40 0x75 0x19cc 0x00>;
|
|
reg = <0x0c>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@11 {
|
|
alloc-size-range = <0x00 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x196d 0x00 0x75 0xc0d 0x20 0x75 0xc2e 0x00 0x75 0xc4d 0x00 0x75 0x19cd 0x00>;
|
|
reg = <0x0d>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
|
|
compute-cb@12 {
|
|
alloc-size-range = <0x00 0xffffffff>;
|
|
pd-type = <0x09>;
|
|
qcom,iova-max-align-shift = <0x09>;
|
|
qcom,iova-best-fit;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0HUPCF";
|
|
iommus = <0x75 0x196e 0x00 0x75 0xc0e 0x40 0x75 0x19ce 0x00>;
|
|
reg = <0x0e>;
|
|
compatible = "qcom,fastrpc-compute-cb";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,pmic_glink {
|
|
compatible = "qcom,qti-pmic-glink";
|
|
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
|
|
qcom,subsys-name = "lpass";
|
|
qcom,protection-domain = "tms/servreg\0msm/adsp/charger_pd";
|
|
depends-on-supply = <0x21>;
|
|
|
|
qcom,battery_charger {
|
|
compatible = "qcom,battery-charger";
|
|
phandle = <0x448>;
|
|
};
|
|
|
|
qcom,ucsi {
|
|
compatible = "qcom,ucsi-glink";
|
|
phandle = <0x449>;
|
|
};
|
|
|
|
qcom,altmode {
|
|
compatible = "qcom,altmode-glink";
|
|
#altmode-cells = <0x01>;
|
|
phandle = <0x44a>;
|
|
};
|
|
};
|
|
|
|
qcom,pmic_glink_log {
|
|
compatible = "qcom,qti-pmic-glink";
|
|
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
|
|
|
|
qcom,battery_debug {
|
|
compatible = "qcom,battery-debug";
|
|
};
|
|
|
|
qcom,charger_ulog_glink {
|
|
compatible = "qcom,charger-ulog-glink";
|
|
};
|
|
|
|
qcom,pmic_glink_debug {
|
|
compatible = "qcom,pmic-glink-debug";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
depends-on-supply = <0x80>;
|
|
phandle = <0x44b>;
|
|
|
|
spmi@0 {
|
|
reg = <0x00>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
qcom,pmih010x-debug@7 {
|
|
compatible = "qcom,spmi-pmic";
|
|
reg = <0x07 0x00>;
|
|
qcom,can-sleep;
|
|
phandle = <0x44c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glink-adc {
|
|
compatible = "qcom,glink-adc";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
#io-channel-cells = <0x01>;
|
|
status = "disabled";
|
|
phandle = <0x44d>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
phandle = <0x44e>;
|
|
|
|
sdr0_pa {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x48>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdr0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x26>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x2e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x2f>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x30>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x31>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
mmw_ific0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x99 0x32>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config0 {
|
|
temperature = <0x1e848>;
|
|
hysteresis = <0x3e8>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu0-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
cpu0-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu000_cdev {
|
|
trip = <0x9b>;
|
|
cooling-device = <0x9c 0x01 0x01>;
|
|
};
|
|
|
|
cpu000_cdev1 {
|
|
trip = <0x9d>;
|
|
cooling-device = <0x9e 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu0-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
cpu0-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu001_cdev {
|
|
trip = <0x9f>;
|
|
cooling-device = <0x9c 0x01 0x01>;
|
|
};
|
|
|
|
cpu001_cdev1 {
|
|
trip = <0xa0>;
|
|
cooling-device = <0x9e 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu1-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
cpu1-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu010_cdev {
|
|
trip = <0xa1>;
|
|
cooling-device = <0xa2 0x01 0x01>;
|
|
};
|
|
|
|
cpu010_cdev1 {
|
|
trip = <0xa3>;
|
|
cooling-device = <0xa4 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu1-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
cpu1-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu011_cdev {
|
|
trip = <0xa5>;
|
|
cooling-device = <0xa2 0x01 0x01>;
|
|
};
|
|
|
|
cpu011_cdev1 {
|
|
trip = <0xa6>;
|
|
cooling-device = <0xa4 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
cpu2-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu020_cdev {
|
|
trip = <0xa7>;
|
|
cooling-device = <0xa8 0x01 0x01>;
|
|
};
|
|
|
|
cpu020_cdev1 {
|
|
trip = <0xa9>;
|
|
cooling-device = <0xaa 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu2-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
cpu2-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu021_cdev {
|
|
trip = <0xab>;
|
|
cooling-device = <0xa8 0x01 0x01>;
|
|
};
|
|
|
|
cpu021_cdev1 {
|
|
trip = <0xac>;
|
|
cooling-device = <0xaa 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
cpu3-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu030_cdev {
|
|
trip = <0xad>;
|
|
cooling-device = <0xae 0x01 0x01>;
|
|
};
|
|
|
|
cpu030_cdev1 {
|
|
trip = <0xaf>;
|
|
cooling-device = <0xb0 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu3-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xb1>;
|
|
};
|
|
|
|
cpu3-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu031_cdev {
|
|
trip = <0xb1>;
|
|
cooling-device = <0xae 0x01 0x01>;
|
|
};
|
|
|
|
cpu031_cdev1 {
|
|
trip = <0xb2>;
|
|
cooling-device = <0xb0 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-4-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
cpu4-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu040_cdev {
|
|
trip = <0xb3>;
|
|
cooling-device = <0xb4 0x01 0x01>;
|
|
};
|
|
|
|
cpu040_cdev1 {
|
|
trip = <0xb5>;
|
|
cooling-device = <0xb6 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-4-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu4-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
cpu4-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu041_cdev {
|
|
trip = <0xb7>;
|
|
cooling-device = <0xb4 0x01 0x01>;
|
|
};
|
|
|
|
cpu041_cdev1 {
|
|
trip = <0xb8>;
|
|
cooling-device = <0xb6 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-5-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xb9>;
|
|
};
|
|
|
|
cpu5-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu050_cdev {
|
|
trip = <0xb9>;
|
|
cooling-device = <0xba 0x01 0x01>;
|
|
};
|
|
|
|
cpu050_cdev1 {
|
|
trip = <0xbb>;
|
|
cooling-device = <0xbc 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-5-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu5-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
cpu5-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu051_cdev {
|
|
trip = <0xbd>;
|
|
cooling-device = <0xba 0x01 0x01>;
|
|
};
|
|
|
|
cpu051_cdev1 {
|
|
trip = <0xbe>;
|
|
cooling-device = <0xbc 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x0d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a 0x0e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
cpu6-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu100_cdev {
|
|
trip = <0xc0>;
|
|
cooling-device = <0xc1 0x01 0x01>;
|
|
};
|
|
|
|
cpu100_cdev1 {
|
|
trip = <0xc2>;
|
|
cooling-device = <0xc3 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu6-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
cpu6-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu101_cdev {
|
|
trip = <0xc4>;
|
|
cooling-device = <0xc1 0x01 0x01>;
|
|
};
|
|
|
|
cpu101_cdev1 {
|
|
trip = <0xc5>;
|
|
cooling-device = <0xc3 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7-emerg0-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
cpu7-emerg0-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu110_cdev {
|
|
trip = <0xc6>;
|
|
cooling-device = <0xc7 0x01 0x01>;
|
|
};
|
|
|
|
cpu110_cdev1 {
|
|
trip = <0xc8>;
|
|
cooling-device = <0xc9 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu7-emerg1-cfg {
|
|
temperature = <0x1a5e0>;
|
|
hysteresis = <0x1f40>;
|
|
type = "passive";
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
cpu7-emerg1-1-cfg {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x2710>;
|
|
type = "passive";
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
cpu111_cdev {
|
|
trip = <0xca>;
|
|
cooling-device = <0xc7 0x01 0x01>;
|
|
};
|
|
|
|
cpu111_cdev1 {
|
|
trip = <0xcb>;
|
|
cooling-device = <0xc9 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphvx-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsphmx-3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x0d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xbf 0x0e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
ddr0-config {
|
|
temperature = <0x15f90>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
ddr_cdev {
|
|
trip = <0xcc>;
|
|
cooling-device = <0xcd 0x01 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-2 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-0 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x01>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu0_cdev {
|
|
trip = <0xcf>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-1 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x02>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu1_cdev {
|
|
trip = <0xd1>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-2 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x03>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu2_cdev {
|
|
trip = <0xd2>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-3 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x04>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu3_cdev {
|
|
trip = <0xd3>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-4 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x05>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu4_cdev {
|
|
trip = <0xd4>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-5 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x06>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd5>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu5_cdev {
|
|
trip = <0xd5>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-6 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x07>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd6>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu6_cdev {
|
|
trip = <0xd6>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-7 {
|
|
polling-delay-passive = <0x04>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x08>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
tj_cfg {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0xd7>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
gpu7_cdev {
|
|
trip = <0xd7>;
|
|
cooling-device = <0xd0 0x00 0xffffffff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-0 {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x09>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss0-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xd8>;
|
|
};
|
|
|
|
mdmss0-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xdc>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0xd8>;
|
|
cooling-device = <0xd9 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0xd8>;
|
|
cooling-device = <0xda 0x64 0x64>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0xd8>;
|
|
cooling-device = <0xdb 0x0a 0x0a>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0xdc>;
|
|
cooling-device = <0xd9 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0xdc>;
|
|
cooling-device = <0xdb 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-1 {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0a>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss1-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xdd>;
|
|
};
|
|
|
|
mdmss1-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0xdd>;
|
|
cooling-device = <0xd9 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0xdd>;
|
|
cooling-device = <0xda 0x64 0x64>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0xdd>;
|
|
cooling-device = <0xdb 0x0a 0x0a>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0xde>;
|
|
cooling-device = <0xd9 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0xde>;
|
|
cooling-device = <0xdb 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-2 {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0b>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss2-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xdf>;
|
|
};
|
|
|
|
mdmss2-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xe0>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0xdf>;
|
|
cooling-device = <0xd9 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0xdf>;
|
|
cooling-device = <0xda 0x64 0x64>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0xdf>;
|
|
cooling-device = <0xdb 0x0a 0x0a>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0xe0>;
|
|
cooling-device = <0xd9 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0xe0>;
|
|
cooling-device = <0xdb 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdmss-3 {
|
|
polling-delay-passive = <0x64>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0c>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
thermal-hal-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
mdmss3-config0 {
|
|
temperature = <0x18e70>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xe1>;
|
|
};
|
|
|
|
mdmss3-config1 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0xbb8>;
|
|
type = "passive";
|
|
phandle = <0xe2>;
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
lte_cdev0 {
|
|
trip = <0xe1>;
|
|
cooling-device = <0xd9 0x08 0x08>;
|
|
};
|
|
|
|
nr_scg_cdev0 {
|
|
trip = <0xe1>;
|
|
cooling-device = <0xda 0x64 0x64>;
|
|
};
|
|
|
|
nr_cdev0 {
|
|
trip = <0xe1>;
|
|
cooling-device = <0xdb 0x0a 0x0a>;
|
|
};
|
|
|
|
lte_cdev2 {
|
|
trip = <0xe2>;
|
|
cooling-device = <0xd9 0xff 0xff>;
|
|
};
|
|
|
|
nr_cdev2 {
|
|
trip = <0xe2>;
|
|
cooling-device = <0xdb 0xff 0xff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-0 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0d>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
camera-1 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0e>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
video {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xce 0x0f>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-3 {
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0xe3 0x00>;
|
|
|
|
trips {
|
|
|
|
thermal-engine-config {
|
|
temperature = <0x20f58>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
};
|
|
|
|
reset-mon-cfg {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x00>;
|
|
type = "hot";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,test-dbl-tuivm {
|
|
compatible = "qcom,gh-dbl";
|
|
qcom,label = <0x04>;
|
|
};
|
|
|
|
qcom,test-dbl-oemvm {
|
|
compatible = "qcom,gh-dbl";
|
|
qcom,label = <0x05>;
|
|
};
|
|
|
|
qcom,test-msgq-tuivm {
|
|
compatible = "qcom,gh-msgq-test";
|
|
gunyah-label = <0x04>;
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,test-msgq-oemvm {
|
|
compatible = "qcom,gh-msgq-test";
|
|
gunyah-label = <0x05>;
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,test-large-dmabuf-tuivm {
|
|
compatible = "qcom,gh-large-dmabuf-test";
|
|
gunyah-label = <0x0d>;
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,test-large-dmabuf-oemvm {
|
|
compatible = "qcom,gh-large-dmabuf-test";
|
|
gunyah-label = <0x0e>;
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,gh-qtimer@1680b000 {
|
|
compatible = "qcom,gh-qtmr";
|
|
reg = <0x1680b000 0x1000>;
|
|
reg-names = "qtmr-base";
|
|
interrupts = <0x00 0x0d 0x04>;
|
|
interrupt-names = "qcom,qtmr-intr";
|
|
qcom,primary;
|
|
};
|
|
|
|
qcom,gunyah-panic-notifier {
|
|
compatible = "qcom,gh-panic-notifier";
|
|
qcom,primary-vm;
|
|
gunyah-label = <0x09>;
|
|
peer-name = <0x02>;
|
|
memory-region = <0x70>;
|
|
shared-buffer-size = <0x1000>;
|
|
};
|
|
|
|
dmesg-dump {
|
|
compatible = "qcom,dmesg-dump";
|
|
qcom,primary-vm;
|
|
gunyah-label = <0x07>;
|
|
peer-name = <0x02>;
|
|
memory-region = <0xe4>;
|
|
};
|
|
|
|
qcom,qrtr-gunyah-tuivm {
|
|
compatible = "qcom,qrtr-gunyah";
|
|
qcom,master;
|
|
gunyah-label = <0x03>;
|
|
peer-name = <0x02>;
|
|
};
|
|
|
|
mmio-sram@0x17b4e000 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
compatible = "mmio-sram";
|
|
reg = <0x00 0x17b4e000 0x00 0x400>;
|
|
ranges = <0x00 0x00 0x00 0x17b4e000 0x00 0x400>;
|
|
phandle = <0x44f>;
|
|
|
|
scmi-shmem@0 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x00 0x17b4e000 0x00 0x200>;
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
scmi-shmem@1 {
|
|
compatible = "arm,scmi-shmem";
|
|
reg = <0x00 0x17b4e200 0x00 0x200>;
|
|
phandle = <0xe6>;
|
|
};
|
|
};
|
|
|
|
qcom,cpucp@0x17830000 {
|
|
compatible = "qcom,cpucp-v2";
|
|
reg = <0x16430000 0x4c08 0x17830000 0x300>;
|
|
reg-names = "rx\0tx";
|
|
#mbox-cells = <0x01>;
|
|
interrupts = <0x00 0x1a 0x04>;
|
|
phandle = <0x48>;
|
|
};
|
|
|
|
qcom,pdp0@0x18980000 {
|
|
compatible = "qcom,cpucp-v2";
|
|
reg = <0x16420000 0x4c08 0x18980000 0x300>;
|
|
reg-names = "rx\0tx";
|
|
#mbox-cells = <0x01>;
|
|
interrupts = <0x00 0x20 0x04>;
|
|
qcom,rx-chans = <0x10>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
qcom,pdp1@0x19980000 {
|
|
compatible = "qcom,cpucp-v2";
|
|
reg = <0x16420000 0x4c08 0x19980000 0x300>;
|
|
reg-names = "rx\0tx";
|
|
#mbox-cells = <0x01>;
|
|
interrupts = <0x00 0x20 0x04>;
|
|
qcom,rx-chans = <0x20>;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
qcom,scmi {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
compatible = "arm,scmi";
|
|
mboxes = <0x48 0x00 0x48 0x02>;
|
|
mbox-names = "tx\0rx";
|
|
shmem = <0xe5 0xe6>;
|
|
phandle = <0x450>;
|
|
|
|
protocol@13 {
|
|
reg = <0x13>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x06>;
|
|
};
|
|
|
|
protocol@14 {
|
|
reg = <0x14>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x163>;
|
|
};
|
|
|
|
protocol@80 {
|
|
reg = <0x80>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x451>;
|
|
};
|
|
};
|
|
|
|
qcom,cpucp_fast {
|
|
compatible = "qcom,cpucp_fast";
|
|
mboxes = <0x48 0x07>;
|
|
qcom,policy-cpus = <0x06>;
|
|
phandle = <0x452>;
|
|
};
|
|
|
|
qcom,cpucp_log@0x81210000 {
|
|
compatible = "qcom,cpucp-log";
|
|
reg = <0x81210000 0x10000 0x81220000 0x10000>;
|
|
mboxes = <0x48 0x01>;
|
|
qcom,log-type = <0x00>;
|
|
phandle = <0x453>;
|
|
};
|
|
|
|
qcom,pdp0_log@0x81f41000 {
|
|
compatible = "qcom,pdp-log";
|
|
reg = <0x81f41000 0x10000 0x81f51000 0x10000>;
|
|
mboxes = <0xe7 0x04>;
|
|
qcom,log-type = <0x01>;
|
|
phandle = <0x454>;
|
|
};
|
|
|
|
qcom,pdp1_log@0x81f61000 {
|
|
compatible = "qcom,pdp-log";
|
|
reg = <0x81f61000 0x10000 0x81f71000 0x10000>;
|
|
mboxes = <0xe8 0x05 0xe8 0x04>;
|
|
qcom,log-type = <0x02>;
|
|
phandle = <0x455>;
|
|
};
|
|
|
|
qcom,mpam {
|
|
compatible = "qcom,mpam";
|
|
phandle = <0x456>;
|
|
};
|
|
|
|
qcom,cpu_mpam {
|
|
compatible = "qcom,cpu-mpam";
|
|
reg = <0x17b6f000 0x400>;
|
|
reg-names = "mon-base";
|
|
phandle = <0x457>;
|
|
|
|
L2_0 {
|
|
qcom,msc-id = <0x00>;
|
|
qcom,msc-name = "L2_0";
|
|
};
|
|
|
|
L2_1 {
|
|
qcom,msc-id = <0x01>;
|
|
qcom,msc-name = "L2_1";
|
|
};
|
|
};
|
|
|
|
qcom,noc_bw_mpam {
|
|
compatible = "qcom,platform-mpam";
|
|
reg = <0x17b6f400 0x400>;
|
|
reg-names = "mon-base";
|
|
qcom,msc-id = <0x03>;
|
|
qcom,msc-name = "noc_bw";
|
|
qcom,gears = "low\0medium\0high\0veryhigh";
|
|
qcom,gear-id = <0x01 0x02 0x03 0x04>;
|
|
phandle = <0x458>;
|
|
|
|
cpu_cluster0 {
|
|
qcom,client-id = <0x01>;
|
|
qcom,client-name = "cpu_cluster0";
|
|
};
|
|
|
|
cpu_cluster1 {
|
|
qcom,client-id = <0x02>;
|
|
qcom,client-name = "cpu_cluster1";
|
|
};
|
|
|
|
gpu {
|
|
qcom,client-id = <0x10>;
|
|
qcom,client-name = "gpu";
|
|
};
|
|
|
|
nsp {
|
|
qcom,client-id = <0x100>;
|
|
qcom,client-name = "nsp";
|
|
};
|
|
};
|
|
|
|
qcom-mpam-msc {
|
|
compatible = "qcom,mpam-msc";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
qcom-slc-mpam@17b6f800 {
|
|
compatible = "qcom,slc-mpam";
|
|
reg = <0x17b6f800 0x400>;
|
|
reg-names = "mon-base";
|
|
qcom,msc-id = <0x02>;
|
|
qcom,msc-name = "slc";
|
|
qcom,dev-index = <0x00>;
|
|
qcom,num-read-miss-cfg = <0x02>;
|
|
qcom,num-cap-cfg = <0x05>;
|
|
qcom,slc-clients = "APPS_CLIENT\0GPU_CLIENT\0NSP_CLIENT";
|
|
};
|
|
};
|
|
|
|
qcom,slc_mpam {
|
|
compatible = "qcom,mpam-slc";
|
|
qcom,msc-name = "slc";
|
|
phandle = <0x459>;
|
|
|
|
apps {
|
|
qcom,client-id = <0x00>;
|
|
qcom,client-name = "apps";
|
|
|
|
part-id0 {
|
|
qcom,part-id = <0x00>;
|
|
};
|
|
|
|
part-id1 {
|
|
qcom,part-id = <0x01>;
|
|
};
|
|
|
|
part-id2 {
|
|
qcom,part-id = <0x02>;
|
|
};
|
|
};
|
|
|
|
gpu {
|
|
qcom,client-id = <0x01>;
|
|
qcom,client-name = "gpu";
|
|
};
|
|
|
|
nsp {
|
|
qcom,client-id = <0x02>;
|
|
qcom,client-name = "nsp";
|
|
};
|
|
};
|
|
|
|
llcc-pmu@24095000 {
|
|
compatible = "qcom,llcc-pmu-ver2";
|
|
reg = <0x24095000 0x300>;
|
|
reg-names = "lagg-base";
|
|
qcom,idx-tbl = <0x02 0x03 0x04 0x05 0x06 0x07 0x00 0x01>;
|
|
phandle = <0x45a>;
|
|
};
|
|
|
|
qcom,pmu {
|
|
compatible = "qcom,pmu";
|
|
qcom,long-counter;
|
|
qcom,pmu-events-tbl = <0x08 0xff 0x02 0x02 0x11 0xff 0x01 0x00 0x17 0xff 0xff 0x04 0x1000 0xff 0xff 0x08>;
|
|
phandle = <0x45b>;
|
|
};
|
|
|
|
ddr-freq-table {
|
|
qcom,freq-tbl = <0x858b8 0x14a528 0x17ba38 0x1a0fe0 0x1febe0 0x29bf80 0x30a138 0x383e70 0x407400 0x48a5a8>;
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
llcc-freq-table {
|
|
qcom,freq-tbl = <0x55730 0x82208 0x927c0 0xc4c70 0xe3c88 0x104410 0x127a78>;
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
ddrqos-freq-table {
|
|
qcom,freq-tbl = <0x00 0x01>;
|
|
phandle = <0xec>;
|
|
};
|
|
|
|
qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
phandle = <0x45c>;
|
|
|
|
ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x00>;
|
|
qcom,bus-width = <0x04>;
|
|
qcom,freq-tbl = <0xe9>;
|
|
phandle = <0xed>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x45 0x03 0x45 0x201>;
|
|
phandle = <0x45d>;
|
|
};
|
|
|
|
fp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x01>;
|
|
qcom,fp-voter = <0xea>;
|
|
phandle = <0xee>;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x01>;
|
|
qcom,bus-width = <0x10>;
|
|
qcom,freq-tbl = <0xeb>;
|
|
phandle = <0xef>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x78 0x02 0x78 0x229>;
|
|
phandle = <0x45e>;
|
|
};
|
|
|
|
fp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x01>;
|
|
qcom,fp-voter = <0xea>;
|
|
phandle = <0xf0>;
|
|
};
|
|
};
|
|
|
|
ddrqos {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0x03>;
|
|
qcom,bus-width = <0x01>;
|
|
qcom,freq-tbl = <0xec>;
|
|
phandle = <0xf1>;
|
|
|
|
sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0x00>;
|
|
interconnects = <0x45 0x03 0x45 0x201>;
|
|
phandle = <0xf2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
phandle = <0x45f>;
|
|
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xed>;
|
|
qcom,sampling-path = <0xee>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x10 0x11 0x12 0x13 0x14 0x15>;
|
|
qcom,cpufreq-memfreq-tbl = <0xa8750 0x858b8 0xd6d80 0x14a528 0x144b50 0x17ba38 0x197b70 0x1febe0 0x22a330 0x30a138 0x275e20 0x383e70>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x94ed0 0x858b8 0xc8320 0x14a528 0x1b0210 0x1febe0 0x2143a0 0x30a138 0x2ab980 0x383e70 0x3567e0 0x407400 0x3cbae0 0x48a5a8>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x1e0f50 0x858b8 0x3cbae0 0x1febe0>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
|
|
prime-latfloor {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x2ab980 0x858b8 0x3cbae0 0x407400>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xef>;
|
|
qcom,sampling-path = <0xf0>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x10 0x11 0x12 0x13 0x14 0x15>;
|
|
qcom,cpufreq-memfreq-tbl = <0xd6d80 0x55730 0x197b70 0x82208 0x22a330 0xc4c70 0x275e20 0xe3c88>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0xc8320 0x55730 0x1b0210 0x82208 0x2143a0 0xc4c70 0x2ab980 0xe3c88 0x3567e0 0x104410 0x3cbae0 0x127a78>;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x1e0f50 0x55730 0x3cbae0 0x82208>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
ddrqos {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <0xf1>;
|
|
qcom,sampling-path = <0xf2>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x1e0f50 0x00 0x3cbae0 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x460>;
|
|
};
|
|
|
|
prime {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x1b0210 0x00 0x3cbae0 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x461>;
|
|
};
|
|
|
|
prime-latfloor {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <0x16 0x17>;
|
|
qcom,cpufreq-memfreq-tbl = <0x2143a0 0x00 0x3cbae0 0x01>;
|
|
qcom,sampling-enabled;
|
|
phandle = <0x462>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,llcc-ddr-vote {
|
|
qcom,target-dev = <0xed>;
|
|
qcom,secondary-map = <0x55730 0x858b8 0x82208 0x17ba38 0x927c0 0x1febe0 0xc4c70 0x30a138 0xe3c88 0x383e70 0x104410 0x407400 0x127a78 0x48a5a8>;
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
qcom,bwmon-llcc-gold@240B3300 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x240b3400 0x300 0x240b3300 0x200>;
|
|
reg-names = "base\0global_base";
|
|
interrupts = <0x00 0x245 0x04>;
|
|
qcom,map-ne;
|
|
qcom,mport = <0x00>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <0xef>;
|
|
qcom,second-vote = <0xf3>;
|
|
phandle = <0x463>;
|
|
};
|
|
|
|
qcom,bwmon-llcc-prime@240B7300 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x240b7400 0x300 0x240b7300 0x200>;
|
|
reg-names = "base\0global_base";
|
|
interrupts = <0x00 0x245 0x04>;
|
|
qcom,mport = <0x00>;
|
|
qcom,hw-timer-hz = <0x124f800>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <0xef>;
|
|
qcom,second-vote = <0xf3>;
|
|
phandle = <0x464>;
|
|
};
|
|
|
|
qcom,qrtr-gunyah-oemvm {
|
|
compatible = "qcom,qrtr-gunyah";
|
|
qcom,master;
|
|
gunyah-label = <0x08>;
|
|
peer-name = <0x04>;
|
|
};
|
|
|
|
qcom,qrtr-mhi-cnss {
|
|
compatible = "qcom,qrtr-mhi";
|
|
qcom,dev-id = <0x1107>;
|
|
qcom,net-id = <0x01>;
|
|
qcom,low-latency;
|
|
};
|
|
|
|
remoteproc-soccp@a3380000 {
|
|
compatible = "qcom,sun-soccp-pas";
|
|
reg = <0xa3380000 0x10000>;
|
|
status = "ok";
|
|
cx-supply = <0x38>;
|
|
cx-uV-uA = <0x40 0x00>;
|
|
mx-supply = <0x37>;
|
|
mx-uV-uA = <0x40 0x00>;
|
|
reg-names = "cx\0mx";
|
|
clocks = <0x35 0x00>;
|
|
clock-names = "xo";
|
|
interconnects = <0x44 0x2c 0x45 0x201 0xf4 0x23 0x45 0x201>;
|
|
interconnect-names = "rproc_ddr\0rproc_cnoc";
|
|
memory-region = <0xf5 0x00>;
|
|
soccp-tcsr = <0x02 0x1a000>;
|
|
soccp-spare = <0xda0024>;
|
|
interrupts-extended = <0x01 0x00 0xa7 0x01 0xf6 0x00 0x00 0xf6 0x01 0x00 0xf6 0x03 0x00 0xf6 0x02 0x00 0xf6 0x09 0x00>;
|
|
interrupt-names = "wdog\0fatal\0ready\0stop-ack\0handover\0pong";
|
|
qcom,smem-states = <0xf7 0x00 0xf7 0x0a 0xf7 0x09>;
|
|
qcom,smem-state-names = "stop\0wakeup\0sleep";
|
|
phandle = <0x465>;
|
|
};
|
|
|
|
qfprom@221c8000 {
|
|
compatible = "qcom,sun-qfprom\0qcom,qfprom";
|
|
reg = <0x221c8000 0x1000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
read-only;
|
|
ranges;
|
|
phandle = <0x466>;
|
|
|
|
gpu_speed_bin@138 {
|
|
reg = <0x138 0x02>;
|
|
bits = <0x00 0x09>;
|
|
phandle = <0x467>;
|
|
};
|
|
|
|
ssip_config@13e {
|
|
reg = <0x13e 0x02>;
|
|
bits = <0x07 0x02>;
|
|
phandle = <0x468>;
|
|
};
|
|
};
|
|
|
|
cnss_audio_iommu_group0 {
|
|
qcom,iommu-msi-size = <0x1000>;
|
|
qcom,iommu-geometry = <0x18000000 0x98010000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
qcom,iommu-pagetable = "coherent";
|
|
qcom,iommu-faults = "stall-disable\0HUPCF\0non-fatal";
|
|
phandle = <0x469>;
|
|
};
|
|
|
|
qcom,dma-heaps {
|
|
compatible = "qcom,dma-heaps";
|
|
depends-on-supply = <0xf8>;
|
|
|
|
qcom,display {
|
|
qcom,dma-heap-name = "qcom,display";
|
|
qcom,dma-heap-type = <0x02>;
|
|
qcom,max-align = <0x09>;
|
|
memory-region = <0xf9>;
|
|
};
|
|
|
|
qcom,qseecom {
|
|
qcom,dma-heap-name = "qcom,qseecom";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xfa>;
|
|
};
|
|
|
|
qcom,qseecom_ta {
|
|
qcom,dma-heap-name = "qcom,qseecom-ta";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xfb>;
|
|
};
|
|
|
|
qcom,sp_hlos {
|
|
qcom,dma-heap-name = "qcom,sp-hlos";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xfc>;
|
|
};
|
|
|
|
qcom,secure_sp_tz {
|
|
qcom,dma-heap-name = "qcom,secure-sp-tz";
|
|
qcom,dma-heap-type = <0x00>;
|
|
memory-region = <0xfd>;
|
|
qcom,token = <0x1000000>;
|
|
};
|
|
|
|
qcom,secure_sp_modem {
|
|
qcom,dma-heap-name = "qcom,secure-sp-modem";
|
|
qcom,dma-heap-type = <0x00>;
|
|
memory-region = <0xfe>;
|
|
qcom,token = <0x10800000>;
|
|
};
|
|
|
|
qcom,secure_cdsp {
|
|
qcom,dma-heap-name = "qcom,cma-secure-cdsp";
|
|
qcom,dma-heap-type = <0x02>;
|
|
memory-region = <0xff>;
|
|
};
|
|
};
|
|
|
|
tgu@10b0e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b0e000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x04>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-ipcb";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46a>;
|
|
};
|
|
|
|
tgu@10b0f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b0f000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x09>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-spmi0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46b>;
|
|
};
|
|
|
|
tgu@10b10000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb999>;
|
|
reg = <0x10b10000 0x1000>;
|
|
reg-names = "tgu-base";
|
|
tgu-steps = <0x03>;
|
|
tgu-conditions = <0x04>;
|
|
tgu-regs = <0x09>;
|
|
tgu-timer-counters = <0x08>;
|
|
coresight-name = "coresight-tgu-spmi1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46c>;
|
|
};
|
|
|
|
csr@10001000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x10001000 0x1000>;
|
|
reg-names = "csr-base";
|
|
coresight-name = "coresight-csr";
|
|
qcom,hwctrl-set-support;
|
|
qcom,set-byte-cntr-support;
|
|
qcom,blk-size = <0x01>;
|
|
phandle = <0x258>;
|
|
};
|
|
|
|
csr@10b11000 {
|
|
compatible = "qcom,coresight-csr";
|
|
reg = <0x10b11000 0x1000 0x10b110f8 0x78>;
|
|
reg-names = "csr-base\0msr-base";
|
|
coresight-name = "coresight-swao-csr";
|
|
qcom,timestamp-support;
|
|
qcom,msr-support;
|
|
qcom,blk-size = <0x01>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46d>;
|
|
};
|
|
|
|
tpdm@10900000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10900000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-gpu";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x105>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x100>;
|
|
phandle = <0x102>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10963000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10963000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-gfx";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "ok";
|
|
phandle = <0x46e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x101>;
|
|
phandle = <0x103>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#size-cells = <0x00>;
|
|
#address-cells = <0x01>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
phandle = <0x578>;
|
|
remote-endpoint = <0x579>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
phandle = <0x577>;
|
|
remote-endpoint = <0x57a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10902000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10902000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-gfx_dl";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x46f>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x102>;
|
|
phandle = <0x100>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x103>;
|
|
phandle = <0x101>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x104>;
|
|
source = <0x105>;
|
|
phandle = <0x107>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x106>;
|
|
phandle = <0x10a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10c38000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10c38000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-dlet";
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x470>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x107>;
|
|
phandle = <0x104>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x108>;
|
|
phandle = <0x109>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c39000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c39000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dlet";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x471>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x109>;
|
|
phandle = <0x108>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10a>;
|
|
phandle = <0x106>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10b>;
|
|
phandle = <0x21b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10830000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10830000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-video";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x472>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10c>;
|
|
phandle = <0x10d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10832000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10832000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-video";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x473>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10d>;
|
|
phandle = <0x10c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10e>;
|
|
phandle = <0x118>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109c0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-eva";
|
|
status = "disabled";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x474>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10f>;
|
|
phandle = <0x110>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@109c2000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x109c2000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-eva";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x475>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x110>;
|
|
phandle = <0x10f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x111>;
|
|
phandle = <0x119>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c60000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c60000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mdss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x476>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x112>;
|
|
phandle = <0x477>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c61000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c61000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mdss-rscc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x478>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x113>;
|
|
phandle = <0x115>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10c09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10c09000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-dlmm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x479>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x114>;
|
|
phandle = <0x112>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x115>;
|
|
phandle = <0x113>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x116>;
|
|
phandle = <0x11a>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x117>;
|
|
phandle = <0x11b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10c08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10c08000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-dlmm";
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20 0x03 0x20>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47a>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x118>;
|
|
phandle = <0x10e>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x119>;
|
|
phandle = <0x111>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11a>;
|
|
phandle = <0x47b>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11b>;
|
|
phandle = <0x117>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x112>;
|
|
phandle = <0x114>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10ba4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10ba4000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-soccp";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47c>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11c>;
|
|
phandle = <0x11d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
traceNoc@10ba0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x10ba0000 0x1000>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-tracenoc-soccp";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,interconnect-trace-noc;
|
|
phandle = <0x47d>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11d>;
|
|
phandle = <0x11c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11e>;
|
|
phandle = <0x22f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10980000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10980000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-turing";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x47e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11f>;
|
|
phandle = <0x124>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10981000 {
|
|
compatible = "qcom,coresight-static-tpdm";
|
|
coresight-name = "coresight-tpdm-turing-llm";
|
|
phandle = <0x47f>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x120>;
|
|
phandle = <0x125>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10982000 {
|
|
compatible = "qcom,coresight-static-tpdm";
|
|
coresight-name = "coresight-tpdm-turing-llm2";
|
|
phandle = <0x480>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x121>;
|
|
phandle = <0x126>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10983000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10983000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dpm1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x481>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x122>;
|
|
phandle = <0x127>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10984000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10984000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dpm2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x482>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x123>;
|
|
phandle = <0x128>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10986000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10986000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-turing";
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x01 0x20 0x02 0x20 0x03 0x40 0x04 0x40>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x483>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x124>;
|
|
phandle = <0x11f>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x125>;
|
|
phandle = <0x120>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x126>;
|
|
phandle = <0x121>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x127>;
|
|
phandle = <0x122>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x128>;
|
|
phandle = <0x123>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x129>;
|
|
phandle = <0x12e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
turing-etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-turing-etm0";
|
|
qcom,atid-num = <0x02>;
|
|
atid = <0x26 0x27>;
|
|
trace-name = "turing-etm0";
|
|
phandle = <0x484>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12a>;
|
|
phandle = <0x12c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12b>;
|
|
phandle = <0x25d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10940000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10940000 0x1000 0x10987000 0x1000>;
|
|
reg-names = "funnel-base-dummy\0funnel-base-real";
|
|
coresight-name = "coresight-funnel-turing_dup";
|
|
qcom,duplicate-funnel;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x485>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12c>;
|
|
phandle = <0x12a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12d>;
|
|
phandle = <0x12f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10987000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10987000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-turing";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x486>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12e>;
|
|
phandle = <0x129>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x12f>;
|
|
phandle = <0x12d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x130>;
|
|
phandle = <0x21c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10800000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10800000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-modem-0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x487>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x131>;
|
|
phandle = <0x139>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10801000 {
|
|
compatible = "qcom,coresight-static-tpdm";
|
|
coresight-name = "coresight-tpdm-modem-1";
|
|
phandle = <0x488>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x132>;
|
|
phandle = <0x13a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1080d000 {
|
|
compatible = "qcom,coresight-static-tpdm";
|
|
coresight-name = "coresight-tpdm-modem-rscc";
|
|
phandle = <0x489>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x133>;
|
|
phandle = <0x140>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem-etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-modem-etm0";
|
|
qcom,atid-num = <0x02>;
|
|
atid = <0x24 0x25>;
|
|
trace-name = "modem-etm0";
|
|
qcom,secure-component;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x134>;
|
|
phandle = <0x13c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x135>;
|
|
phandle = <0x264>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2-etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-modem2-etm0";
|
|
qcom,atid-num = <0x01>;
|
|
atid = <0x27>;
|
|
trace-name = "modem2-etm0";
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x136>;
|
|
phandle = <0x143>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x137>;
|
|
phandle = <0x266>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem_diag {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-modem-diag";
|
|
atid = <0x32>;
|
|
phandle = <0x48a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x138>;
|
|
phandle = <0x13f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10803000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10803000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-modem";
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48b>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x139>;
|
|
phandle = <0x131>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13a>;
|
|
phandle = <0x132>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13b>;
|
|
phandle = <0x142>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@1080d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x1080d000 0x1000 0x1080c000 0x1000>;
|
|
reg-names = "funnel-base-dummy\0funnel-base-real";
|
|
coresight-name = "coresight-funnel-modem_q6_dup";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,duplicate-funnel;
|
|
phandle = <0x48c>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13c>;
|
|
phandle = <0x134>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13d>;
|
|
phandle = <0x13e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@1080c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x1080c000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-modem_q6";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48d>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13e>;
|
|
phandle = <0x13d>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x13f>;
|
|
phandle = <0x138>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x140>;
|
|
phandle = <0x133>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x141>;
|
|
phandle = <0x144>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10804000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10804000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-modem_dl";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x48e>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x142>;
|
|
phandle = <0x13b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x143>;
|
|
phandle = <0x136>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x144>;
|
|
phandle = <0x141>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x145>;
|
|
phandle = <0x21a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc9000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc9000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-tmess-prng";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x48f>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x146>;
|
|
phandle = <0x149>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-tmess-0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,hw-enable-check;
|
|
status = "disabled";
|
|
phandle = <0x490>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x147>;
|
|
phandle = <0x14a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10cc1000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10cc1000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-tmess-1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,hw-enable-check;
|
|
phandle = <0x491>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x148>;
|
|
phandle = <0x14b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10cc4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10cc4000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-tmess";
|
|
qcom,dsb-elem-size = <0x00 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x40>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x492>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x149>;
|
|
phandle = <0x146>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14a>;
|
|
phandle = <0x147>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14b>;
|
|
phandle = <0x148>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14c>;
|
|
phandle = <0x14d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10cc5000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10cc5000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-tmess";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x493>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14d>;
|
|
phandle = <0x14c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14e>;
|
|
phandle = <0x219>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10a04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10a04000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-titan-dsb";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
static = "disabled";
|
|
phandle = <0x494>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x14f>;
|
|
phandle = <0x154>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10a0e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10a0e000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-titan-rscc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x495>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x150>;
|
|
phandle = <0x151>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10a0f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10a0f000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-titan";
|
|
qcom,cmb-elem-size = <0x00 0x40>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x496>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x151>;
|
|
phandle = <0x150>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x152>;
|
|
phandle = <0x153>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tn@0x10a00000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x10a00000 0x1000>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-tracenoc-titan";
|
|
status = "disabled";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,trace-noc-v2;
|
|
phandle = <0x497>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x153>;
|
|
phandle = <0x152>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x154>;
|
|
phandle = <0x14f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x155>;
|
|
phandle = <0x218>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10880000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10880000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-spss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x498>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x156>;
|
|
phandle = <0x157>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10883000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10883000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-spss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x499>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x157>;
|
|
phandle = <0x156>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x158>;
|
|
phandle = <0x217>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c70000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c70000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-pcie-rscc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x49a>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x159>;
|
|
phandle = <0x15a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10c71000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10c71000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-pcie-rscc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,cmb-elem-size = <0x00 0x08>;
|
|
phandle = <0x49b>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15a>;
|
|
phandle = <0x159>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15b>;
|
|
phandle = <0x216>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1084e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1084e000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mm-bcv";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49c>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15c>;
|
|
phandle = <0x15f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1084f00 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1084f000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mm-lmh";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49d>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15d>;
|
|
phandle = <0x160>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10850000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10850000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-mm-dpm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49e>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15e>;
|
|
phandle = <0x161>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10851000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10851000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-mm";
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x02 0x20>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x49f>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x15f>;
|
|
phandle = <0x15c>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x160>;
|
|
phandle = <0x15d>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x161>;
|
|
phandle = <0x15e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x162>;
|
|
phandle = <0x215>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218f000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-lmh0";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a0>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x164>;
|
|
phandle = <0x170>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12190000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12190000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-llm-lmh1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a1>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x165>;
|
|
phandle = <0x171>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218a000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext-dsb0";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x166>;
|
|
phandle = <0x172>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218b000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext-dsb1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x167>;
|
|
phandle = <0x173>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext-dsb2";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x168>;
|
|
phandle = <0x174>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218d000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext-dsb3";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a5>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x169>;
|
|
phandle = <0x175>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1218e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1218e000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext-dsb4";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a6>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16a>;
|
|
phandle = <0x176>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12181000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12181000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext_cmb0";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a7>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16b>;
|
|
phandle = <0x177>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12183000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12183000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext_cmb1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a8>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16c>;
|
|
phandle = <0x178>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12185000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12185000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext_cmb2";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4a9>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16d>;
|
|
phandle = <0x179>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12187000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12187000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ext_cmb3";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4aa>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16e>;
|
|
phandle = <0x17a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@12194000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x12194000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-int-cmb";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4ab>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x16f>;
|
|
phandle = <0x17b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@12196000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x12196000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-apss";
|
|
qcom,dsb-elem-size = <0x02 0x20 0x03 0x20 0x04 0x20 0x05 0x20 0x06 0x20 0x08 0x20>;
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20 0x07 0x40 0x08 0x40 0x09 0x40 0x0a 0x40 0x0b 0x40>;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4ac>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x170>;
|
|
phandle = <0x164>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x171>;
|
|
phandle = <0x165>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x172>;
|
|
phandle = <0x166>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x173>;
|
|
phandle = <0x167>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x174>;
|
|
phandle = <0x168>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x175>;
|
|
phandle = <0x169>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x176>;
|
|
phandle = <0x16a>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x177>;
|
|
phandle = <0x16b>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x178>;
|
|
phandle = <0x16c>;
|
|
};
|
|
};
|
|
|
|
port@9 {
|
|
reg = <0x09>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x179>;
|
|
phandle = <0x16d>;
|
|
};
|
|
};
|
|
|
|
port@a {
|
|
reg = <0x0a>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17a>;
|
|
phandle = <0x16e>;
|
|
};
|
|
};
|
|
|
|
port@b {
|
|
reg = <0x0b>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17b>;
|
|
phandle = <0x16f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17c>;
|
|
phandle = <0x1d5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@12c21000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x10>;
|
|
coresight-name = "coresight-etm0";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17d>;
|
|
phandle = <0x180>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm0 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core0";
|
|
cluster = <0x00>;
|
|
core = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17e>;
|
|
phandle = <0x181>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm0 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm0";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x17f>;
|
|
phandle = <0x182>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x180>;
|
|
phandle = <0x17d>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x181>;
|
|
phandle = <0x17e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@13490000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x13490000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr0_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4ad>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x182>;
|
|
phandle = <0x17f>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x183>;
|
|
phandle = <0x1a7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@12d21000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x11>;
|
|
coresight-name = "coresight-etm1";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x184>;
|
|
phandle = <0x187>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm1 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core1";
|
|
cluster = <0x00>;
|
|
core = <0x01>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x185>;
|
|
phandle = <0x188>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm1 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm1";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x186>;
|
|
phandle = <0x189>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x187>;
|
|
phandle = <0x184>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x188>;
|
|
phandle = <0x185>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@134a0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x134a0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr1_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4ae>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x189>;
|
|
phandle = <0x186>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18a>;
|
|
phandle = <0x1a8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@12e21000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x12>;
|
|
coresight-name = "coresight-etm2";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18b>;
|
|
phandle = <0x18e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm2 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core2";
|
|
cluster = <0x00>;
|
|
core = <0x02>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18c>;
|
|
phandle = <0x18f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm2 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm2";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18d>;
|
|
phandle = <0x190>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18e>;
|
|
phandle = <0x18b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x18f>;
|
|
phandle = <0x18c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@134b0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x134b0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr2_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4af>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x190>;
|
|
phandle = <0x18d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x191>;
|
|
phandle = <0x1a9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@12f21000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x13>;
|
|
coresight-name = "coresight-etm3";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x192>;
|
|
phandle = <0x195>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm3 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core3";
|
|
cluster = <0x00>;
|
|
core = <0x03>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x193>;
|
|
phandle = <0x196>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm3 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm3";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x194>;
|
|
phandle = <0x197>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x195>;
|
|
phandle = <0x192>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x196>;
|
|
phandle = <0x193>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@134c0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x134c0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr3_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b0>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x197>;
|
|
phandle = <0x194>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x198>;
|
|
phandle = <0x1aa>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13021000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x14>;
|
|
coresight-name = "coresight-etm4";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x199>;
|
|
phandle = <0x19c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm4 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core4";
|
|
cluster = <0x00>;
|
|
core = <0x04>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19a>;
|
|
phandle = <0x19d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm4 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm4";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19b>;
|
|
phandle = <0x19e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19c>;
|
|
phandle = <0x199>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19d>;
|
|
phandle = <0x19a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@134d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x134d0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr4_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b1>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19e>;
|
|
phandle = <0x19b>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x19f>;
|
|
phandle = <0x1ab>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13121000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x15>;
|
|
coresight-name = "coresight-etm5";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a0>;
|
|
phandle = <0x1a3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm5 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-core5";
|
|
cluster = <0x00>;
|
|
core = <0x05>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a1>;
|
|
phandle = <0x1a4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm5 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm5";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a2>;
|
|
phandle = <0x1a5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a3>;
|
|
phandle = <0x1a0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a4>;
|
|
phandle = <0x1a1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@134e0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x134e0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr5_ncc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b2>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a5>;
|
|
phandle = <0x1a2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a6>;
|
|
phandle = <0x1ac>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13481000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x13481000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ncc0_lv1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b3>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a7>;
|
|
phandle = <0x183>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a8>;
|
|
phandle = <0x18a>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1a9>;
|
|
phandle = <0x191>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1aa>;
|
|
phandle = <0x198>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ab>;
|
|
phandle = <0x19f>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ac>;
|
|
phandle = <0x1a6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ad>;
|
|
phandle = <0x1b4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uc_uetm0 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster0-uncore";
|
|
cluster = <0x00>;
|
|
qcom,uncore_uetm;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ae>;
|
|
phandle = <0x1af>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@13408000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x13408000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf-uc0";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b4>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1af>;
|
|
phandle = <0x1ae>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b0>;
|
|
phandle = <0x1b1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@1340a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x1340a000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-uc0";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b5>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b1>;
|
|
phandle = <0x1b0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b2>;
|
|
phandle = <0x1b3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13401000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x13401000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ncc0_lv2";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b6>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b3>;
|
|
phandle = <0x1b2>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b4>;
|
|
phandle = <0x1ad>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b5>;
|
|
phandle = <0x1b6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@13409000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x13409000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf_ncc0";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1a>;
|
|
phandle = <0x4b7>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b6>;
|
|
phandle = <0x1b5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b7>;
|
|
phandle = <0x1d3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13521000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x16>;
|
|
coresight-name = "coresight-etm6";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b8>;
|
|
phandle = <0x1bb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm6 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster1-core0";
|
|
cluster = <0x01>;
|
|
core = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1b9>;
|
|
phandle = <0x1bc>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm6 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm6";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ba>;
|
|
phandle = <0x1bd>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1bb>;
|
|
phandle = <0x1b8>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1bc>;
|
|
phandle = <0x1b9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@13d90000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x13d90000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr0_ncc1";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4b8>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1bd>;
|
|
phandle = <0x1ba>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1be>;
|
|
phandle = <0x1c6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@13621000 {
|
|
compatible = "arm,coresight-etm4x-sysreg";
|
|
cpu = <0x17>;
|
|
coresight-name = "coresight-etm7";
|
|
qcom,skip-power-up;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1bf>;
|
|
phandle = <0x1c2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uetm7 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster1-core1";
|
|
cluster = <0x01>;
|
|
core = <0x01>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c0>;
|
|
phandle = <0x1c3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel-etm7 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-etm7";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c1>;
|
|
phandle = <0x1c4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c2>;
|
|
phandle = <0x1bf>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c3>;
|
|
phandle = <0x1c0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@13da0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x13da0000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-etr1_ncc1";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4b9>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c4>;
|
|
phandle = <0x1c1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c5>;
|
|
phandle = <0x1c7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13d81000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x13d81000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ncc1_lv1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4ba>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c6>;
|
|
phandle = <0x1be>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c7>;
|
|
phandle = <0x1c5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c8>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uc_uetm1 {
|
|
compatible = "qcom,coresight-uetm";
|
|
coresight-name = "coresight-uetm-cluster1-uncore";
|
|
cluster = <0x01>;
|
|
qcom,uncore_uetm;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1c9>;
|
|
phandle = <0x1ca>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@13d08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x13d08000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf-uc1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4bb>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ca>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cb>;
|
|
phandle = <0x1cc>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@13d0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x13d0a000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator-uc1";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4bc>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cc>;
|
|
phandle = <0x1cb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cd>;
|
|
phandle = <0x1ce>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@13d01000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x13d01000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-ncc1_lv2";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
phandle = <0x4bd>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ce>;
|
|
phandle = <0x1cd>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1cf>;
|
|
phandle = <0x1c8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d0>;
|
|
phandle = <0x1d1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@13d09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x13d09000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf_ncc1";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
power-domains = <0x1b>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d1>;
|
|
phandle = <0x1d0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d2>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@12080000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x12080000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-apss";
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
phandle = <0x4be>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d3>;
|
|
phandle = <0x1b7>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d4>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d5>;
|
|
phandle = <0x17c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d6>;
|
|
phandle = <0x22c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b34000 {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-tpdm-ddr-lpi";
|
|
trace-name = "tracenoc-ddr-lpi";
|
|
phandle = <0x4bf>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d7>;
|
|
phandle = <0x244>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d8>;
|
|
phandle = <0x263>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10f80000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10f80000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-ubwcp";
|
|
status = "disabled";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c0>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1d9>;
|
|
phandle = <0x1e4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10f82000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10f82000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-llcc0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c1>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1da>;
|
|
phandle = <0x1e5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10f84000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10f84000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-llcc1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1db>;
|
|
phandle = <0x1e6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10f83000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10f83000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-llcc2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1dc>;
|
|
phandle = <0x1e7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10f85000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10f85000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-llcc3";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1dd>;
|
|
phandle = <0x1e8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d04000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-dpm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4c5>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1de>;
|
|
phandle = <0x1e9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d03000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d03000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-shrm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4c6>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1df>;
|
|
phandle = <0x1ea>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d06000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d06000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-ch02";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c7>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e0>;
|
|
phandle = <0x1eb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10d08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10d08000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ddr-ch13";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c8>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e1>;
|
|
phandle = <0x1ec>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
gladiator {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-gladiator";
|
|
atid = <0x60>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e2>;
|
|
phandle = <0x1e3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
TN@10d00000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x10d00000 0x1000>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-tracenoc-ddr";
|
|
qcom,interconnect-trace-noc;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4c9>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e3>;
|
|
phandle = <0x1e2>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e4>;
|
|
phandle = <0x1d9>;
|
|
};
|
|
};
|
|
|
|
port@9 {
|
|
reg = <0x09>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e5>;
|
|
phandle = <0x1da>;
|
|
};
|
|
};
|
|
|
|
port@a {
|
|
reg = <0x0a>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e6>;
|
|
phandle = <0x1db>;
|
|
};
|
|
};
|
|
|
|
port@b {
|
|
reg = <0x0b>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e7>;
|
|
phandle = <0x1dc>;
|
|
};
|
|
};
|
|
|
|
port@c {
|
|
reg = <0x0c>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e8>;
|
|
phandle = <0x1dd>;
|
|
};
|
|
};
|
|
|
|
port@d {
|
|
reg = <0x0d>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1e9>;
|
|
phandle = <0x1de>;
|
|
};
|
|
};
|
|
|
|
port@e {
|
|
reg = <0x0e>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ea>;
|
|
phandle = <0x1df>;
|
|
};
|
|
};
|
|
|
|
port@f {
|
|
reg = <0x0f>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1eb>;
|
|
phandle = <0x1e0>;
|
|
};
|
|
};
|
|
|
|
port@10 {
|
|
reg = <0x10>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ec>;
|
|
phandle = <0x1e1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ed>;
|
|
phandle = <0x22d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
audio_etm0 {
|
|
compatible = "qcom,coresight-remote-etm";
|
|
coresight-name = "coresight-audio-etm0";
|
|
qcom,atid-num = <0x02>;
|
|
trace-name = "audio-etm0";
|
|
atid = <0x28 0x29>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ee>;
|
|
phandle = <0x200>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ef>;
|
|
phandle = <0x25e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b46000 {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-tpdm-lpass-lpi";
|
|
trace-name = "tpda-lpass-lpi";
|
|
phandle = <0x4ca>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f0>;
|
|
phandle = <0x1fc>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f1>;
|
|
phandle = <0x260>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b52000 {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-tpdm-lpass-rscc";
|
|
trace-name = "tpda-lpass-rscc";
|
|
phandle = <0x4cb>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f2>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f3>;
|
|
phandle = <0x261>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b54000 {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-tpdm-lpass-audio";
|
|
trace-name = "tpda-lpass-audio";
|
|
status = "disabled";
|
|
phandle = <0x4cc>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f4>;
|
|
phandle = <0x1fe>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f5>;
|
|
phandle = <0x262>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10bb4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10bb4000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-lpass-crdl";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4cd>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f6>;
|
|
phandle = <0x1f7>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
TN@10b80000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x10b80000 0x3400>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-tracenoc-lpass";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,interconnect-trace-noc;
|
|
phandle = <0x4ce>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f7>;
|
|
phandle = <0x1f6>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f8>;
|
|
phandle = <0x22e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lpass-stm {
|
|
compatible = "arm,coresight-dummy-source";
|
|
coresight-name = "coresight-lpass-stm";
|
|
trace-name = "lpass-stm";
|
|
atid = <0x19>;
|
|
phandle = <0x4cf>;
|
|
|
|
out-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1f9>;
|
|
phandle = <0x1fb>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fa>;
|
|
phandle = <0x25f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b50000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-lpass_lpi_1";
|
|
phandle = <0x4d0>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fb>;
|
|
phandle = <0x1f9>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fc>;
|
|
phandle = <0x1f0>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fd>;
|
|
phandle = <0x1f2>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1fe>;
|
|
phandle = <0x1f4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x1ff>;
|
|
phandle = <0x201>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b44000 {
|
|
compatible = "arm,coresight-static-funnel";
|
|
coresight-name = "coresight-funnel-lpass_lpi_0";
|
|
phandle = <0x4d1>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x200>;
|
|
phandle = <0x1ee>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x201>;
|
|
phandle = <0x1ff>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x202>;
|
|
phandle = <0x245>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
stm@10002000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb962>;
|
|
reg = <0x10002000 0x1000 0x37280000 0x180000>;
|
|
reg-names = "stm-base\0stm-stimulus-base";
|
|
coresight-name = "coresight-stm";
|
|
atid = <0x10>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x203>;
|
|
phandle = <0x237>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10003000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10003000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dcc";
|
|
qcom,hw-enable-check;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x204>;
|
|
phandle = <0x232>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c23000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c23000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ufs";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4d4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x205>;
|
|
phandle = <0x223>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c21000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c21000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-sdcc4";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4d5>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x206>;
|
|
phandle = <0x222>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c20000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c20000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-sdcc2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4d6>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x207>;
|
|
phandle = <0x221>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10c22000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10c22000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ipa";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4d7>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x208>;
|
|
phandle = <0x220>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10840000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10840000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-vsense";
|
|
status = "disabled";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d8>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x209>;
|
|
phandle = <0x21f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109d0000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109d0000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-qm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4d9>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20a>;
|
|
phandle = <0x4da>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10841000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10841000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-prng";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4db>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20b>;
|
|
phandle = <0x21e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1082c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1082c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-gcc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4dc>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20c>;
|
|
phandle = <0x21d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a5000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a5000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-dlmm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4dd>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20d>;
|
|
phandle = <0x224>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a6000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a6000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-north-dsb";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4de>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20e>;
|
|
phandle = <0x225>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a7000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a7000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-south-dsb";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4df>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x20f>;
|
|
phandle = <0x226>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a4000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a4000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-ipcc";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e0>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x210>;
|
|
phandle = <0x227>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a3000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a3000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-pmu";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e1>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x211>;
|
|
phandle = <0x228>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a8000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a8000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-cmb0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4e2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x212>;
|
|
phandle = <0x229>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109a9000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109a9000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-cmb1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4e3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x213>;
|
|
phandle = <0x22a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@109aa000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x109aa000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-rdpm-cmb2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
phandle = <0x4e4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x214>;
|
|
phandle = <0x22b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tn@109ab000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xf0c00>;
|
|
reg = <0x109ab000 0x4200>;
|
|
reg-names = "traceNoc-base";
|
|
coresight-name = "coresight-tracenoc-ag";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,trace-noc-v2;
|
|
phandle = <0x4e5>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x215>;
|
|
phandle = <0x162>;
|
|
};
|
|
};
|
|
|
|
port@8 {
|
|
reg = <0x08>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x216>;
|
|
phandle = <0x15b>;
|
|
};
|
|
};
|
|
|
|
port@9 {
|
|
reg = <0x09>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x217>;
|
|
phandle = <0x158>;
|
|
};
|
|
};
|
|
|
|
port@b {
|
|
reg = <0x0b>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x218>;
|
|
phandle = <0x155>;
|
|
};
|
|
};
|
|
|
|
port@c {
|
|
reg = <0x0c>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x219>;
|
|
phandle = <0x14e>;
|
|
};
|
|
};
|
|
|
|
port@d {
|
|
reg = <0x0d>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21a>;
|
|
phandle = <0x145>;
|
|
};
|
|
};
|
|
|
|
port@e {
|
|
reg = <0x0e>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x11a>;
|
|
phandle = <0x116>;
|
|
};
|
|
};
|
|
|
|
port@f {
|
|
reg = <0x0f>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21b>;
|
|
phandle = <0x10b>;
|
|
};
|
|
};
|
|
|
|
port@10 {
|
|
reg = <0x10>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21c>;
|
|
phandle = <0x130>;
|
|
};
|
|
};
|
|
|
|
port@11 {
|
|
reg = <0x11>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21d>;
|
|
phandle = <0x20c>;
|
|
};
|
|
};
|
|
|
|
port@12 {
|
|
reg = <0x12>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21e>;
|
|
phandle = <0x20b>;
|
|
};
|
|
};
|
|
|
|
port@13 {
|
|
reg = <0x13>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21e>;
|
|
phandle = <0x20a>;
|
|
};
|
|
};
|
|
|
|
port@14 {
|
|
reg = <0x14>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x21f>;
|
|
phandle = <0x209>;
|
|
};
|
|
};
|
|
|
|
port@15 {
|
|
reg = <0x15>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x220>;
|
|
phandle = <0x208>;
|
|
};
|
|
};
|
|
|
|
port@16 {
|
|
reg = <0x16>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x221>;
|
|
phandle = <0x207>;
|
|
};
|
|
};
|
|
|
|
port@17 {
|
|
reg = <0x17>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x222>;
|
|
phandle = <0x206>;
|
|
};
|
|
};
|
|
|
|
port@18 {
|
|
reg = <0x18>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x223>;
|
|
phandle = <0x205>;
|
|
};
|
|
};
|
|
|
|
port@19 {
|
|
reg = <0x19>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x224>;
|
|
phandle = <0x20d>;
|
|
};
|
|
};
|
|
|
|
port@1a {
|
|
reg = <0x1a>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x225>;
|
|
phandle = <0x20e>;
|
|
};
|
|
};
|
|
|
|
port@1b {
|
|
reg = <0x1b>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x226>;
|
|
phandle = <0x20f>;
|
|
};
|
|
};
|
|
|
|
port@1c {
|
|
reg = <0x1c>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x227>;
|
|
phandle = <0x210>;
|
|
};
|
|
};
|
|
|
|
port@1d {
|
|
reg = <0x1d>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x228>;
|
|
phandle = <0x211>;
|
|
};
|
|
};
|
|
|
|
port@1e {
|
|
reg = <0x1e>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x229>;
|
|
phandle = <0x212>;
|
|
};
|
|
};
|
|
|
|
port@1f {
|
|
reg = <0x1f>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22a>;
|
|
phandle = <0x213>;
|
|
};
|
|
};
|
|
|
|
port@20 {
|
|
reg = <0x20>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22b>;
|
|
phandle = <0x214>;
|
|
};
|
|
};
|
|
|
|
port@21 {
|
|
reg = <0x21>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22c>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
};
|
|
|
|
port@22 {
|
|
reg = <0x22>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22d>;
|
|
phandle = <0x1ed>;
|
|
};
|
|
};
|
|
|
|
port@23 {
|
|
reg = <0x23>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22e>;
|
|
phandle = <0x1f8>;
|
|
};
|
|
};
|
|
|
|
port@24 {
|
|
reg = <0x24>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x22f>;
|
|
phandle = <0x11e>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x230>;
|
|
phandle = <0x235>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@1000f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x1000f000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-spdm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e6>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x231>;
|
|
phandle = <0x233>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10004000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10004000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-qdss";
|
|
qcom,cmb-elem-size = <0x00 0x20 0x01 0x20>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e7>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x232>;
|
|
phandle = <0x204>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x233>;
|
|
phandle = <0x231>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x234>;
|
|
phandle = <0x236>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10041000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10041000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-in0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e8>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x235>;
|
|
phandle = <0x230>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x236>;
|
|
phandle = <0x234>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x237>;
|
|
phandle = <0x203>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x238>;
|
|
phandle = <0x247>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b09000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b09000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4e9>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x239>;
|
|
phandle = <0x23e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0a000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0a000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ea>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23a>;
|
|
phandle = <0x23f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0b000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0b000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4eb>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23b>;
|
|
phandle = <0x240>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0c000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0c000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-prio-3";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ec>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23c>;
|
|
phandle = <0x241>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpdm@10b0d000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb968>;
|
|
reg = <0x10b0d000 0x1000>;
|
|
reg-names = "tpdm-base";
|
|
coresight-name = "coresight-tpdm-swao-1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ed>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23d>;
|
|
phandle = <0x242>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tpda@10b08000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb969>;
|
|
reg = <0x10b08000 0x1000>;
|
|
reg-names = "tpda-base";
|
|
coresight-name = "coresight-tpda-aoss";
|
|
qcom,cmb-elem-size = <0x00 0x40 0x01 0x40 0x02 0x40 0x03 0x40>;
|
|
qcom,dsb-elem-size = <0x04 0x20>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ee>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23e>;
|
|
phandle = <0x239>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x23f>;
|
|
phandle = <0x23a>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x240>;
|
|
phandle = <0x23b>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x241>;
|
|
phandle = <0x23c>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x242>;
|
|
phandle = <0x23d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x243>;
|
|
phandle = <0x246>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@10b04000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb908>;
|
|
reg = <0x10b04000 0x1000>;
|
|
reg-names = "funnel-base";
|
|
coresight-name = "coresight-funnel-aoss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4ef>;
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x244>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x245>;
|
|
phandle = <0x202>;
|
|
};
|
|
};
|
|
|
|
port@6 {
|
|
reg = <0x06>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x246>;
|
|
phandle = <0x243>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x247>;
|
|
phandle = <0x238>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x248>;
|
|
phandle = <0x249>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@10b05000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x10b05000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etf";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f0>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x249>;
|
|
phandle = <0x248>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24a>;
|
|
phandle = <0x24b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@10b06000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x10b06000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_swao";
|
|
qcom,replicator-loses-context;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f1>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24b>;
|
|
phandle = <0x24a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24c>;
|
|
phandle = <0x24f>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24d>;
|
|
phandle = <0x24e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
dummy-eud {
|
|
compatible = "arm,coresight-dummy-sink";
|
|
coresight-name = "coresight-eud";
|
|
phandle = <0x4f2>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24e>;
|
|
phandle = <0x24d>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@10046000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x10046000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_qdss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f3>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x24f>;
|
|
phandle = <0x24c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x250>;
|
|
phandle = <0x251>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
replicator@1004e000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb909>;
|
|
reg = <0x1004e000 0x1000>;
|
|
reg-names = "replicator-base";
|
|
coresight-name = "coresight-replicator_etr";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f4>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x251>;
|
|
phandle = <0x250>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x252>;
|
|
phandle = <0x25b>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x253>;
|
|
phandle = <0x254>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr1-replicator {
|
|
compatible = "arm,coresight-static-replicator";
|
|
coresight-name = "coresight-replicator-etr1";
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x254>;
|
|
phandle = <0x253>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x255>;
|
|
phandle = <0x259>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x256>;
|
|
phandle = <0x25c>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc-modem {
|
|
compatible = "qcom,coresight-secure-etr";
|
|
coresight-name = "coresight-modem-etr1";
|
|
real-name = "coresight-tmc-etr1";
|
|
qdss,buffer-size = <0x2000000>;
|
|
qcom,secure-component;
|
|
memory-region = <0x257>;
|
|
coresight-csr = <0x258>;
|
|
csr-atid-offset = <0x108>;
|
|
csr-irqctrl-offset = <0x70>;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f5>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x259>;
|
|
phandle = <0x255>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25a>;
|
|
phandle = <0x265>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@10048000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x10048000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etr";
|
|
qcom,iommu-dma = "bypass";
|
|
iommus = <0x75 0x4e0 0x00>;
|
|
dma-coherent;
|
|
arm,scatter-gather;
|
|
qcom,sw-usb;
|
|
coresight-csr = <0x258>;
|
|
csr-atid-offset = <0xf8>;
|
|
csr-irqctrl-offset = <0x6c>;
|
|
byte-cntr-name = "byte-cntr";
|
|
byte-cntr-class-name = "coresight-tmc-etr-stream";
|
|
interrupts = <0x00 0x2e2 0x01>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f6>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25b>;
|
|
phandle = <0x252>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tmc@1004f000 {
|
|
compatible = "arm,primecell";
|
|
arm,primecell-periphid = <0xbb961>;
|
|
reg = <0x1004f000 0x1000>;
|
|
reg-names = "tmc-base";
|
|
coresight-name = "coresight-tmc-etr1";
|
|
iommus = <0x75 0x500 0x00>;
|
|
dma-coherent;
|
|
arm,scatter-gather;
|
|
coresight-csr = <0x258>;
|
|
csr-atid-offset = <0x108>;
|
|
csr-irqctrl-offset = <0x70>;
|
|
byte-cntr-name = "byte-cntr1";
|
|
byte-cntr-class-name = "coresight-tmc-etr1-stream";
|
|
interrupts = <0x00 0x2e1 0x01>;
|
|
interrupt-names = "byte-cntr-irq";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f7>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25c>;
|
|
phandle = <0x256>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
turing-qmi {
|
|
compatible = "qcom,coresight-qmi";
|
|
coresight-name = "coresight-qmi-turing";
|
|
qcom,inst-id = <0x0d>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25d>;
|
|
phandle = <0x12b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
audio-qmi {
|
|
compatible = "qcom,coresight-qmi";
|
|
coresight-name = "coresight-qmi-auido";
|
|
qcom,inst-id = <0x05>;
|
|
|
|
in-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25e>;
|
|
phandle = <0x1ef>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x25f>;
|
|
phandle = <0x1fa>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x260>;
|
|
phandle = <0x1f1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x261>;
|
|
phandle = <0x1f3>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x262>;
|
|
phandle = <0x1f5>;
|
|
};
|
|
};
|
|
|
|
port@5 {
|
|
reg = <0x05>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x263>;
|
|
phandle = <0x1d8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem0-qmi {
|
|
compatible = "qcom,coresight-qmi";
|
|
coresight-name = "coresight-qmi-modem0";
|
|
qcom,inst-id = <0x02>;
|
|
|
|
in-ports {
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x264>;
|
|
phandle = <0x135>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x265>;
|
|
phandle = <0x25a>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
modem2-qmi {
|
|
compatible = "qcom,coresight-qmi";
|
|
coresight-name = "coresight-qmi-modem2";
|
|
qcom,inst-id = <0x0b>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x266>;
|
|
phandle = <0x137>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cti@10010000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10010000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-qdss";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,cti-gpio-trigout = <0x10>;
|
|
pinctrl-names = "cti-trigout-pctrl";
|
|
pinctrl-0 = <0x267>;
|
|
};
|
|
|
|
cti@10b00000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b00000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-swao";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x4f8>;
|
|
};
|
|
|
|
cti@10b21000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b21000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-aoss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@12100000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x12100000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_cti";
|
|
qcom,extended_cti;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
};
|
|
|
|
cti@12195000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x12195000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-apss_dl";
|
|
qcom,extended_cti;
|
|
clocks = <0x19 0x163 0x00>;
|
|
clock-names = "apb_pclk\0dynamic_clk";
|
|
};
|
|
|
|
cti@10a05000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10a05000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-camera";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@1098b000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x1098b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-turing_qdsp";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10985000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10985000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-turing";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10d21000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10d21000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_shrm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b35000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b35000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_lpi";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10d05000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10d05000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_center";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10d07000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10d07000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_chhm02";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10d09000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10d09000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-ddr_chhm13";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10c62000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10c62000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mdss";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10961000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10961000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-a6x_isdb";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10962000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10962000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-a6x_gpmu";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10901000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10901000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-a6x_dragonlink";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b42000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b42000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b4b000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b4b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_qdsp";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b41000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b41000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_cti_1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b51000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b51000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass_lpi_cti_3";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10b85000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10b85000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-lpass";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10813000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10813000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mss_vdsp6";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@1080b000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x1080b000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mss_qdsp6";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10802000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10802000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-mss";
|
|
qcom,extended_cti;
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
cti@10cd1000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10cd1000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_rvss";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10cc2000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10cc2000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_dragonlink_cti0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@10cc3000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10cc3000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-tmess_dragonlink_cti1";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
status = "disabled";
|
|
};
|
|
|
|
cti@109a0000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x109a0000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-trace_noc_cti0";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
cti@109a1000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x109a1000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-trace_noc_cti2";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
cti@109a2000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x109a2000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-trace_noc_cti0_mm";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
cti@109c1000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x109c1000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-eva";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
cti@10ba5000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10ba5000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-soccp";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
cti@10831000 {
|
|
compatible = "arm,coresight-cti\0arm,primecell";
|
|
reg = <0x10831000 0x1000>;
|
|
arm,primecell-periphid = <0xbb922>;
|
|
coresight-name = "coresight-cti-venus";
|
|
clocks = <0x19>;
|
|
clock-names = "apb_pclk";
|
|
qcom,extended_cti;
|
|
};
|
|
|
|
dcc@100ff000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x100ff000 0x1000 0x10080800 0x7800>;
|
|
reg-names = "dcc-base\0dcc-ram-base";
|
|
qcom,transaction_timeout = <0x80>;
|
|
dcc-ram-offset = <0x800>;
|
|
phandle = <0x4f9>;
|
|
|
|
link_list_0 {
|
|
qcom,curr-link-list = <0x06>;
|
|
qcom,data-sink = "sram";
|
|
qcom,ap-qad-override;
|
|
qcom,link-list = <0x00 0x16801000 0x02 0x00 0x00 0x18880258 0x0a 0x00 0x00 0x18880288 0x06 0x00 0x00 0x188802a8 0x0a 0x00 0x00 0x18880328 0x06 0x00 0x00 0x188803d8 0x0a 0x00 0x00 0x18880408 0x02 0x00 0x00 0x19880258 0x0a 0x00 0x00 0x19880288 0x06 0x00 0x00 0x198802a8 0x0a 0x00 0x00 0x19880328 0x06 0x00 0x00 0x198803d8 0x0a 0x00 0x00 0x19880408 0x02 0x00 0x00 0x188b0000 0x04 0x00 0x00 0x188b0050 0x02 0x00 0x00 0x188b00e8 0x24 0x00 0x00 0x188b0788 0x02 0x00 0x00 0x188b0c18 0x02 0x00 0x00 0x198b0000 0x04 0x00 0x00 0x198b0050 0x02 0x00 0x00 0x198b00e8 0x24 0x00 0x00 0x198b0788 0x02 0x00 0x00 0x198b0c18 0x02 0x00 0x00 0x17988814 0x02 0x00 0x00 0x17998814 0x02 0x00 0x00 0x179d2000 0x03 0x00 0x00 0x179d2020 0x03 0x00 0x00 0x179d2040 0x02 0x00 0x00 0x179d2060 0x02 0x00 0x00 0x179d2080 0x02 0x00 0x00 0x179d20a0 0x01 0x00 0x00 0x179d20b0 0x01 0x00 0x00 0x179d20c0 0x01 0x00 0x00 0x179d2200 0x02 0x00 0x00 0x179d2220 0x02 0x00 0x00 0x179d2280 0x02 0x00 0x00 0x179d22f0 0x01 0x00 0x00 0x179d2304 0x01 0x00 0x00 0x179d2310 0x01 0x00 0x00 0x179d2400 0x04 0x00 0x00 0x179d2420 0x01 0x00 0x00 0x179d2428 0x02 0x00 0x00 0x179d2440 0x02 0x00 0x00 0x179d2520 0x02 0x00 0x00 0x179d2600 0x02 0x00 0x00 0x179d2710 0x02 0x00 0x00 0x179d2720 0x02 0x00 0x00 0x179d2740 0x02 0x00 0x00 0x179d3080 0x02 0x00 0x00 0x17846018 0x02 0x00 0x00 0x17846060 0x01 0x00 0x00 0x17846100 0x02 0x00 0x00 0x17846110 0x01 0x00 0x00 0x17847030 0x02 0x00 0x00 0x17847040 0x02 0x00 0x00 0x17847050 0x02 0x00 0x00 0x17847060 0x02 0x00 0x00 0x17847070 0x02 0x00 0x00 0x17847080 0x02 0x00 0x00 0x17847090 0x02 0x00 0x00 0x178470a0 0x02 0x00 0x00 0x178470b0 0x02 0x00 0x00 0x178470c0 0x02 0x00 0x00 0x17850000 0x02 0x00 0x00 0x17850010 0x02 0x00 0x00 0x17850030 0x02 0x00 0x00 0x17850040 0x01 0x00 0x00 0x17854000 0x01 0x00 0x00 0x17854008 0x04 0x00 0x00 0x179c8814 0x02 0x00 0x00 0x179d0104 0x01 0x00 0x00 0x179d0118 0x02 0x00 0x00 0x179d0148 0x02 0x00 0x00 0x179d1600 0x01 0x00 0x00 0x179d1678 0x01 0x00 0x00 0x179d1688 0x02 0x00 0x00 0x179d1694 0x03 0x00 0x00 0x179d1820 0x03 0x00 0x00 0x17b70000 0x01 0x00 0x00 0x17b70008 0x02 0x00 0x00 0x17b71000 0x01 0x00 0x00 0x17b71008 0x02 0x00 0x00 0x164807f8 0x01 0x00 0x00 0x16480810 0x03 0x00 0x00 0x16483000 0x28 0x00 0x00 0x16483a00 0x02 0x00 0x00 0x16488908 0x01 0x00 0x00 0x16488c18 0x01 0x00 0x00 0x164a8908 0x01 0x00 0x00 0x164a8c18 0x01 0x00 0x00 0x164a07f8 0x01 0x00 0x00 0x164a0810 0x03 0x00 0x00 0x164a3000 0x28 0x00 0x00 0x164a3a00 0x02 0x00 0x00 0x16493000 0x28 0x00 0x00 0x16493a00 0x02 0x00 0x00 0x16498c18 0x01 0x00 0x00 0x164b8c18 0x01 0x00 0x00 0x164b3a00 0x02 0x00 0x00 0x16440000 0x02 0x00 0x00 0x16440020 0x03 0x00 0x00 0x16440030 0x01 0x00 0x00 0x1644003c 0x01 0x00 0x00 0x16440044 0x03 0x00 0x00 0x16440438 0x01 0x00 0x00 0x16440500 0x05 0x00 0x00 0x16562000 0x02 0x00 0x00 0x16565004 0x01 0x00 0x00 0x17000bd0 0x01 0x00 0x00 0x170404a0 0x01 0x00 0x00 0x170a0590 0x01 0x00 0x00 0x170c0330 0x01 0x00 0x00 0x170c0338 0x01 0x00 0x00 0x170c0340 0x01 0x00 0x00 0x170c0518 0x01 0x00 0x00 0x170c0528 0x01 0x00 0x00 0x170c0538 0x01 0x00 0x00 0x170c0560 0x04 0x00 0x00 0x17200bd0 0x01 0x00 0x00 0x172404a0 0x01 0x00 0x00 0x172a0590 0x01 0x00 0x00 0x172c0330 0x01 0x00 0x00 0x172c0338 0x01 0x00 0x00 0x172c0340 0x01 0x00 0x00 0x172c0518 0x01 0x00 0x00 0x172c0528 0x01 0x00 0x00 0x172c0538 0x01 0x00 0x00 0x172c0560 0x04 0x00 0x00 0x1641000c 0x01 0x00 0x00 0x1641400c 0x01 0x00 0x00 0x18830320 0x02 0x00 0x00 0x19830320 0x02 0x00 0x00 0x18040010 0x06 0x00 0x00 0x18040040 0x0a 0x00 0x00 0x18040090 0x06 0x00 0x00 0x18850020 0x02 0x00 0x00 0x18850060 0x02 0x00 0x00 0x188500a0 0x02 0x00 0x00 0x188500e0 0x02 0x00 0x00 0x18850120 0x02 0x00 0x00 0x18850160 0x02 0x00 0x00 0x189c1000 0x01 0x00 0x00 0x199c1000 0x01 0x00 0x00 0x18a30000 0x09 0x00 0x00 0x18a30030 0x01 0x00 0x00 0x18a3003c 0x02 0x00 0x00 0x19a30000 0x09 0x00 0x00 0x19a30030 0x01 0x00 0x00 0x19a3003c 0x02 0x00 0x00 0x24201040 0x01 0x00 0x00 0x24201048 0x01 0x00 0x00 0x24100010 0x01 0x00 0x00 0x24100020 0x06 0x00 0x00 0x24180010 0x01 0x00 0x00 0x24180020 0x06 0x00 0x00 0x24200010 0x01 0x00 0x00 0x24200020 0x06 0x00 0x00 0x24200410 0x01 0x00 0x00 0x24200420 0x06 0x00 0x00 0x24102010 0x01 0x00 0x00 0x24102038 0x01 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102038 0x01 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102038 0x01 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102038 0x01 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102008 0x02 0x00 0x00 0x24181010 0x01 0x00 0x00 0x24181038 0x01 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181038 0x01 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181038 0x01 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181038 0x01 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181008 0x02 0x00 0x00 0x24203010 0x01 0x00 0x00 0x24203038 0x01 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203038 0x01 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203038 0x01 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203038 0x01 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203030 0x02 0x00 0x00 0x24203008 0x02 0x00 0x00 0x24203410 0x01 0x00 0x00 0x24203438 0x01 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203438 0x01 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203438 0x01 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203438 0x01 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203430 0x02 0x00 0x00 0x24203408 0x02 0x00 0x00 0x24104018 0x01 0x00 0x00 0x24104008 0x01 0x00 0x00 0x24104010 0x02 0x00 0x00 0x24104010 0x02 0x00 0x00 0x24104010 0x02 0x00 0x00 0x24104010 0x02 0x00 0x00 0x24104098 0x01 0x00 0x00 0x24104088 0x01 0x00 0x00 0x24104090 0x02 0x00 0x00 0x24104090 0x02 0x00 0x00 0x24104090 0x02 0x00 0x00 0x24104090 0x02 0x00 0x00 0x24104090 0x02 0x00 0x00 0x24182018 0x01 0x00 0x00 0x24182008 0x01 0x00 0x00 0x24182010 0x02 0x00 0x00 0x24182010 0x02 0x00 0x00 0x24182010 0x02 0x00 0x00 0x24182010 0x02 0x00 0x00 0x24182098 0x01 0x00 0x00 0x24182088 0x01 0x00 0x00 0x24182090 0x02 0x00 0x00 0x24182090 0x02 0x00 0x00 0x24182090 0x02 0x00 0x00 0x24182090 0x02 0x00 0x00 0x24182090 0x02 0x00 0x00 0x24204018 0x01 0x00 0x00 0x24204008 0x01 0x00 0x00 0x24204010 0x02 0x00 0x00 0x24204010 0x02 0x00 0x00 0x24204010 0x02 0x00 0x00 0x24204098 0x01 0x00 0x00 0x24204088 0x01 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x00 0x24204090 0x02 0x00 0x01 0x24102028 0x02 0x00 0x02 0x40 0x00 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x00 0x24102030 0x02 0x00 0x02 0x01 0x00 0x00 0x01 0x24102028 0x01 0x00 0x01 0x24181028 0x02 0x00 0x02 0x40 0x00 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x00 0x24181030 0x02 0x00 0x02 0x01 0x00 0x00 0x01 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0x02 0x00 0x00 0x24076c68 0x02 0x00 0x00 0x24076c74 0x02 0x00 0x00 0x24076950 0x01 0x00 0x00 0x240760a4 0x01 0x00 0x00 0x248720b0 0x01 0x00 0x00 0x258720b0 0x01 0x00 0x00 0x24c720b0 0x01 0x00 0x00 0x25c720b0 0x01 0x00>;
|
|
};
|
|
|
|
link_list_1 {
|
|
qcom,curr-link-list = <0x04>;
|
|
qcom,data-sink = "sram";
|
|
qcom,ap-qad-override;
|
|
qcom,link-list = <0x00 0x16801000 0x02 0x00 0x00 0x240e0010 0x01 0x00 0x00 0x240e0020 0x08 0x00 0x00 0x240e0248 0x01 0x00 0x00 0x24330010 0x01 0x00 0x00 0x24330020 0x08 0x00 0x00 0x24330248 0x01 0x00 0x00 0x240e1018 0x01 0x00 0x00 0x240e1008 0x01 0x00 0x02 0x09 0x00 0x00 0x00 0x240e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x24331018 0x01 0x00 0x00 0x24331008 0x01 0x00 0x02 0x08 0x00 0x00 0x00 0x24331010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1780010 0x01 0x00 0x00 0x1780020 0x08 0x00 0x00 0x1780248 0x01 0x00 0x00 0x1782018 0x01 0x00 0x00 0x1782008 0x01 0x00 0x02 0x0c 0x00 0x00 0x00 0x1782010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1783018 0x01 0x00 0x00 0x1783008 0x01 0x00 0x02 0x11 0x00 0x00 0x00 0x1783010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1680010 0x01 0x00 0x00 0x1680020 0x08 0x00 0x00 0x1681048 0x01 0x00 0x00 0x1682018 0x01 0x00 0x00 0x1682008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x1682010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e0010 0x01 0x00 0x00 0x16e0020 0x08 0x00 0x00 0x16e0248 0x01 0x00 0x00 0x16e1018 0x01 0x00 0x00 0x16e1008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x16e1010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1098 0x01 0x00 0x00 0x16e1088 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x16e1090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e1118 0x01 0x00 0x00 0x16e1108 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x16e1110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1700010 0x01 0x00 0x00 0x1700020 0x08 0x00 0x00 0x1700248 0x01 0x00 0x00 0x1702018 0x01 0x00 0x00 0x1702008 0x01 0x00 0x02 0x04 0x00 0x00 0x00 0x1702010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1702218 0x01 0x00 0x00 0x1702208 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1702210 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1702118 0x01 0x00 0x00 0x1702108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1702110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1600010 0x01 0x00 0x00 0x1600020 0x08 0x00 0x00 0x1600248 0x02 0x00 0x00 0x1600258 0x01 0x00 0x00 0x1602018 0x01 0x00 0x00 0x1602008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1602010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602098 0x01 0x00 0x00 0x1602088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602118 0x01 0x00 0x00 0x1602108 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602110 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602198 0x01 0x00 0x00 0x1602188 0x01 0x00 0x02 0x03 0x00 0x00 0x00 0x1602190 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602218 0x01 0x00 0x00 0x1602208 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602210 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1602098 0x01 0x00 0x00 0x1602088 0x01 0x00 0x02 0x02 0x00 0x00 0x00 0x1602090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1500010 0x01 0x00 0x00 0x1500020 0x08 0x00 0x00 0x1500248 0x01 0x00 0x00 0x1500448 0x01 0x00 0x00 0x1502018 0x01 0x00 0x00 0x1502008 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1502098 0x01 0x00 0x00 0x1502088 0x01 0x00 0x02 0x07 0x00 0x00 0x00 0x1502090 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16e00010 0x01 0x00 0x00 0x16e00020 0x08 0x00 0x00 0x16e00248 0x01 0x00 0x00 0x16e01018 0x01 0x00 0x00 0x16e01008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x16e01010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x1b600010 0x01 0x00 0x00 0x1b600020 0x08 0x00 0x00 0x1b600248 0x01 0x00 0x00 0x1b601018 0x01 0x00 0x00 0x1b601008 0x01 0x00 0x02 0x06 0x00 0x00 0x00 0x1b601010 0x02 0x00 0x02 0x01 0x00 0x00 0x00 0x16000104 0x1e 0x00 0x00 0x16000204 0x1d 0x00 0x00 0x16000384 0x1e 0x00 0x00 0xb291024 0x01 0x00 0x00 0xc201244 0x01 0x00 0x00 0xc202244 0x01 0x00 0x00 0xbde1034 0x01 0x00 0x00 0xbde1038 0x01 0x00 0x00 0xb201020 0x02 0x00 0x00 0xb211020 0x02 0x00 0x00 0xb221020 0x02 0x00 0x00 0xb231020 0x02 0x00 0x00 0xb204520 0x01 0x00 0x00 0xb200000 0x01 0x00 0x00 0xb210000 0x01 0x00 0x00 0xb220000 0x01 0x00 0x00 0xb230000 0x01 0x00 0x00 0x16500010 0x01 0x00 0x00 0x16510010 0x01 0x00 0x00 0x16520010 0x01 0x00 0x00 0x16530010 0x01 0x00 0x00 0x16500030 0x01 0x00 0x00 0x16510030 0x01 0x00 0x00 0x16520030 0x01 0x00 0x00 0x16530030 0x01 0x00 0x00 0x16500038 0x01 0x00 0x00 0x16510038 0x01 0x00 0x00 0x16520038 0x01 0x00 0x00 0x16530038 0x01 0x00 0x00 0x16500040 0x01 0x00 0x00 0x16510040 0x01 0x00 0x00 0x16520040 0x01 0x00 0x00 0x16530040 0x01 0x00 0x00 0x16500048 0x01 0x00 0x00 0x16500400 0x03 0x00 0x00 0x16510400 0x03 0x00 0x00 0x16520400 0x03 0x00 0x00 0x16530400 0x03 0x00 0x00 0x16510d3c 0x01 0x00 0x00 0x16510d54 0x01 0x00 0x00 0x16510d6c 0x01 0x00 0x00 0x16510d84 0x01 0x00 0x00 0x16510d9c 0x01 0x00 0x00 0x16510db4 0x01 0x00 0x00 0x16510dcc 0x01 0x00 0x00 0x16510de4 0x01 0x00 0x00 0x16510dfc 0x01 0x00 0x00 0x16510e14 0x01 0x00 0x00 0x16510e2c 0x01 0x00 0x00 0x16510e44 0x01 0x00 0x00 0x16510e5c 0x01 0x00 0x00 0x16510e74 0x01 0x00 0x00 0x16510e8c 0x01 0x00 0x00 0x16510ea4 0x01 0x00 0x00 0x16510fdc 0x01 0x00 0x00 0x16510ff4 0x01 0x00 0x00 0x1651100c 0x01 0x00 0x00 0x16511024 0x01 0x00 0x00 0x1651103c 0x01 0x00 0x00 0x16511054 0x01 0x00 0x00 0x1651106c 0x01 0x00 0x00 0x16511084 0x01 0x00 0x00 0x1651109c 0x01 0x00 0x00 0x165110b4 0x01 0x00 0x00 0x165110cc 0x01 0x00 0x00 0x165110e4 0x01 0x00 0x00 0x165110fc 0x01 0x00 0x00 0x16511114 0x01 0x00 0x00 0x1651112c 0x01 0x00 0x00 0x16511144 0x01 0x00 0x00 0x1651127c 0x01 0x00 0x00 0x16511294 0x01 0x00 0x00 0x165112ac 0x01 0x00 0x00 0x165112c4 0x01 0x00 0x00 0x165112dc 0x01 0x00 0x00 0x165112f4 0x01 0x00 0x00 0x1651130c 0x01 0x00 0x00 0x16511324 0x01 0x00 0x00 0x1651133c 0x01 0x00 0x00 0x16511354 0x01 0x00 0x00 0x1651136c 0x01 0x00 0x00 0x16511384 0x01 0x00 0x00 0x1651139c 0x01 0x00 0x00 0x165113b4 0x01 0x00 0x00 0x165113cc 0x01 0x00 0x00 0x165113e4 0x01 0x00 0x00 0x1651151c 0x01 0x00 0x00 0x16511534 0x01 0x00 0x00 0x1651154c 0x01 0x00 0x00 0x16511564 0x01 0x00 0x00 0x1651157c 0x01 0x00 0x00 0x16511594 0x01 0x00 0x00 0x165115ac 0x01 0x00 0x00 0x165115c4 0x01 0x00 0x00 0x165115dc 0x01 0x00 0x00 0x165115f4 0x01 0x00 0x00 0x1651160c 0x01 0x00 0x00 0x16511624 0x01 0x00 0x00 0x1651163c 0x01 0x00 0x00 0x16511654 0x01 0x00 0x00 0x1651166c 0x01 0x00 0x00 0x16511684 0x01 0x00 0x00 0x110004 0x02 0x00 0x00 0x11003c 0x03 0x00 0x00 0x176040 0x01 0x00 0x00 0x10c0000 0x04 0x00 0x00 0x10c1000 0x02 0x00 0x00 0x10c1010 0x07 0x00 0x00 0x10c1100 0x03 0x00 0x00 0x10c1110 0x05 0x00 0x00 0x10c1130 0x02 0x00 0x00 0x10c113c 0x02 0x00 0x00 0x10c1148 0x03 0x00 0x00 0x10c1800 0x0b 0x00 0x00 0x10c2000 0x01 0x00 0x00 0x10cf004 0x01 0x00 0x00 0x16801000 0x02 0x00>;
|
|
};
|
|
};
|
|
|
|
mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <0x268>;
|
|
|
|
static_dump {
|
|
qcom,static-mem-dump;
|
|
|
|
c0_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x00>;
|
|
};
|
|
|
|
c100_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x01>;
|
|
};
|
|
|
|
c200_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x02>;
|
|
};
|
|
|
|
c300_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x03>;
|
|
};
|
|
|
|
c400_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x04>;
|
|
};
|
|
|
|
c500_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x05>;
|
|
};
|
|
|
|
c600_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x06>;
|
|
};
|
|
|
|
c700_context {
|
|
qcom,dump-size = <0x800>;
|
|
qcom,dump-id = <0x07>;
|
|
};
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x400000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x200000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
etf_swao {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
etr1_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x105>;
|
|
};
|
|
|
|
etf_slpi {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf3>;
|
|
};
|
|
|
|
etfslpi_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x103>;
|
|
};
|
|
|
|
etf_lpass {
|
|
qcom,dump-size = <0x4000>;
|
|
qcom,dump-id = <0xf4>;
|
|
};
|
|
|
|
etflpass_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x104>;
|
|
};
|
|
|
|
osm_reg {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x163>;
|
|
};
|
|
|
|
pcu_reg {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x164>;
|
|
};
|
|
|
|
fsm_data {
|
|
qcom,dump-size = <0x400>;
|
|
qcom,dump-id = <0x165>;
|
|
};
|
|
|
|
scandump_smmu {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x220>;
|
|
};
|
|
|
|
apps_scandump {
|
|
qcom,dump-size = <0x380000>;
|
|
qcom,dump-id = <0x130>;
|
|
};
|
|
};
|
|
|
|
dynamic_mem_dump {
|
|
qcom,dynamic-mem-dump;
|
|
|
|
scandump_gpu {
|
|
|
|
scandump_gpu {
|
|
qcom,dump-size = <0x300000>;
|
|
qcom,dump-id = <0x221>;
|
|
};
|
|
};
|
|
|
|
cpuss_reg {
|
|
|
|
cpuss_reg {
|
|
qcom,dump-size = <0xa00000>;
|
|
qcom,dump-id = <0xef>;
|
|
};
|
|
};
|
|
|
|
spr {
|
|
|
|
spr_cpu0 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f0>;
|
|
};
|
|
|
|
spr_cpu1 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f1>;
|
|
};
|
|
|
|
spr_cpu2 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f2>;
|
|
};
|
|
|
|
spr_cpu3 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f3>;
|
|
};
|
|
|
|
spr_cpu4 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f4>;
|
|
};
|
|
|
|
spr_cpu5 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f5>;
|
|
};
|
|
|
|
spr_cpu6 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f6>;
|
|
};
|
|
|
|
spr_cpu7 {
|
|
qcom,dump-size = <0x2000>;
|
|
qcom,dump-id = <0x1f7>;
|
|
};
|
|
};
|
|
|
|
cpuss_cpu {
|
|
|
|
cpuss_cpu0 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x280>;
|
|
};
|
|
|
|
cpuss_cpu1 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x281>;
|
|
};
|
|
|
|
cpuss_cpu2 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x282>;
|
|
};
|
|
|
|
cpuss_cpu3 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x283>;
|
|
};
|
|
|
|
cpuss_cpu4 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x284>;
|
|
};
|
|
|
|
cpuss_cpu5 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x285>;
|
|
};
|
|
|
|
cpuss_cpu6 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x286>;
|
|
};
|
|
|
|
cpuss_cpu7 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x287>;
|
|
};
|
|
};
|
|
|
|
cpuss_cluster {
|
|
|
|
cpuss_cluster0 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x270>;
|
|
};
|
|
|
|
cpuss_cluster1 {
|
|
qcom,dump-size = <0x40000>;
|
|
qcom,dump-id = <0x271>;
|
|
};
|
|
};
|
|
|
|
cpucp {
|
|
|
|
cpucp {
|
|
qcom,dump-size = <0x80000>;
|
|
qcom,dump-id = <0xf5>;
|
|
};
|
|
};
|
|
|
|
cpu_cache {
|
|
|
|
cache_cpu0 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x230>;
|
|
};
|
|
|
|
cache_cpu1 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x231>;
|
|
};
|
|
|
|
cache_cpu2 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x232>;
|
|
};
|
|
|
|
cache_cpu3 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x233>;
|
|
};
|
|
|
|
cache_cpu4 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x234>;
|
|
};
|
|
|
|
cache_cpu5 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x235>;
|
|
};
|
|
|
|
cache_cpu6 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x236>;
|
|
};
|
|
|
|
cache_cpu7 {
|
|
qcom,dump-size = <0x2aa000>;
|
|
qcom,dump-id = <0x237>;
|
|
};
|
|
};
|
|
|
|
cluster_cache {
|
|
|
|
cl_cache0 {
|
|
qcom,dump-size = <0x1400000>;
|
|
qcom,dump-id = <0x240>;
|
|
};
|
|
|
|
cl_cache1 {
|
|
qcom,dump-size = <0x1400000>;
|
|
qcom,dump-id = <0x241>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
kgsl-smmu@3da0000 {
|
|
compatible = "qcom,qsmmu-v500\0qcom,adreno-smmu";
|
|
reg = <0x3da0000 0x40000>;
|
|
#iommu-cells = <0x02>;
|
|
qcom,use-3-lvl-tables;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
dma-coherent;
|
|
power-domains = <0x50 0x01>;
|
|
interconnects = <0x78 0x00 0x45 0x201>;
|
|
clocks = <0x50 0x11>;
|
|
clock-names = "gpu_cc_hlos1_vote_gpu_smmu";
|
|
interrupts = <0x00 0x2a2 0x04 0x00 0x2a6 0x04 0x00 0x2a7 0x04 0x00 0x2a8 0x04 0x00 0x2a9 0x04 0x00 0x2aa 0x04 0x00 0x2ab 0x04 0x00 0x2ac 0x04 0x00 0x2ad 0x04 0x00 0x2ae 0x04 0x00 0x2af 0x04 0x00 0x2b0 0x04 0x00 0x1a6 0x04 0x00 0x1dc 0x04 0x00 0x23e 0x04 0x00 0x23f 0x04 0x00 0x240 0x04 0x00 0x241 0x04 0x00 0x294 0x04 0x00 0x296 0x04 0x00 0x299 0x04 0x00 0x29a 0x04 0x00 0x29b 0x04 0x00 0x29d 0x04 0x00 0x29e 0x04 0x00 0x2bc 0x04>;
|
|
qcom,actlr = <0x00 0x3ff 0x32b>;
|
|
phandle = <0x26b>;
|
|
|
|
gpu_qtb@3de8000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x3de8000 0x1000>;
|
|
qcom,stream-id-range = <0x00 0x400>;
|
|
qcom,iova-width = <0x31>;
|
|
interconnects = <0x78 0x00 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x4fa>;
|
|
};
|
|
};
|
|
|
|
apps-smmu@15000000 {
|
|
compatible = "qcom,qsmmu-v500";
|
|
reg = <0x15000000 0x100000>;
|
|
#iommu-cells = <0x02>;
|
|
qcom,use-3-lvl-tables;
|
|
qcom,handoff-smrs = <0x800 0x02>;
|
|
#global-interrupts = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
ranges;
|
|
dma-coherent;
|
|
interrupts = <0x00 0x41 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0xb5 0x04 0x00 0xb6 0x04 0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x13e 0x04 0x00 0x13f 0x04 0x00 0x140 0x04 0x00 0x141 0x04 0x00 0x142 0x04 0x00 0x143 0x04 0x00 0x144 0x04 0x00 0x145 0x04 0x00 0x146 0x04 0x00 0x147 0x04 0x00 0x148 0x04 0x00 0x149 0x04 0x00 0x14a 0x04 0x00 0x14b 0x04 0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04 0x00 0x152 0x04 0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x155 0x04 0x00 0x156 0x04 0x00 0x157 0x04 0x00 0x158 0x04 0x00 0x159 0x04 0x00 0x18b 0x04 0x00 0x18c 0x04 0x00 0x18d 0x04 0x00 0x18e 0x04 0x00 0x18f 0x04 0x00 0x190 0x04 0x00 0x191 0x04 0x00 0x192 0x04 0x00 0x193 0x04 0x00 0x194 0x04 0x00 0x195 0x04 0x00 0x196 0x04 0x00 0x197 0x04 0x00 0x198 0x04 0x00 0x199 0x04 0x00 0x1a2 0x04 0x00 0x1a3 0x04 0x00 0x19c 0x04 0x00 0x1a5 0x04 0x00 0x2c3 0x04 0x00 0x1a7 0x04 0x00 0x1a8 0x04 0x00 0x1a9 0x04 0x00 0x2b2 0x04 0x00 0x2b3 0x04 0x00 0x2b4 0x04 0x00 0x2b5 0x04 0x00 0x2b6 0x04 0x00 0x2b7 0x04 0x00 0x2b8 0x04 0x00 0x2b9 0x04 0x00 0x19a 0x04 0x00 0x1e8 0x04 0x00 0x1e9 0x04 0x00 0x1ea 0x04 0x00 0x1eb 0x04 0x00 0x1ec 0x04 0x00 0x1ed 0x04 0x00 0x1ee 0x04 0x00 0x1ef 0x04 0x00 0x1f0 0x04 0x00 0x1f1 0x04 0x00 0x1f2 0x04 0x00 0x1f3 0x04 0x00 0x1f4 0x04 0x00 0x1f5 0x04 0x00 0x1f6 0x04>;
|
|
qcom,actlr = <0x1c00 0x00 0x01 0x800 0x02 0x01 0x801 0x00 0x01 0xc01 0x40 0x303 0xc02 0x20 0x303 0xc03 0x40 0x303 0xc04 0x40 0x303 0xc05 0x40 0x303 0xc06 0x20 0x303 0xc07 0x40 0x303 0xc08 0x20 0x303 0xc09 0x40 0x303 0xc0c 0x40 0x303 0xc0d 0x20 0x303 0xc0e 0x40 0x303 0xc21 0x00 0x303 0xc23 0x00 0x303 0xc24 0x00 0x303 0xc25 0x00 0x303 0xc27 0x00 0x303 0xc29 0x00 0x303 0xc2c 0x00 0x303 0xc2e 0x00 0x303 0xc42 0x00 0x303 0xc46 0x00 0x303 0xc48 0x00 0x303 0xc4d 0x00 0x303 0x1800 0xc0 0x01 0x1820 0x00 0x01 0x1860 0x00 0x103 0x18a0 0x00 0x103 0x18e0 0x00 0x103 0x1980 0x00 0x01 0x1900 0x20 0x103 0x1904 0x20 0x103 0x1923 0x00 0x103 0x1940 0x00 0x103 0x1941 0x04 0x103 0x1943 0x00 0x103 0x1944 0x00 0x103 0x1947 0x00 0x103>;
|
|
phandle = <0x75>;
|
|
|
|
anoc_1_qtb@16f2000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x16f2000 0x1000>;
|
|
qcom,stream-id-range = <0x00 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0x269 0x08 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x4fb>;
|
|
};
|
|
|
|
anoc_2_qtb@171b000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x171b000 0x1000>;
|
|
qcom,stream-id-range = <0x400 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0x269 0x09 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x4fc>;
|
|
};
|
|
|
|
cam_hf_qtb@17d2000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x17d2000 0x1000>;
|
|
qcom,stream-id-range = <0x1c00 0x400>;
|
|
qcom,iova-width = <0x24>;
|
|
interconnects = <0x5c 0x0a 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x4fd>;
|
|
};
|
|
|
|
nsp_qtb@7d3000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x7d3000 0x1000>;
|
|
qcom,stream-id-range = <0xc00 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0x96 0x19 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x4fe>;
|
|
};
|
|
|
|
lpass_qtb@7b3000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x7b3000 0x1000>;
|
|
qcom,stream-id-range = <0x1000 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0x85 0x14 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
phandle = <0x4ff>;
|
|
};
|
|
|
|
pcie_qtb@16cd000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x16cd000 0x1000>;
|
|
qcom,stream-id-range = <0x1400 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0x26a 0x2f 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x01>;
|
|
qcom,opt-out-tbu-halting;
|
|
phandle = <0x500>;
|
|
};
|
|
|
|
sf_qtb@17d1000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x17d1000 0x1000>;
|
|
qcom,stream-id-range = <0x1800 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0x5c 0x20 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x501>;
|
|
};
|
|
|
|
mdp_hf_qtb@17d0000 {
|
|
compatible = "qcom,qsmmuv500-tbu\0qcom,qtb500";
|
|
reg = <0x17d0000 0x1000>;
|
|
qcom,stream-id-range = <0x800 0x400>;
|
|
qcom,iova-width = <0x20>;
|
|
interconnects = <0x5c 0x15 0x45 0x201>;
|
|
qcom,num-qtb-ports = <0x02>;
|
|
phandle = <0x502>;
|
|
};
|
|
};
|
|
|
|
dma_dev {
|
|
compatible = "qcom,iommu-dma";
|
|
memory-region = <0x8d>;
|
|
};
|
|
|
|
iommu_test_device {
|
|
compatible = "qcom,iommu-debug-test";
|
|
|
|
usecase0_apps {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x75 0x400 0x00>;
|
|
};
|
|
|
|
usecase1_apps_fastmap {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x75 0x400 0x00>;
|
|
qcom,iommu-dma = "fastmap";
|
|
};
|
|
|
|
usecase2_apps_atomic {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x75 0x400 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
};
|
|
|
|
usecase3_apps_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x75 0x400 0x00>;
|
|
dma-coherent;
|
|
};
|
|
|
|
usecase4_apps_secure {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x75 0x400 0x00>;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
};
|
|
|
|
usecase5_kgsl {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x26b 0x07 0x00>;
|
|
};
|
|
|
|
usecase6_kgsl_dma {
|
|
compatible = "qcom,iommu-debug-usecase";
|
|
iommus = <0x26b 0x07 0x00>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
qup1_gpi_iommu_region {
|
|
iommu-addresses = <0x26c 0x00 0x100000 0x26c 0x200000 0xffe00000>;
|
|
phandle = <0x26d>;
|
|
};
|
|
|
|
qcom,gpi-dma@a00000 {
|
|
compatible = "qcom,gpi-dma";
|
|
#dma-cells = <0x05>;
|
|
reg = <0xa00000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
iommus = <0x75 0xb6 0x00>;
|
|
qcom,max-num-gpii = <0x0c>;
|
|
interrupts = <0x00 0x117 0x04 0x00 0x118 0x04 0x00 0x119 0x04 0x00 0x11a 0x04 0x00 0x11b 0x04 0x00 0x11c 0x04 0x00 0x125 0x04 0x00 0x126 0x04 0x00 0x127 0x04 0x00 0x128 0x04 0x00 0x129 0x04 0x00 0x12a 0x04>;
|
|
qcom,static-gpii-mask = <0x01>;
|
|
qcom,gpii-mask = <0x1e>;
|
|
qcom,ev-factor = <0x01>;
|
|
memory-region = <0x26d>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
dma-coherent;
|
|
status = "ok";
|
|
phandle = <0x26c>;
|
|
};
|
|
|
|
qup1_se_iommu_region {
|
|
iommu-addresses = <0x26e 0x00 0x40000000 0x26e 0x50000000 0xb0000000>;
|
|
phandle = <0x26f>;
|
|
};
|
|
|
|
qcom,qupv3_1_geni_se@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0xac0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb\0s-ahb";
|
|
clocks = <0x34 0x7d 0x34 0x7e>;
|
|
iommus = <0x75 0xa3 0x00>;
|
|
memory-region = <0x26f>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x26e>;
|
|
|
|
i2c@a80000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x161 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x58>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x271 0x272>;
|
|
pinctrl-1 = <0x273>;
|
|
dmas = <0x26c 0x00 0x00 0x03 0x40 0x00 0x26c 0x01 0x00 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x503>;
|
|
};
|
|
|
|
spi@a80000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa80000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x161 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x58>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x274 0x275 0x276 0x277>;
|
|
pinctrl-1 = <0x278>;
|
|
dmas = <0x26c 0x00 0x00 0x01 0x40 0x00 0x26c 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x504>;
|
|
};
|
|
|
|
i3c-master@a80000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0xa80000 0x4000 0xec90000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x58>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x279 0x27a>;
|
|
pinctrl-1 = <0x27b 0x27c>;
|
|
pinctrl-2 = <0x27d>;
|
|
interrupts-extended = <0x01 0x00 0x161 0x04 0x25 0x3d 0x04 0x25 0x1e 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x01>;
|
|
dmas = <0x26c 0x00 0x00 0x04 0x40 0x00 0x26c 0x01 0x00 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x505>;
|
|
};
|
|
|
|
i2c@a84000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x162 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5a>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x27e 0x27f>;
|
|
pinctrl-1 = <0x280>;
|
|
dmas = <0x26c 0x00 0x01 0x03 0x40 0x00 0x26c 0x01 0x01 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x506>;
|
|
};
|
|
|
|
spi@a84000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa84000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x162 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5a>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x281 0x282 0x283 0x284>;
|
|
pinctrl-1 = <0x285>;
|
|
dmas = <0x26c 0x00 0x01 0x01 0x40 0x00 0x26c 0x01 0x01 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x507>;
|
|
};
|
|
|
|
i3c-master@a84000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0xa84000 0x4000 0xeca0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5a>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x286 0x287>;
|
|
pinctrl-1 = <0x288 0x289>;
|
|
pinctrl-2 = <0x28a>;
|
|
interrupts-extended = <0x01 0x00 0x162 0x04 0x25 0x3e 0x04 0x25 0x20 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x02>;
|
|
dmas = <0x26c 0x00 0x01 0x04 0x40 0x00 0x26c 0x01 0x01 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x508>;
|
|
};
|
|
|
|
i2c@a88000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x163 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5c>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x28b 0x28c>;
|
|
pinctrl-1 = <0x28d>;
|
|
dmas = <0x26c 0x00 0x02 0x03 0x40 0x00 0x26c 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x509>;
|
|
};
|
|
|
|
spi@a88000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa88000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x163 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5c>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x28e 0x28f 0x290 0x291>;
|
|
pinctrl-1 = <0x292>;
|
|
dmas = <0x26c 0x00 0x02 0x01 0x40 0x00 0x26c 0x01 0x02 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x50a>;
|
|
};
|
|
|
|
i2c@a8c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x164 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5e>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x293 0x294>;
|
|
pinctrl-1 = <0x295>;
|
|
dmas = <0x26c 0x00 0x03 0x03 0x40 0x00 0x26c 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "ok";
|
|
phandle = <0x50b>;
|
|
|
|
wcd939x_i2c@e {
|
|
compatible = "qcom,wcd939x-i2c";
|
|
reg = <0x0e>;
|
|
vdd-usb-cp-supply = <0x296>;
|
|
phandle = <0x50c>;
|
|
};
|
|
};
|
|
|
|
spi@a8c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa8c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x164 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x5e>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x297 0x298 0x299 0x29a>;
|
|
pinctrl-1 = <0x29b>;
|
|
dmas = <0x26c 0x00 0x03 0x01 0x40 0x00 0x26c 0x01 0x03 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x50d>;
|
|
};
|
|
|
|
i2c@a90000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x165 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x60>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x29c 0x29d>;
|
|
pinctrl-1 = <0x29e>;
|
|
dmas = <0x26c 0x00 0x04 0x03 0x40 0x02 0x26c 0x01 0x04 0x03 0x40 0x02>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x50e>;
|
|
};
|
|
|
|
spi@a90000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa90000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x165 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x60>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x29f 0x2a0 0x2a1 0x2a2>;
|
|
pinctrl-1 = <0x2a3>;
|
|
dmas = <0x26c 0x00 0x04 0x01 0x40 0x02 0x26c 0x01 0x04 0x01 0x40 0x02>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x50f>;
|
|
};
|
|
|
|
i3c-master@a90000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0xa90000 0x4000 0xecb0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x60>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x2a4 0x2a5>;
|
|
pinctrl-1 = <0x2a6 0x2a7>;
|
|
pinctrl-2 = <0x2a8>;
|
|
interrupts-extended = <0x01 0x00 0x165 0x04 0x25 0x3f 0x04 0x25 0x22 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x03>;
|
|
dmas = <0x26c 0x00 0x04 0x04 0x40 0x00 0x26c 0x01 0x04 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x510>;
|
|
};
|
|
|
|
i2c@a94000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x166 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x62>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2a9 0x2aa>;
|
|
pinctrl-1 = <0x2ab>;
|
|
dmas = <0x26c 0x00 0x05 0x03 0x40 0x00 0x26c 0x01 0x05 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
qcom,shared;
|
|
status = "disabled";
|
|
phandle = <0x511>;
|
|
};
|
|
|
|
spi@a94000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa94000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x166 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x62>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2ac 0x2ad 0x2ae 0x2af>;
|
|
pinctrl-1 = <0x2b0>;
|
|
dmas = <0x26c 0x00 0x05 0x01 0x40 0x00 0x26c 0x01 0x05 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x512>;
|
|
};
|
|
|
|
i2c@a98000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x16b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x64>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2b1 0x2b2>;
|
|
pinctrl-1 = <0x2b3>;
|
|
dmas = <0x26c 0x00 0x06 0x03 0x40 0x00 0x26c 0x01 0x06 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x513>;
|
|
};
|
|
|
|
spi@a98000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0xa98000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x16b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x64>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2b4 0x2b5 0x2b6 0x2b7>;
|
|
pinctrl-1 = <0x2b8>;
|
|
dmas = <0x26c 0x00 0x06 0x01 0x40 0x00 0x26c 0x01 0x06 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x514>;
|
|
};
|
|
|
|
qcom,qup_uart@a9c000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0xa9c000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x243 0x04>;
|
|
clock-names = "se";
|
|
clocks = <0x34 0x66>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x27 0x270 0x237 0x78 0x02 0x79 0x217 0x77 0x06 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2b9 0x2ba>;
|
|
pinctrl-1 = <0x2bb>;
|
|
status = "ok";
|
|
phandle = <0x515>;
|
|
};
|
|
};
|
|
|
|
qup2_gpi_iommu_region {
|
|
iommu-addresses = <0x2bc 0x00 0x100000 0x2bc 0x200000 0xffe00000>;
|
|
phandle = <0x2bd>;
|
|
};
|
|
|
|
qcom,gpi-dma@800000 {
|
|
compatible = "qcom,gpi-dma";
|
|
#dma-cells = <0x05>;
|
|
reg = <0x800000 0x60000>;
|
|
reg-names = "gpi-top";
|
|
iommus = <0x75 0x436 0x00>;
|
|
qcom,max-num-gpii = <0x0c>;
|
|
interrupts = <0x00 0x24c 0x04 0x00 0x24d 0x04 0x00 0x24e 0x04 0x00 0x24f 0x04 0x00 0x250 0x04 0x00 0x251 0x04 0x00 0x252 0x04 0x00 0x253 0x04 0x00 0x254 0x04 0x00 0x255 0x04 0x00 0x256 0x04 0x00 0x257 0x04>;
|
|
qcom,static-gpii-mask = <0x01>;
|
|
qcom,gpii-mask = <0x1e>;
|
|
qcom,ev-factor = <0x01>;
|
|
memory-region = <0x2bd>;
|
|
qcom,gpi-ee-offset = <0x10000>;
|
|
dma-coherent;
|
|
status = "ok";
|
|
phandle = <0x2bc>;
|
|
};
|
|
|
|
qup2_se_iommu_region {
|
|
iommu-addresses = <0x2be 0x00 0x40000000 0x2be 0x50000000 0xb0000000>;
|
|
phandle = <0x2bf>;
|
|
};
|
|
|
|
qcom,qupv3_2_geni_se@8c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x8c0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb\0s-ahb";
|
|
clocks = <0x34 0x81 0x34 0x82>;
|
|
iommus = <0x75 0x423 0x00>;
|
|
memory-region = <0x2bf>;
|
|
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
dma-coherent;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x2be>;
|
|
|
|
i2c@880000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x880000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x175 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6d>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2c0 0x2c1>;
|
|
pinctrl-1 = <0x2c2>;
|
|
dmas = <0x2bc 0x00 0x00 0x03 0x40 0x00 0x2bc 0x01 0x00 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x516>;
|
|
};
|
|
|
|
spi@880000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x880000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x175 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6d>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2c3 0x2c4 0x2c5 0x2c6>;
|
|
pinctrl-1 = <0x2c7>;
|
|
dmas = <0x2bc 0x00 0x00 0x01 0x40 0x00 0x2bc 0x01 0x00 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x517>;
|
|
};
|
|
|
|
i3c-master@880000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x880000 0x4000 0xecc0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6d>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x2c8 0x2c9>;
|
|
pinctrl-1 = <0x2ca 0x2cb>;
|
|
pinctrl-2 = <0x2cc>;
|
|
interrupts-extended = <0x01 0x00 0x175 0x04 0x25 0x40 0x04 0x25 0x24 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x05>;
|
|
dmas = <0x2bc 0x00 0x00 0x04 0x400 0x00 0x2bc 0x01 0x00 0x04 0x400 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x518>;
|
|
};
|
|
|
|
i2c@884000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x884000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x247 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6f>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2cd 0x2ce>;
|
|
pinctrl-1 = <0x2cf>;
|
|
dmas = <0x2bc 0x00 0x01 0x03 0x400 0x00 0x2bc 0x01 0x01 0x03 0x400 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x519>;
|
|
};
|
|
|
|
spi@884000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x884000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x247 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6f>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2d0 0x2d1 0x2d2 0x2d3>;
|
|
pinctrl-1 = <0x2d4>;
|
|
dmas = <0x2bc 0x00 0x01 0x01 0x40 0x00 0x2bc 0x01 0x01 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x51a>;
|
|
};
|
|
|
|
i3c-master@884000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x884000 0x4000 0xecd0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x6f>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x2d5 0x2d6>;
|
|
pinctrl-1 = <0x2d7 0x2d8>;
|
|
pinctrl-2 = <0x2d9>;
|
|
interrupts-extended = <0x01 0x00 0x247 0x04 0x25 0x41 0x04 0x25 0x2f 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x06>;
|
|
dmas = <0x2bc 0x00 0x01 0x04 0x40 0x00 0x2bc 0x01 0x01 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x51b>;
|
|
};
|
|
|
|
i2c@888000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x888000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x248 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x71>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2da 0x2db>;
|
|
pinctrl-1 = <0x2dc>;
|
|
dmas = <0x2bc 0x00 0x02 0x03 0x40 0x00 0x2bc 0x01 0x02 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x51c>;
|
|
};
|
|
|
|
spi@888000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x888000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x248 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x71>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2dd 0x2de 0x2df 0x2e0>;
|
|
pinctrl-1 = <0x2e1>;
|
|
dmas = <0x2bc 0x00 0x02 0x01 0x40 0x00 0x2bc 0x01 0x02 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x51d>;
|
|
};
|
|
|
|
i3c-master@888000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x888000 0x4000 0xb00000 0x10000>;
|
|
clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk";
|
|
clocks = <0x34 0x71 0x34 0x6b 0x34 0x7f 0x34 0x6a>;
|
|
qcom,ibic-naon;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x2e2 0x2e3>;
|
|
pinctrl-1 = <0x2e4 0x2e5>;
|
|
pinctrl-2 = <0x2e6>;
|
|
interrupts = <0x00 0x248 0x04 0x00 0xef 0x04 0x00 0xee 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x07>;
|
|
dmas = <0x2bc 0x00 0x02 0x04 0x40 0x00 0x2bc 0x01 0x02 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x51e>;
|
|
};
|
|
|
|
i2c@88c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x88c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x249 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x73>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2e7 0x2e8>;
|
|
pinctrl-1 = <0x2e9>;
|
|
dmas = <0x2bc 0x00 0x03 0x03 0x40 0x00 0x2bc 0x01 0x03 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x51f>;
|
|
};
|
|
|
|
spi@88c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x88c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x249 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x73>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2ea 0x2eb 0x2ec 0x2ed>;
|
|
pinctrl-1 = <0x2ee>;
|
|
dmas = <0x2bc 0x00 0x03 0x01 0x40 0x00 0x2bc 0x01 0x03 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x520>;
|
|
};
|
|
|
|
i3c-master@88c000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x88c000 0x4000 0xb10000 0x10000>;
|
|
clock-names = "se-clk\0ibic-core-clk\0ibic-ahb-clk\0ibic-src-clk";
|
|
clocks = <0x34 0x73 0x34 0x6c 0x34 0x80 0x34 0x6a>;
|
|
qcom,ibic-naon;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x2ef 0x2f0>;
|
|
pinctrl-1 = <0x2f1 0x2f2>;
|
|
pinctrl-2 = <0x2f3>;
|
|
interrupts = <0x00 0x249 0x04 0x00 0xef 0x04 0x00 0xee 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x08>;
|
|
dmas = <0x2bc 0x00 0x03 0x04 0x40 0x00 0x2bc 0x01 0x03 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x521>;
|
|
};
|
|
|
|
i2c@890000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x890000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x24a 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x75>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2f4 0x2f5>;
|
|
pinctrl-1 = <0x2f6>;
|
|
dmas = <0x2bc 0x00 0x04 0x03 0x40 0x00 0x2bc 0x01 0x04 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x522>;
|
|
};
|
|
|
|
spi@890000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x890000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x24a 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x75>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2f7 0x2f8 0x2f9 0x2fa>;
|
|
pinctrl-1 = <0x2fb>;
|
|
dmas = <0x2bc 0x00 0x04 0x01 0x40 0x00 0x2bc 0x01 0x04 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x523>;
|
|
};
|
|
|
|
i2c@894000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x24b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x77>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2fc 0x2fd>;
|
|
pinctrl-1 = <0x2fe>;
|
|
dmas = <0x2bc 0x00 0x05 0x03 0x40 0x00 0x2bc 0x01 0x05 0x03 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x524>;
|
|
};
|
|
|
|
spi@894000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x24b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x77>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x2ff 0x300 0x301 0x302>;
|
|
pinctrl-1 = <0x303 0x304>;
|
|
dmas = <0x2bc 0x00 0x05 0x01 0x40 0x00 0x2bc 0x01 0x05 0x01 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x525>;
|
|
};
|
|
|
|
q2spi@894000 {
|
|
compatible = "qcom,q2spi-msm-geni";
|
|
reg = <0x894000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts-extended = <0x01 0x00 0x24b 0x04 0x26 0x17 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x77>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
mosi-pin = <0x26 0x15 0x00>;
|
|
clk-pin = <0x26 0x16 0x00>;
|
|
pinctrl-names = "default\0active\0sleep\0shutdown";
|
|
pinctrl-0 = <0x305 0x306>;
|
|
pinctrl-1 = <0x307 0x308 0x309 0x30a>;
|
|
pinctrl-2 = <0x307 0x30b 0x309 0x30c>;
|
|
pinctrl-3 = <0x305 0x306>;
|
|
dmas = <0x2bc 0x00 0x05 0x0e 0x40 0x00 0x2bc 0x01 0x05 0x0e 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
q2spi-max-frequency = <0x1e84800>;
|
|
status = "disabled";
|
|
phandle = <0x526>;
|
|
};
|
|
|
|
qcom,qup_uart@898000 {
|
|
compatible = "qcom,msm-geni-serial-hs";
|
|
reg = <0x898000 0x4000>;
|
|
reg-names = "se_phys";
|
|
interrupts-extended = <0x01 0x00 0x1cd 0x04 0x26 0x1b 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x79>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0active\0sleep\0shutdown";
|
|
pinctrl-0 = <0x30d 0x30e 0x30f 0x310>;
|
|
pinctrl-1 = <0x311 0x312 0x313 0x314>;
|
|
pinctrl-2 = <0x311 0x312 0x313 0x315>;
|
|
pinctrl-3 = <0x30d 0x30e 0x30f 0x310>;
|
|
qcom,wakeup-byte = <0xfd>;
|
|
qcom,suspend-ignore-children;
|
|
status = "disabled";
|
|
phandle = <0x527>;
|
|
};
|
|
|
|
i2c@89c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x89c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1ce 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x7b>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x316 0x317>;
|
|
pinctrl-1 = <0x318>;
|
|
dmas = <0x2bc 0x00 0x07 0x03 0x40 0x02 0x2bc 0x01 0x07 0x03 0x40 0x02>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x528>;
|
|
};
|
|
|
|
spi@89c000 {
|
|
compatible = "qcom,spi-geni";
|
|
reg = <0x89c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
reg-names = "se_phys";
|
|
interrupts = <0x00 0x1ce 0x04>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x7b>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x319 0x31a 0x31b 0x31c>;
|
|
pinctrl-1 = <0x31d>;
|
|
dmas = <0x2bc 0x00 0x07 0x01 0x40 0x02 0x2bc 0x01 0x07 0x01 0x40 0x02>;
|
|
dma-names = "tx\0rx";
|
|
spi-max-frequency = <0x2faf080>;
|
|
status = "disabled";
|
|
phandle = <0x529>;
|
|
};
|
|
|
|
i3c-master@89c000 {
|
|
compatible = "qcom,geni-i3c";
|
|
reg = <0x89c000 0x4000 0xece0000 0x10000>;
|
|
clock-names = "se-clk";
|
|
clocks = <0x34 0x7b>;
|
|
interconnect-names = "qup-core\0qup-config\0qup-memory";
|
|
interconnects = <0x270 0x28 0x270 0x238 0x78 0x02 0x79 0x218 0x44 0x07 0x45 0x201>;
|
|
pinctrl-names = "default\0sleep\0disable";
|
|
pinctrl-0 = <0x31e 0x31f>;
|
|
pinctrl-1 = <0x320 0x321>;
|
|
pinctrl-2 = <0x322>;
|
|
interrupts-extended = <0x01 0x00 0x1ce 0x04 0x25 0x42 0x04 0x25 0x31 0x04>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x00>;
|
|
qcom,ibi-ctrl-id = <0x09>;
|
|
dmas = <0x2bc 0x00 0x07 0x04 0x40 0x00 0x2bc 0x01 0x07 0x04 0x40 0x00>;
|
|
dma-names = "tx\0rx";
|
|
status = "disabled";
|
|
phandle = <0x52a>;
|
|
};
|
|
};
|
|
|
|
qcom,qupv3_i2c_geni_se@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x9c0000 0x2000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
clock-names = "m-ahb\0s-ahb";
|
|
clocks = <0x34 0x53 0x34 0x53>;
|
|
ranges;
|
|
status = "ok";
|
|
phandle = <0x52b>;
|
|
|
|
i2c@980000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x980000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d0 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x3f 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x323 0x324>;
|
|
pinctrl-1 = <0x325>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x52c>;
|
|
};
|
|
|
|
i2c@984000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x984000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d1 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x41 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x326 0x327>;
|
|
pinctrl-1 = <0x328>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x52d>;
|
|
};
|
|
|
|
i2c@988000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x988000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d2 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x43 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x329 0x32a>;
|
|
pinctrl-1 = <0x32b>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x52e>;
|
|
};
|
|
|
|
i2c@98c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x98c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d3 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x45 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x32c 0x32d>;
|
|
pinctrl-1 = <0x32e>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x52f>;
|
|
};
|
|
|
|
i2c@990000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x990000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d4 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x47 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x32f 0x330>;
|
|
pinctrl-1 = <0x331>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x530>;
|
|
};
|
|
|
|
i2c@994000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x994000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d5 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x49 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x332 0x333>;
|
|
pinctrl-1 = <0x334>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x531>;
|
|
};
|
|
|
|
i2c@998000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x998000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d6 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x4b 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x335 0x336>;
|
|
pinctrl-1 = <0x337>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x532>;
|
|
};
|
|
|
|
i2c@99c000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x99c000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d7 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x4d 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x338 0x339>;
|
|
pinctrl-1 = <0x33a>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x533>;
|
|
};
|
|
|
|
i2c@9a0000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x9a0000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d8 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x4f 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x33b 0x33c>;
|
|
pinctrl-1 = <0x33d>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x534>;
|
|
};
|
|
|
|
i2c@9a4000 {
|
|
compatible = "qcom,i2c-geni";
|
|
reg = <0x9a4000 0x4000>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x1d9 0x04>;
|
|
clock-names = "se-clk\0core-clk";
|
|
clocks = <0x34 0x51 0x34 0x3e>;
|
|
interconnect-names = "qup-core\0qup-config";
|
|
interconnects = <0x270 0x26 0x270 0x236 0x78 0x02 0x79 0x20b>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x33e 0x33f>;
|
|
pinctrl-1 = <0x340>;
|
|
qcom,i2c-hub;
|
|
status = "disabled";
|
|
phandle = <0x535>;
|
|
};
|
|
};
|
|
|
|
ssusb@a600000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0xa600000 0x100000 0x1fc6000 0x04>;
|
|
reg-names = "core_base\0tcsr_dyn_en_dis";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x02>;
|
|
ranges;
|
|
USB3_GDSC-supply = <0x62>;
|
|
clocks = <0x34 0x9c 0x34 0x0b 0x34 0x03 0x34 0x9e 0x34 0xa1>;
|
|
clock-names = "core_clk\0iface_clk\0bus_aggr_clk\0utmi_clk\0sleep_clk";
|
|
resets = <0x34 0x18>;
|
|
reset-names = "core_reset";
|
|
extcon = <0x341>;
|
|
interrupts-extended = <0x01 0x00 0x82 0x04 0x25 0x0e 0x01 0x25 0x0f 0x01 0x25 0x11 0x04>;
|
|
interrupt-names = "pwr_event_irq\0dp_hs_phy_irq\0dm_hs_phy_irq\0ss_phy_irq";
|
|
qcom,use-pdc-interrupts;
|
|
qcom,use-eusb2-phy;
|
|
qcom,dis-sending-cm-l1-quirk;
|
|
qcom,core-clk-rate = <0xbebc200>;
|
|
qcom,core-clk-rate-hs = <0x3f940ab>;
|
|
qcom,core-clk-rate-disconnected = <0x7f28155>;
|
|
interconnect-names = "usb-ddr\0usb-ipa\0ddr-usb";
|
|
interconnects = <0x77 0x35 0x45 0x201 0x77 0x35 0x79 0x20f 0x78 0x02 0x79 0x221>;
|
|
qcom,num-gsi-evt-buffs = <0x03>;
|
|
qcom,gsi-reg-offset = <0xfc 0x110 0x120 0x130 0x144 0x1a4>;
|
|
dummy-supply = <0x75>;
|
|
phandle = <0x536>;
|
|
|
|
dwc3@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x00 0xa600000 0x00 0xd93c>;
|
|
iommus = <0x75 0x40 0x00>;
|
|
qcom,iommu-dma = "atomic";
|
|
memory-region = <0x342>;
|
|
dma-coherent;
|
|
interrupts = <0x00 0x85 0x04>;
|
|
usb-phy = <0x343 0x344>;
|
|
snps,disable-clk-gating;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = [00];
|
|
snps,is-utmi-l1-suspend;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,ssp-u3-u0-quirk;
|
|
tx-fifo-resize;
|
|
num-hc-interrupters = [00 03];
|
|
dr_mode = "otg";
|
|
maximum-speed = "super-speed-plus";
|
|
usb-role-switch;
|
|
phandle = <0x345>;
|
|
};
|
|
};
|
|
|
|
dwc3_mem_region {
|
|
iommu-addresses = <0x345 0x00 0x00 0x00 0x90000000 0x345 0x00 0xf0000000 0xffffffff 0x10000000>;
|
|
phandle = <0x342>;
|
|
};
|
|
|
|
hsphy@88e3000 {
|
|
compatible = "qcom,usb-m31-eusb2-phy";
|
|
reg = <0x88e3000 0x29c 0x88e2000 0x04 0xc278000 0x04>;
|
|
reg-names = "eusb2_phy_base\0eud_enable_reg\0eud_detect_reg";
|
|
vdd-supply = <0x346>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
vdda12-supply = <0x3c>;
|
|
vdd_refgen-supply = <0x347>;
|
|
clocks = <0x35 0x1b 0x5a 0x02>;
|
|
clock-names = "ref_clk_src\0ref_clk";
|
|
resets = <0x34 0x13>;
|
|
reset-names = "phy_reset";
|
|
phandle = <0x343>;
|
|
};
|
|
|
|
ssphy@88e8000 {
|
|
compatible = "qcom,usb-ssphy-qmp-dp-combo";
|
|
reg = <0x88e8000 0x3000>;
|
|
reg-names = "qmp_phy_base";
|
|
vdd-supply = <0x346>;
|
|
qcom,vdd-voltage-level = <0x00 0xd6d80 0xd6d80>;
|
|
qcom,vdd-max-load-uA = <0xb798>;
|
|
core-supply = <0x3c>;
|
|
usb3_dp_phy_gdsc-supply = <0x63>;
|
|
clocks = <0x34 0xa2 0x34 0xa5 0x34 0xa6 0x4f 0x35 0x1b 0x5a 0x03 0x34 0xa4>;
|
|
clock-names = "aux_clk\0pipe_clk\0pipe_clk_mux\0pipe_clk_ext_src\0ref_clk_src\0ref_clk\0com_aux_clk";
|
|
resets = <0x34 0x19 0x34 0x1b>;
|
|
reset-names = "global_phy_reset\0phy_reset";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x348>;
|
|
qcom,qmp-phy-reg-offset = <0x1e14 0x2108 0x2114 0x1e40 0x1e00 0x1e44 0xffff 0x08 0x04 0x1c 0x00 0x10 0x2000>;
|
|
qcom,qmp-phy-init-seq = <0x1000 0xc0 0x1004 0x01 0x1010 0x02 0x1014 0x16 0x1018 0x36 0x101c 0x04 0x1020 0x16 0x1024 0x41 0x1028 0x41 0x102c 0x00 0x1030 0x55 0x1034 0x75 0x1038 0x01 0x103c 0x01 0x1048 0x25 0x104c 0x02 0x1050 0x5c 0x1054 0x0f 0x1058 0x5c 0x105c 0x0f 0x1060 0xc0 0x1064 0x01 0x1070 0x02 0x1074 0x16 0x1078 0x36 0x1080 0x08 0x1084 0x1a 0x1088 0x41 0x108c 0x00 0x1090 0x55 0x1094 0x75 0x1098 0x01 0x10a8 0x25 0x10ac 0x02 0x10bc 0x0a 0x10c0 0x01 0x10cc 0x62 0x10d0 0x02 0x10e8 0x0c 0x1110 0x1a 0x1124 0x14 0x1140 0x04 0x1170 0x20 0x1174 0x16 0x11a4 0xb6 0x11a8 0x4a 0x11ac 0x36 0x11b4 0x0c 0x1434 0x00 0x1438 0x00 0x143c 0x1f 0x1440 0x09 0x1484 0xf5 0x148c 0x11 0x1490 0x31 0x1494 0x5f 0x14a4 0x12 0x14e4 0x21 0x1608 0x0a 0x1614 0x06 0x1630 0x2f 0x1634 0x7f 0x163c 0xff 0x1640 0x0f 0x1644 0x99 0x164c 0x08 0x1650 0x08 0x1654 0x00 0x1658 0x0a 0x1660 0x20 0x16d4 0x54 0x16d8 0x0f 0x16dc 0x13 0x16ec 0x0e 0x16f0 0x4a 0x16f4 0x0a 0x16f8 0x07 0x16fc 0x00 0x1710 0x27 0x1718 0x0c 0x171c 0x04 0x1724 0x0e 0x175c 0x3f 0x1760 0xbf 0x1764 0xff 0x1768 0xdf 0x176c 0xed 0x1770 0x19 0x1774 0x09 0x1778 0x91 0x177c 0xb7 0x1780 0xaa 0x17a0 0x04 0x17a4 0x38 0x17a8 0x0c 0x17b0 0x10 0x17e4 0x14 0x17f8 0x08 0x1834 0x00 0x1838 0x00 0x183c 0x1f 0x1840 0x09 0x1884 0xf5 0x188c 0x11 0x1890 0x31 0x1894 0x5f 0x18a4 0x12 0x18e4 0x05 0x1a08 0x0a 0x1a14 0x06 0x1a30 0x2f 0x1a34 0x7f 0x1a3c 0xff 0x1a40 0x0f 0x1a44 0x99 0x1a4c 0x08 0x1a50 0x08 0x1a54 0x00 0x1a58 0x0a 0x1a60 0x20 0x1ad4 0x54 0x1ad8 0x0f 0x1adc 0x13 0x1aec 0x0e 0x1af0 0x4a 0x1af4 0x0a 0x1af8 0x07 0x1afc 0x00 0x1b10 0x27 0x1b18 0x0c 0x1b1c 0x04 0x1b24 0x0e 0x1b5c 0x3f 0x1b60 0xbf 0x1b64 0xff 0x1b68 0xdf 0x1b6c 0xed 0x1b70 0x19 0x1b74 0x09 0x1b78 0x91 0x1b7c 0xb7 0x1b80 0xaa 0x1ba0 0x04 0x1ba4 0x38 0x1ba8 0x0c 0x1bb0 0x10 0x1be4 0x14 0x1bf8 0x08 0x1ec4 0xc4 0x1ec8 0x89 0x1ecc 0x20 0x1ed8 0x13 0x1edc 0x21 0x1f88 0x55 0x1f90 0xe7 0x1f94 0x03 0x1fb0 0x0a 0x1fc0 0x88 0x1fc4 0x13 0x1fd0 0x0c 0x1fdc 0x4b 0x1fec 0x10 0x2118 0xf8 0x213c 0x07 0x2140 0x40 0x2144 0x00>;
|
|
phandle = <0x344>;
|
|
};
|
|
|
|
usb_audio_qmi_dev {
|
|
compatible = "qcom,usb-audio-qmi-dev";
|
|
iommus = <0x75 0x100b 0x00>;
|
|
qcom,iommu-dma = "disabled";
|
|
qcom,usb-audio-stream-id = <0x0b>;
|
|
qcom,usb-audio-intr-num = <0x02>;
|
|
};
|
|
|
|
tsens0@c228000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc228000 0x1ff 0xc222000 0x1ff>;
|
|
#qcom,sensors = <0x0f>;
|
|
interrupts = <0x00 0x303 0x04 0x00 0x1e4 0x04>;
|
|
interrupt-names = "uplow\0critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
tsens1@c229000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc229000 0x1ff 0xc223000 0x1ff>;
|
|
#qcom,sensors = <0x0f>;
|
|
interrupts = <0x00 0x304 0x04 0x00 0x1e5 0x04>;
|
|
interrupt-names = "uplow\0critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
tsens2@c22a000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc22a000 0x1ff 0xc224000 0x1ff>;
|
|
#qcom,sensors = <0x10>;
|
|
interrupts = <0x00 0x305 0x04 0x00 0x1e6 0x04>;
|
|
interrupt-names = "uplow\0critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
tsens3@c22b000 {
|
|
compatible = "qcom,tsens-v2";
|
|
reg = <0xc22b000 0x1ff 0xc225000 0x1ff>;
|
|
#qcom,sensors = <0x01>;
|
|
interrupts = <0x00 0x306 0x04 0x00 0x1e7 0x04>;
|
|
interrupt-names = "uplow\0critical";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0xe3>;
|
|
};
|
|
|
|
qcom,cpu-pause {
|
|
compatible = "qcom,thermal-pause";
|
|
|
|
cpu0-pause {
|
|
qcom,cpus = <0x10>;
|
|
qcom,cdev-alias = "thermal-pause-1";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
cpu1-pause {
|
|
qcom,cpus = <0x11>;
|
|
qcom,cdev-alias = "thermal-pause-2";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
cpu2-pause {
|
|
qcom,cpus = <0x12>;
|
|
qcom,cdev-alias = "thermal-pause-4";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
cpu3-pause {
|
|
qcom,cpus = <0x13>;
|
|
qcom,cdev-alias = "thermal-pause-8";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
cpu4-pause {
|
|
qcom,cpus = <0x14>;
|
|
qcom,cdev-alias = "thermal-pause-10";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
cpu5-pause {
|
|
qcom,cpus = <0x15>;
|
|
qcom,cdev-alias = "thermal-pause-20";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
cpu6-pause {
|
|
qcom,cpus = <0x16>;
|
|
qcom,cdev-alias = "thermal-pause-40";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
cpu7-pause {
|
|
qcom,cpus = <0x17>;
|
|
qcom,cdev-alias = "thermal-pause-80";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
apc0-mx-cx-pause {
|
|
qcom,cpus = <0x12 0x13 0x14 0x15>;
|
|
qcom,cdev-alias = "thermal-pause-3C";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x537>;
|
|
};
|
|
|
|
apc1-mx-cx-pause {
|
|
qcom,cpus = <0x16 0x17>;
|
|
qcom,cdev-alias = "thermal-pause-C0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x538>;
|
|
};
|
|
|
|
pause-cpu0 {
|
|
qcom,cpus = <0x10>;
|
|
qcom,cdev-alias = "pause-cpu0";
|
|
};
|
|
|
|
pause-cpu1 {
|
|
qcom,cpus = <0x11>;
|
|
qcom,cdev-alias = "pause-cpu1";
|
|
};
|
|
|
|
pause-cpu2 {
|
|
qcom,cpus = <0x12>;
|
|
qcom,cdev-alias = "pause-cpu2";
|
|
};
|
|
|
|
pause-cpu3 {
|
|
qcom,cpus = <0x13>;
|
|
qcom,cdev-alias = "pause-cpu3";
|
|
};
|
|
|
|
pause-cpu4 {
|
|
qcom,cpus = <0x14>;
|
|
qcom,cdev-alias = "pause-cpu4";
|
|
};
|
|
|
|
pause-cpu5 {
|
|
qcom,cpus = <0x15>;
|
|
qcom,cdev-alias = "pause-cpu5";
|
|
};
|
|
|
|
pause-cpu6 {
|
|
qcom,cpus = <0x16>;
|
|
qcom,cdev-alias = "pause-cpu6";
|
|
};
|
|
|
|
pause-cpu7 {
|
|
qcom,cpus = <0x17>;
|
|
qcom,cdev-alias = "pause-cpu7";
|
|
};
|
|
};
|
|
|
|
qcom,cpu-hotplug {
|
|
compatible = "qcom,cpu-hotplug";
|
|
|
|
cpu0-hotplug {
|
|
qcom,cpu = <0x10>;
|
|
qcom,cdev-alias = "cpu-hotplug0";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
cpu1-hotplug {
|
|
qcom,cpu = <0x11>;
|
|
qcom,cdev-alias = "cpu-hotplug1";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
cpu2-hotplug {
|
|
qcom,cpu = <0x12>;
|
|
qcom,cdev-alias = "cpu-hotplug2";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
cpu3-hotplug {
|
|
qcom,cpu = <0x13>;
|
|
qcom,cdev-alias = "cpu-hotplug3";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
cpu4-hotplug {
|
|
qcom,cpu = <0x14>;
|
|
qcom,cdev-alias = "cpu-hotplug4";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xb6>;
|
|
};
|
|
|
|
cpu5-hotplug {
|
|
qcom,cpu = <0x15>;
|
|
qcom,cdev-alias = "cpu-hotplug5";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
cpu6-hotplug {
|
|
qcom,cpu = <0x16>;
|
|
qcom,cdev-alias = "cpu-hotplug6";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
cpu7-hotplug {
|
|
qcom,cpu = <0x17>;
|
|
qcom,cdev-alias = "cpu-hotplug7";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xc9>;
|
|
};
|
|
};
|
|
|
|
thermal-ddr-freq-table {
|
|
qcom,freq-tbl = <0x1fef00>;
|
|
phandle = <0x349>;
|
|
};
|
|
|
|
qcom,ddr-cdev {
|
|
compatible = "qcom,ddr-cooling-device";
|
|
#cooling-cells = <0x02>;
|
|
qcom,bus-width = <0x04>;
|
|
qcom,freq-table = <0x349>;
|
|
interconnects = <0x45 0x03 0x45 0x201>;
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
qcom,devfreq-cdev {
|
|
compatible = "qcom,devfreq-cdev";
|
|
qcom,devfreq = <0xd0>;
|
|
};
|
|
|
|
qcom,cpufreq-cdev {
|
|
compatible = "qcom,cpufreq-cdev";
|
|
|
|
cpu-cluster0 {
|
|
qcom,cpus = <0x10 0x11 0x12 0x13 0x14 0x15>;
|
|
};
|
|
|
|
cpu-cluster1 {
|
|
qcom,cpus = <0x16 0x17>;
|
|
};
|
|
};
|
|
|
|
qmi-tmd-devices {
|
|
compatible = "qcom,qmi-cooling-devices";
|
|
phandle = <0x539>;
|
|
|
|
cdsp {
|
|
qcom,instance-id = <0x43>;
|
|
|
|
cdsp {
|
|
qcom,qmi-dev-name = "cdsp_sw";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53a>;
|
|
};
|
|
|
|
cdsp_sw_hvx {
|
|
qcom,qmi-dev-name = "cdsp_sw_hvx";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53b>;
|
|
};
|
|
|
|
cdsp_sw_hmx {
|
|
qcom,qmi-dev-name = "cdsp_sw_hmx";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53c>;
|
|
};
|
|
|
|
cdsp_hw {
|
|
qcom,qmi-dev-name = "cdsp_hw";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53d>;
|
|
};
|
|
};
|
|
|
|
modem {
|
|
qcom,instance-id = <0x00>;
|
|
|
|
modem_lte_dsc {
|
|
qcom,qmi-dev-name = "modem_lte_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xd9>;
|
|
};
|
|
|
|
modem_nr_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xdb>;
|
|
};
|
|
|
|
modem_nr_scg_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_scg_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0xda>;
|
|
};
|
|
|
|
modem_lte_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_lte_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53e>;
|
|
};
|
|
|
|
modem_nr_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x53f>;
|
|
};
|
|
|
|
modem_nr_scg_sub1_dsc {
|
|
qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x540>;
|
|
};
|
|
|
|
pa_lte_sdr0_dsc {
|
|
qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x541>;
|
|
};
|
|
|
|
pa_nr_sdr0_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x542>;
|
|
};
|
|
|
|
pa_nr_sdr0_scg_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x543>;
|
|
};
|
|
|
|
pa_lte_sdr0_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x544>;
|
|
};
|
|
|
|
pa_nr_sdr0_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x545>;
|
|
};
|
|
|
|
pa_nr_sdr0_scg_sub1_dsc {
|
|
qcom,qmi-dev-name = "pa_nr_sdr0_scg_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x546>;
|
|
};
|
|
|
|
mmw0_dsc {
|
|
qcom,qmi-dev-name = "mmw0_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x547>;
|
|
};
|
|
|
|
mmw1_dsc {
|
|
qcom,qmi-dev-name = "mmw1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x548>;
|
|
};
|
|
|
|
mmw2_dsc {
|
|
qcom,qmi-dev-name = "mmw2_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x549>;
|
|
};
|
|
|
|
mmw3_dsc {
|
|
qcom,qmi-dev-name = "mmw3_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54a>;
|
|
};
|
|
|
|
mmw0_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw0_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54b>;
|
|
};
|
|
|
|
mmw1_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw1_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54c>;
|
|
};
|
|
|
|
mmw2_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw2_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54d>;
|
|
};
|
|
|
|
mmw3_sub1_dsc {
|
|
qcom,qmi-dev-name = "mmw3_sub1_dsc";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54e>;
|
|
};
|
|
|
|
modem_vdd {
|
|
qcom,qmi-dev-name = "cpuv_restriction_cold";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x54f>;
|
|
};
|
|
|
|
modem_bcl {
|
|
qcom,qmi-dev-name = "bcl";
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x550>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,userspace-cdev {
|
|
compatible = "qcom,userspace-cooling-devices";
|
|
|
|
display-fps {
|
|
qcom,max-level = <0x10>;
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x551>;
|
|
};
|
|
};
|
|
|
|
limits-stat {
|
|
compatible = "qcom,limits-stat";
|
|
qcom,limits-stat-sensor-names = "aoss-0\0cpu-0-0-0\0cpu-0-0-1\0cpu-0-1-0\0cpu-0-1-1\0cpu-0-2-0\0cpu-0-2-1\0cpu-0-3-0\0cpu-0-3-1\0cpu-0-4-0\0cpu-0-4-1\0cpu-0-5-0\0cpu-0-5-1\0cpuss-0-0\0cpuss-0-1\0aoss-1\0cpu-1-0-0\0cpu-1-0-1\0cpu-1-1-0\0cpu-1-1-1\0cpuss-1-0\0cpuss-1-1\0nsphvx-0\0nsphvx-1\0nsphvx-2\0nsphmx-0\0nsphmx-1\0nsphmx-2\0nsphmx-3\0ddr\0aoss-2\0gpuss-0\0gpuss-1\0gpuss-2\0gpuss-3\0gpuss-4\0gpuss-5\0gpuss-6\0gpuss-7\0mdmss-0\0mdmss-1\0mdmss-2\0mdmss-3\0camera-0\0camera-1\0video\0aoss-3\0pmih010x-ibat-lvl0\0vbat";
|
|
phandle = <0x552>;
|
|
};
|
|
|
|
qmi-ts-sensors {
|
|
compatible = "qcom,qmi-sensors";
|
|
#thermal-sensor-cells = <0x01>;
|
|
phandle = <0x99>;
|
|
|
|
modem {
|
|
qcom,instance-id = <0x00>;
|
|
qcom,qmi-sensor-names = "sdr0_pa\0sdr0\0mmw0\0mmw1\0mmw2\0mmw3\0mmw_ific0";
|
|
};
|
|
};
|
|
|
|
pcie@1c00000 {
|
|
compatible = "qcom,pci-msm";
|
|
device_type = "pci";
|
|
reg = <0x1c00000 0x3000 0x1c06000 0x2000 0x40000000 0xf1d 0x40000f20 0xa8 0x40001000 0x1000 0x40100000 0x100000 0x1d07000 0x7000>;
|
|
reg-names = "parf\0phy\0dm_core\0elbi\0iatu\0conf\0pcie_sm";
|
|
cell-index = <0x00>;
|
|
linux,pci-domain = <0x00>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
ranges = <0x1000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x2000000 0x00 0x40300000 0x40300000 0x00 0x3d00000>;
|
|
interrupts = <0x00 0x8c 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04>;
|
|
interrupt-names = "int_global_int\0int_a\0int_b\0int_c\0int_d";
|
|
msi-map = <0x00 0x7c 0x1400 0x01 0x100 0x7c 0x1401 0x01>;
|
|
perst-gpio = <0x26 0x66 0x00>;
|
|
wake-gpio = <0x26 0x68 0x00>;
|
|
pinctrl-names = "default\0sleep";
|
|
pinctrl-0 = <0x34a 0x34b 0x34c>;
|
|
pinctrl-1 = <0x34a 0x34d 0x34c>;
|
|
gdsc-phy-vdd-supply = <0x34e>;
|
|
qcom,bw-scale = <0x40 0x40 0x124f800 0x40 0x40 0x124f800 0x100 0x100 0x5f5e100>;
|
|
interconnect-names = "icc_path";
|
|
interconnects = <0x26a 0x138b 0x45 0x1588>;
|
|
resets = <0x34 0x06 0x34 0x09>;
|
|
reset-names = "pcie_0_core_reset\0pcie_0_phy_reset";
|
|
dma-coherent;
|
|
qcom,smmu-sid-base = <0x1400>;
|
|
iommu-map = <0x00 0x75 0x1400 0x01 0x100 0x75 0x1401 0x01>;
|
|
qcom,boot-option = <0x01>;
|
|
qcom,aux-clk-freq = <0x14>;
|
|
qcom,l1-2-th-scale = <0x02>;
|
|
qcom,l1-2-th-value = <0x96>;
|
|
qcom,ep-latency = <0x0a>;
|
|
qcom,num-parf-testbus-sel = <0xb9>;
|
|
qcom,pcie-phy-ver = <0x5e>;
|
|
qcom,phy-status-offset = <0x414>;
|
|
qcom,phy-status-bit = <0x06>;
|
|
qcom,phy-power-down-offset = <0x440>;
|
|
qcom,phy-sequence = <0x440 0x03 0x00 0xc0 0x01 0x00 0xcc 0x62 0x00 0xd0 0x02 0x00 0x60 0xf8 0x00 0x64 0x01 0x00 0x00 0x93 0x00 0x04 0x01 0x00 0xe0 0x90 0x00 0xe4 0x82 0x00 0xf4 0x07 0x00 0x70 0x02 0x00 0x10 0x02 0x00 0x74 0x16 0x00 0x14 0x16 0x00 0x78 0x36 0x00 0x18 0x36 0x00 0x110 0x08 0x00 0xbc 0x0a 0x00 0x120 0x42 0x00 0x80 0x04 0x00 0x84 0x0d 0x00 0x20 0x0a 0x00 0x24 0x1a 0x00 0x88 0x41 0x00 0x28 0x34 0x00 0x90 0xab 0x00 0x94 0xaa 0x00 0x98 0x01 0x00 0x30 0x55 0x00 0x34 0x55 0x00 0x38 0x01 0x00 0x140 0x14 0x00 0x164 0x34 0x00 0x3c 0x01 0x00 0x1c 0x04 0x00 0x174 0x16 0x00 0x1bc 0x0f 0x00 0x170 0xa0 0x00 0x13a4 0x38 0x00 0x12dc 0x11 0x00 0x1360 0xbf 0x00 0x1364 0xbf 0x00 0x1368 0xb7 0x00 0x136c 0xea 0x00 0x135c 0x3f 0x00 0x1374 0x09 0x00 0x1378 0x49 0x00 0x137c 0x1b 0x00 0x1380 0x8f 0x00 0x1370 0xd1 0x00 0x1388 0x09 0x00 0x138c 0x49 0x00 0x1390 0x1b 0x00 0x1394 0x8f 0x00 0x1384 0xd1 0x00 0x12c4 0x3e 0x00 0x12c8 0x1e 0x00 0x12cc 0xd2 0x00 0x1208 0x09 0x00 0x1214 0x05 0x00 0x124c 0x08 0x00 0x1250 0x08 0x00 0x12d8 0x09 0x00 0x1318 0x1c 0x00 0x131c 0x60 0x00 0x12f8 0x07 0x00 0x13f8 0x08 0x00 0x1800 0x00 0x00 0x1084 0x35 0x00 0x108c 0x10 0x00 0x1090 0x31 0x00 0x1094 0x7f 0x00 0x10e4 0x02 0x00 0x1040 0x08 0x00 0x103c 0x14 0x00 0x1ba4 0x38 0x00 0x1adc 0x11 0x00 0x1b60 0xbf 0x00 0x1b64 0xbf 0x00 0x1b68 0xb7 0x00 0x1b6c 0xea 0x00 0x1b5c 0x3f 0x00 0x1b74 0x09 0x00 0x1b78 0x49 0x00 0x1b7c 0x1b 0x00 0x1b80 0x8f 0x00 0x1b70 0xd1 0x00 0x1b88 0x09 0x00 0x1b8c 0x49 0x00 0x1b90 0x1b 0x00 0x1b94 0x8f 0x00 0x1b84 0xd1 0x00 0x1ac4 0x3e 0x00 0x1ac8 0x1e 0x00 0x1acc 0xd2 0x00 0x1a08 0x09 0x00 0x1a14 0x05 0x00 0x1a4c 0x08 0x00 0x1a50 0x08 0x00 0x1ad8 0x09 0x00 0x1b18 0x1c 0x00 0x1b1c 0x60 0x00 0x1af8 0x07 0x00 0x1bf8 0x08 0x00 0x1884 0x35 0x00 0x188c 0x10 0x00 0x1890 0x31 0x00 0x1894 0x7f 0x00 0x18e4 0x02 0x00 0x1840 0x08 0x00 0x183c 0x14 0x00 0x4dc 0x05 0x00 0x588 0x77 0x00 0x598 0x0b 0x00 0x8a4 0x1e 0x00 0x8f4 0x27 0x00 0x5e4 0x0f 0x00 0x80c 0x1d 0x00 0x814 0x07 0x00 0x820 0xc1 0x00 0x894 0x00 0x00 0x5d0 0x8c 0x00 0x568 0x17 0x00 0x570 0x2e 0x00 0x400 0x00 0x00 0x444 0x03 0x00>;
|
|
qcom,drv-name = "cesta";
|
|
qcom,drv-l1ss-timeout-us = <0x1388>;
|
|
qcom,pcie-clkreq-offset = <0x2c48>;
|
|
qcom,pcie-clkreq-pin = <0x67>;
|
|
qcom,pcie-sm-branch-offset = <0x1000>;
|
|
qcom,pcie-sm-start-offset = <0x1090>;
|
|
qcom,pcie-sm-seq = <0x1c018081 0x70074002 0x50028000 0x28007003 0x80804002 0x70021c01 0x18001802 0x70005000 0x10004000 0x80814002 0x18001c01 0x1c018080 0x100>;
|
|
qcom,pcie-sm-branch-seq = <0x04 0x1c 0x24 0x2c 0x00 0x00 0x00>;
|
|
qcom,pcie-sm-debug = <0x1040 0x1048 0x1050 0x1058 0x1060 0x1068 0x1070 0x1078 0x1080 0x1088 0x1090 0x1094 0x1098 0x109c>;
|
|
phandle = <0x553>;
|
|
|
|
pcie0_rp {
|
|
reg = <0x00 0x00 0x00 0x00 0x00>;
|
|
phandle = <0x554>;
|
|
};
|
|
};
|
|
|
|
qcom,pcie0_msi@16110040 {
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
reg = <0x17110040 0x00>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x300 0x01 0x00 0x301 0x01 0x00 0x302 0x01 0x00 0x303 0x01 0x00 0x304 0x01 0x00 0x305 0x01 0x00 0x306 0x01 0x00 0x307 0x01 0x00 0x308 0x01 0x00 0x309 0x01 0x00 0x30a 0x01 0x00 0x30b 0x01 0x00 0x30c 0x01 0x00 0x30d 0x01 0x00 0x30e 0x01 0x00 0x30f 0x01 0x00 0x310 0x01 0x00 0x311 0x01 0x00 0x312 0x01 0x00 0x313 0x01 0x00 0x314 0x01 0x00 0x315 0x01 0x00 0x316 0x01 0x00 0x317 0x01 0x00 0x318 0x01 0x00 0x319 0x01 0x00 0x31a 0x01 0x00 0x31b 0x01 0x00 0x31c 0x01 0x00 0x31d 0x01 0x00 0x31e 0x01 0x00 0x31f 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x555>;
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
|
|
qcom,smem-states = <0x34f 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_2_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
|
|
interrupts-extended = <0x350 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_out {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-out";
|
|
qcom,smem-states = <0x351 0x00>;
|
|
qcom,smem-state-names = "rdbg-smp2p-out";
|
|
};
|
|
|
|
qcom,smp2p_interrupt_rdbg_5_in {
|
|
compatible = "qcom,smp2p-interrupt-rdbg-5-in";
|
|
interrupts-extended = <0x352 0x00 0x00>;
|
|
interrupt-names = "rdbg-smp2p-in";
|
|
};
|
|
|
|
walt {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
qcom,cycle-cntr {
|
|
compatible = "qcom,gclk";
|
|
reg = <0x18880400 0x08 0x19880400 0x08>;
|
|
reg-names = "freq-domain0\0freq-domain1";
|
|
};
|
|
};
|
|
|
|
ipcc-self-ping-apss {
|
|
compatible = "qcom,ipcc-self-ping";
|
|
interrupts-extended = <0x21 0x08 0x02 0x04>;
|
|
mboxes = <0x21 0x08 0x02>;
|
|
phandle = <0x556>;
|
|
};
|
|
|
|
qcom,mmrm {
|
|
phandle = <0x562>;
|
|
mmrm-client-info = <0x01 0x0a 0x30b959 0x151ec 0x01 0x01 0x2b 0x139cee 0xd99a 0x03 0x01 0x39 0x3dd30 0x4290 0x01 0x01 0x3c 0x3dd30 0x4290 0x01 0x01 0x3f 0x43063 0x272c 0x02 0x01 0x45 0x2fe7605 0x606ea 0x01 0x01 0x4b 0x86a3e 0x4290 0x04 0x01 0x4f 0x3c198d5 0x61cee 0x01 0x01 0x6c 0x10bf375 0x3af1b 0x01 0x01 0x71 0x10bf375 0x3af1b 0x01 0x01 0x76 0x10c9fbf 0x3c938 0x01 0x01 0x35 0x8000 0x199a 0x01 0x01 0x69 0xe667 0x2e15 0x01 0x01 0x14 0x00 0x290 0x01 0x01 0x16 0x00 0x290 0x01 0x01 0x18 0x00 0x290 0x01 0x01 0x1d 0x10000 0x7af 0x01 0x01 0x1f 0x199a 0x00 0x01 0x01 0x21 0x199a 0x00 0x01 0x01 0x23 0x199a 0x00 0x01 0x01 0x25 0x199a 0x00 0x01 0x01 0x27 0x199a 0x00 0x01 0x01 0x29 0x199a 0x00 0x01 0x01 0x1a 0x4ccd 0x8290 0x0a 0x01 0x42 0x40000 0x3ae2 0x02 0x02 0x03 0x2d2a8f6 0x6374c 0x01 0x03 0x42 0x1490000 0x4e148 0x01 0x04 0x03 0x1be12f2 0xccf9e 0x01>;
|
|
scaling-fact-leak = <0xca148 0xeca3e 0x114a3e 0x13970b 0x160ccd 0x186148>;
|
|
scaling-fact-dyn = <0x9c29 0xbd71 0xe148 0x10290 0x12148 0x13d71>;
|
|
mm-rail-fact-volt = <0x926f 0xa0c5 0xaf1b 0xba5f 0xc49c 0xcccd>;
|
|
mm-rail-corners = "lowsvs\0svs\0svsl1\0nom\0noml1\0turbo";
|
|
mmrm-peak-threshold = <0x2710>;
|
|
status = "okay";
|
|
compatible = "qcom,msm-mmrm\0qcom,sun-mmrm";
|
|
};
|
|
|
|
qcom,cvp@ab00000 {
|
|
phandle = <0x569>;
|
|
cvp,firmware-name = "evass";
|
|
aon_mappings = <0xff80f000 0x1000 0xabe0000>;
|
|
hwmutex_mappings = <0xffb00000 0x2000 0x1f4a000>;
|
|
aon_timer_mappings = <0xffa00000 0x1000 0xc220000>;
|
|
ipclite_mappings = <0xfe500000 0x100000 0x82600000>;
|
|
memory-region = <0x36b>;
|
|
soc_ver = <0x10000>;
|
|
pas-id = <0x1a>;
|
|
qcom,gcc-reg = <0x110000 0x90000>;
|
|
qcom,ipcc-reg = <0x400000 0x100000>;
|
|
qcom,reg-presets = <0xb0088 0x00>;
|
|
reset-power-status = <0x00>;
|
|
reset-names = "cvp_core_reset";
|
|
resets = <0x56 0x03>;
|
|
qcom,allowed-clock-rates = <0x14dc9380 0x17d78400 0x1ad27480 0x1dcd6500 0x20c85580>;
|
|
qcom,clock-configs = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01>;
|
|
qcom,proxy-clock-names = "cvp_axi_clock\0core_axi_clock\0sleep_clk\0cvp_freerun_clk\0core_freerun_clk\0cvp_clk\0core_clk\0eva_cc_mvs0_clk_src";
|
|
clocks = <0x34 0x13 0x34 0x12 0x56 0x0c 0x56 0x09 0x56 0x05 0x56 0x07 0x56 0x02 0x56 0x03>;
|
|
clock-ids = <0x13 0x12 0x0c 0x09 0x05 0x07 0x02 0x03>;
|
|
clock-names = "cvp_axi_clock\0core_axi_clock\0sleep_clk\0cvp_freerun_clk\0core_freerun_clk\0cvp_clk\0core_clk\0eva_cc_mvs0_clk_src";
|
|
cvp-core-supply = <0x43a>;
|
|
cvp-supply = <0x5e>;
|
|
cache-slice-names = "cvpfw\0cvp";
|
|
interrupts = <0x00 0x5e 0x04 0x00 0x5f 0x04>;
|
|
reg = <0xab00000 0x100000>;
|
|
status = "ok";
|
|
compatible = "qcom,msm-cvp\0qcom,sun-cvp";
|
|
|
|
cvp_cnoc {
|
|
interconnect-names = "eva-cfg";
|
|
interconnects = <0x78 0x02 0x79 0x209>;
|
|
qcom,bus-range-kbps = <0x3e8 0x3e8>;
|
|
qcom,bus-governor = "performance";
|
|
compatible = "qcom,msm-cvp,bus";
|
|
};
|
|
|
|
cvp_bus_ddr {
|
|
interconnect-names = "eva-ddr";
|
|
interconnects = <0x5c 0x20 0x45 0x201>;
|
|
qcom,bus-range-kbps = <0x3e8 0x63af88>;
|
|
qcom,bus-governor = "performance";
|
|
compatible = "qcom,msm-cvp,bus";
|
|
};
|
|
|
|
cvp_camera_cb {
|
|
qti,smmu-proxy-cb-id = <0x02>;
|
|
buffer-types = <0xfff>;
|
|
label = "cvp_camera";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_non_secure_cb_group {
|
|
phandle = <0x567>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
};
|
|
|
|
cvp_iommu_region_partition {
|
|
phandle = <0x568>;
|
|
iommu-addresses = <0x563 0x00 0x4b000000 0x563 0xdb000000 0x25000000 0x564 0x00 0x4b000000 0x564 0xdb000000 0x25000000 0x565 0x00 0x1000000 0x565 0x26800000 0xd9800000 0x566 0x00 0x26800000 0x566 0x4b000000 0xb5000000>;
|
|
};
|
|
|
|
cvp_non_secure_cb {
|
|
phandle = <0x563>;
|
|
memory-region = <0x568>;
|
|
qcom,iommu-group = <0x567>;
|
|
dma-coherent;
|
|
buffer-types = <0xfff>;
|
|
iommus = <0x75 0x1920 0x20>;
|
|
label = "cvp_hlos";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_secure_nonpixel_cb {
|
|
phandle = <0x565>;
|
|
qcom,iommu-vmid = <0x0b>;
|
|
memory-region = <0x568>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
buffer-types = <0x741>;
|
|
iommus = <0x75 0x1924 0x20>;
|
|
label = "cvp_sec_nonpixel";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_secure_pixel_cb {
|
|
phandle = <0x566>;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
memory-region = <0x568>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
buffer-types = <0x106>;
|
|
iommus = <0x75 0x1923 0x00>;
|
|
label = "cvp_sec_pixel";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
cvp_dsp_cb {
|
|
phandle = <0x564>;
|
|
memory-region = <0x568>;
|
|
qcom,iommu-group = <0x567>;
|
|
buffer-types = <0xfff>;
|
|
iommus = <0x75 0x1920 0x20>;
|
|
label = "cvp_dsp";
|
|
compatible = "qcom,msm-cvp,context-bank";
|
|
};
|
|
|
|
qcom,msm-cvp,mem_cdsp {
|
|
memory-region = <0x371>;
|
|
compatible = "qcom,msm-cvp,mem-cdsp";
|
|
};
|
|
};
|
|
|
|
qcom,ipcc_compute_l0@443000 {
|
|
phandle = <0x56a>;
|
|
#mbox-cells = <0x02>;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
interrupts = <0x00 0xe6 0x04>;
|
|
reg = <0x443000 0x1000>;
|
|
compatible = "qcom,ipcc";
|
|
};
|
|
|
|
ipclite {
|
|
ranges;
|
|
feature_mask_high = <0x00>;
|
|
feature_mask_low = <0x03>;
|
|
minor_version = <0x00>;
|
|
major_version = <0x01>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
hwlocks = <0x18 0x0b>;
|
|
memory-region = <0x95>;
|
|
compatible = "qcom,ipclite";
|
|
|
|
apss {
|
|
phandle = <0x56b>;
|
|
label = "apss";
|
|
qcom,remote-pid = <0x00>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x08 0x00 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x08 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0xf000 0x01 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0xf000 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x08 0x02 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x08 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x08 0x03 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x08 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x08 0x04 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x08 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x08 0x05 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x08 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cdsp {
|
|
phandle = <0x56c>;
|
|
label = "cdsp";
|
|
qcom,remote-pid = <0x05>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x06 0x00 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x06 0x01 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x06 0x02 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x06 0x03 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x06 0x04 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x06 0x05 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x06 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cvp {
|
|
phandle = <0x56d>;
|
|
label = "cvp";
|
|
qcom,remote-pid = <0x06>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x0a 0x00 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x0a 0x01 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x0a 0x02 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x0a 0x03 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x0a 0x04 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x0a 0x05 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0a 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
|
|
cam {
|
|
phandle = <0x56e>;
|
|
label = "cam";
|
|
qcom,remote-pid = <0x07>;
|
|
|
|
ipclite_signal_0 {
|
|
interrupts = <0x0b 0x00 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x00>;
|
|
index = <0x00>;
|
|
};
|
|
|
|
ipclite_signal_1 {
|
|
interrupts = <0x0b 0x01 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x01>;
|
|
index = <0x01>;
|
|
};
|
|
|
|
ipclite_signal_2 {
|
|
interrupts = <0x0b 0x02 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x02>;
|
|
index = <0x02>;
|
|
};
|
|
|
|
ipclite_signal_3 {
|
|
interrupts = <0x0b 0x03 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x03>;
|
|
index = <0x03>;
|
|
};
|
|
|
|
ipclite_signal_4 {
|
|
interrupts = <0x0b 0x04 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x04>;
|
|
index = <0x04>;
|
|
};
|
|
|
|
ipclite_signal_5 {
|
|
interrupts = <0x0b 0x05 0x01>;
|
|
interrupt-parent = <0x56a>;
|
|
mboxes = <0x56a 0x0b 0x05>;
|
|
index = <0x05>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,hw-fence {
|
|
phandle = <0x56f>;
|
|
qcom,hw-fence-client-type-ife0-extra = <0x14 0x1c 0x01 0x01>;
|
|
qcom,hw-fence-client-type-ife0 = <0x01 0x01 0x80 0x01>;
|
|
qcom,hw-fence-client-type-vpu = <0x01 0x02 0x320 0x00>;
|
|
qcom,hw-fence-client-type-ipe = <0x01 0x02 0x320 0x00>;
|
|
qcom,hw-fence-client-type-dpu = <0x06 0x02 0x80 0x01>;
|
|
qcom,hw-fence-ipc-ver = <0x20a02>;
|
|
qcom,qtime-reg = <0xc221000 0x1000>;
|
|
qcom,ipcc-reg = <0x400000 0x140000>;
|
|
qcom,hw-fence-queue-entries = <0x320>;
|
|
qcom,hw-fence-table-entries = <0x2000>;
|
|
soccp_controller = <0x465>;
|
|
dma-coherent;
|
|
iommus = <0x75 0x562 0x01>;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-controller;
|
|
interrupts = <0x00 0x46 0x04>;
|
|
status = "ok";
|
|
compatible = "qcom,msm-hw-fence";
|
|
|
|
hw_fence@1 {
|
|
shared-buffer = <0x36e>;
|
|
qcom,master;
|
|
compatible = "qcom,msm-hw-fence-mem";
|
|
};
|
|
};
|
|
|
|
qcom,vidc@aa00000 {
|
|
phandle = <0x576>;
|
|
reset-names = "video_axi1_reset\0video_axi0_reset\0video_mvs0c_freerun_reset\0video_mvs0_freerun_reset";
|
|
resets = <0x34 0x20 0x34 0x1f 0x55 0x05 0x55 0x02>;
|
|
memory-region = <0x36a>;
|
|
interconnect-names = "venus-cnoc\0venus-ddr\0venus-llcc";
|
|
interconnects = <0x78 0x02 0x79 0x222 0x45 0x03 0x45 0x201 0x5c 0x21 0x78 0x229>;
|
|
clock-names = "gcc_video_axi1_clk\0gcc_video_axi0_clk\0video_cc_mvs0c_freerun_clk\0video_cc_mvs0_freerun_clk\0video_cc_mvs0c_clk\0video_cc_mvs0_clk\0video_cc_mvs0_clk_src";
|
|
clocks = <0x34 0xa9 0x34 0xa8 0x55 0x09 0x55 0x05 0x55 0x07 0x55 0x02 0x55 0x03>;
|
|
power-domain-names = "iris-ctl\0vcodec";
|
|
power-domains = <0x55 0x01 0x55 0x00>;
|
|
interrupts = <0x00 0xae 0x04>;
|
|
reg = <0xaa00000 0xf0000>;
|
|
#size-cells = <0x01>;
|
|
#address-cells = <0x01>;
|
|
status = "okay";
|
|
compatible = "qcom,sm8750-vidc";
|
|
|
|
iommu_region_partition {
|
|
phandle = <0x575>;
|
|
iommu-addresses = <0x570 0x00 0x100000 0x570 0xe0000000 0x20000000 0x571 0x00 0x25800000 0x571 0xe0000000 0x20000000 0x572 0x00 0x1000000 0x572 0x25800000 0xda800000 0x573 0x00 0x500000 0x573 0xe0000000 0x20000000 0x574 0x00 0x500000 0x574 0xe0000000 0x20000000>;
|
|
};
|
|
|
|
non_secure_pixel_cb {
|
|
phandle = <0x570>;
|
|
dma-coherent;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-faults = "non-fatal";
|
|
memory-region = <0x575>;
|
|
iommus = <0x75 0x1947 0x00>;
|
|
compatible = "qcom,vidc,cb-ns-pxl";
|
|
};
|
|
|
|
non_secure_cb {
|
|
phandle = <0x571>;
|
|
dma-coherent;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-faults = "non-fatal";
|
|
memory-region = <0x575>;
|
|
iommus = <0x75 0x1940 0x00>;
|
|
compatible = "qcom,vidc,cb-ns";
|
|
};
|
|
|
|
secure_non_pixel_cb {
|
|
phandle = <0x572>;
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x0b>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
memory-region = <0x575>;
|
|
iommus = <0x75 0x1944 0x00>;
|
|
compatible = "qcom,vidc,cb-sec-non-pxl";
|
|
};
|
|
|
|
secure_bitstream_cb {
|
|
phandle = <0x573>;
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x09>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
memory-region = <0x575>;
|
|
iommus = <0x75 0x1941 0x04>;
|
|
compatible = "qcom,vidc,cb-sec-bitstream";
|
|
};
|
|
|
|
secure_pixel_cb {
|
|
phandle = <0x574>;
|
|
qcom,secure-context-bank;
|
|
qcom,iova-max-align-shift = <0x08>;
|
|
qcom,iova-best-fit;
|
|
qcom,iommu-vmid = <0x0a>;
|
|
qcom,iommu-faults = "non-fatal";
|
|
memory-region = <0x575>;
|
|
iommus = <0x75 0x1943 0x00>;
|
|
compatible = "qcom,vidc,cb-sec-pxl";
|
|
};
|
|
};
|
|
|
|
qcom,kgsl-iommu@3da0000 {
|
|
phandle = <0x57b>;
|
|
power-domains = <0x50 0x00>;
|
|
reg = <0x3da0000 0x40000>;
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
|
|
gfx3d_user {
|
|
phandle = <0x57c>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0x26b 0x00 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
|
|
gfx3d_lpac {
|
|
phandle = <0x57d>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0x26b 0x01 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
|
|
gfx3d_secure {
|
|
phandle = <0x57e>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0x26b 0x02 0x00>;
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
};
|
|
};
|
|
|
|
qcom,gmu@3d37000 {
|
|
phandle = <0x57f>;
|
|
qcom,qmp = <0x19>;
|
|
qcom,soccp-controller = <0x465>;
|
|
qcom,ipc-core = <0x400000 0x140000>;
|
|
qcom,iommu-dma = "disabled";
|
|
iommus = <0x26b 0x05 0x00>;
|
|
qcom,gmu-perf-ddr-bw = <0x5caf6a>;
|
|
qcom,gmu-freq-table = <0x1dcd6500 0x40 0x26be3680 0x80>;
|
|
clock-names = "gmu_clk\0cxo_clk\0axi_clk\0memnoc_clk\0ahb_clk\0hub_clk";
|
|
clocks = <0x50 0x04 0x50 0x06 0x34 0x0d 0x34 0x22 0x50 0x00 0x50 0x14>;
|
|
power-domain-names = "cx\0gmu_cx\0gx";
|
|
power-domains = <0x50 0x00 0x50 0x02 0x59 0x00>;
|
|
interrupt-names = "hfi\0gmu";
|
|
interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>;
|
|
reg-names = "gmu\0gmu_ao_blk_dec0";
|
|
reg = <0x3d37000 0x68000 0x3d40000 0x10000>;
|
|
compatible = "qcom,gen8-gmu";
|
|
};
|
|
|
|
qcom,gpu-coresight-cx {
|
|
phandle = <0x580>;
|
|
coresight-name = "coresight-gfx-cx";
|
|
compatible = "qcom,gpu-coresight-cx";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
phandle = <0x57a>;
|
|
remote-endpoint = <0x577>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,gpu-coresight-gx {
|
|
phandle = <0x581>;
|
|
coresight-name = "coresight-gfx";
|
|
compatible = "qcom,gpu-coresight-gx";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
phandle = <0x579>;
|
|
remote-endpoint = <0x578>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,msm-stub-codec {
|
|
phandle = <0x586>;
|
|
compatible = "qcom,msm-stub-codec";
|
|
};
|
|
|
|
qcom,audio-pkt-core-platform {
|
|
phandle = <0x587>;
|
|
compatible = "qcom,audio-pkt-core-platform";
|
|
};
|
|
|
|
qcom,msm-adsp-loader {
|
|
phandle = <0x588>;
|
|
qcom,rproc-handle = <0x82>;
|
|
compatible = "qcom,adsp-loader";
|
|
status = "disabled";
|
|
};
|
|
|
|
qcom,msm-adsp-notify {
|
|
phandle = <0x589>;
|
|
qcom,rproc-handle = <0x82>;
|
|
compatible = "qcom,adsp-notify";
|
|
status = "ok";
|
|
};
|
|
|
|
spf_core_platform {
|
|
phandle = <0x58a>;
|
|
compatible = "qcom,spf-core-platform";
|
|
|
|
qcom,msm-audio-ion {
|
|
phandle = <0x583>;
|
|
dma-coherent;
|
|
qcom,smmu-sid-mask = <0x00 0x0f>;
|
|
qcom,iommu-group = <0x469>;
|
|
memory-region = <0x582>;
|
|
iommus = <0x75 0x1001 0x80 0x75 0x1041 0x20>;
|
|
qcom,smmu-enabled;
|
|
qcom,smmu-version = <0x02>;
|
|
compatible = "qcom,msm-audio-ion";
|
|
|
|
audio_cnss_resv_region {
|
|
phandle = <0x582>;
|
|
iommu-addresses = <0x583 0x00 0x18000000 0x583 0xb0000000 0x50000000>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-audio-ion-cma {
|
|
phandle = <0x58b>;
|
|
compatible = "qcom,msm-audio-ion-cma";
|
|
};
|
|
|
|
lpi_pinctrl@07760000 {
|
|
phandle = <0x58c>;
|
|
clocks = <0x584 0x00 0x585 0x00>;
|
|
clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote";
|
|
qcom,lpi-slew-base-tbl = <0x7760000 0x7761000 0x7762000 0x7763000 0x7764000 0x7765000 0x7766000 0x7767000 0x7768000 0x7769000 0x776a000 0x776b000 0x776c000 0x776d000 0x776e000 0x776f000 0x7770000 0x7771000 0x7772000 0x7773000 0x7774000 0x7775000 0x7776000>;
|
|
qcom,lpi-slew-offset-tbl = <0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b 0x0b>;
|
|
qcom,lpi-offset-tbl = <0x00 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 0xc000 0xd000 0xe000 0xf000 0x10000 0x11000 0x12000 0x13000 0x14000 0x15000 0x16000>;
|
|
#gpio-cells = <0x02>;
|
|
gpio-controller;
|
|
qcom,slew-reg = <0x7760000 0x00>;
|
|
qcom,gpios-count = <0x17>;
|
|
reg = <0x7760000 0x00>;
|
|
compatible = "qcom,lpi-pinctrl";
|
|
};
|
|
|
|
lpass-cdc {
|
|
phandle = <0x58d>;
|
|
clocks = <0x584 0x00 0x585 0x00>;
|
|
clock-names = "lpass_core_hw_vote\0lpass_audio_hw_vote";
|
|
compatible = "qcom,lpass-cdc";
|
|
|
|
lpass-cdc-clk-rsc-mngr {
|
|
compatible = "qcom,lpass-cdc-clk-rsc-mngr";
|
|
};
|
|
|
|
va-macro@7660000 {
|
|
phandle = <0x58e>;
|
|
|
|
va_swr_master {
|
|
phandle = <0x58f>;
|
|
};
|
|
};
|
|
|
|
tx-macro@6AE0000 {
|
|
phandle = <0x590>;
|
|
};
|
|
|
|
rx-macro@6AC0000 {
|
|
phandle = <0x591>;
|
|
|
|
rx_swr_master {
|
|
phandle = <0x592>;
|
|
};
|
|
};
|
|
|
|
wsa-macro@6B00000 {
|
|
phandle = <0x593>;
|
|
|
|
wsa_swr_master {
|
|
phandle = <0x594>;
|
|
};
|
|
};
|
|
|
|
wsa2-macro@6AA0000 {
|
|
phandle = <0x595>;
|
|
|
|
wsa2_swr_master {
|
|
phandle = <0x596>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lpass_bt_swr@6CA0000 {
|
|
phandle = <0x597>;
|
|
compatible = "qcom,lpass-bt-swr";
|
|
|
|
bt_swr_mstr {
|
|
phandle = <0x598>;
|
|
};
|
|
};
|
|
|
|
sound {
|
|
phandle = <0x599>;
|
|
clocks = <0x585 0x00>;
|
|
clock-names = "lpass_audio_hw_vote";
|
|
qcom,afe-rxtx-lb = <0x00>;
|
|
qcom,ext-disp-audio-rx = <0x00>;
|
|
qcom,wcn-bt = <0x01>;
|
|
qcom,auxpcm-audio-intf = <0x01>;
|
|
qcom,tdm-audio-intf = <0x00>;
|
|
qcom,mi2s-audio-intf = <0x01>;
|
|
compatible = "qcom,sun-asoc-snd";
|
|
};
|
|
};
|
|
|
|
vote_lpass_core_hw {
|
|
phandle = <0x584>;
|
|
#clock-cells = <0x01>;
|
|
qcom,codec-ext-clk-src = <0x09>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
};
|
|
|
|
vote_lpass_audio_hw {
|
|
phandle = <0x585>;
|
|
#clock-cells = <0x01>;
|
|
qcom,codec-ext-clk-src = <0x0b>;
|
|
compatible = "qcom,audio-ref-clk";
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
qcom,ipa-napi-enable;
|
|
qcom,ipa-advertise-sg-support;
|
|
qcom,ipa-platform-type-msm;
|
|
qcom,rmnet-ipa-ssr;
|
|
compatible = "qcom,rmnet-ipa3";
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
status = "disabled";
|
|
qcom,pil-force-shutdown;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pas-id = <0x0f>;
|
|
compatible = "qcom,pil-tz-generic";
|
|
};
|
|
|
|
qcom,ipa@3e00000 {
|
|
phandle = <0x59c>;
|
|
qcom,ipa-gen-rx-ll-pool-sz-factor = <0x01>;
|
|
qcom,bus-vector-names = "MIN\0SVS2\0SVS\0NOMINAL\0TURBO";
|
|
qcom,turbo = <0x36ee80 0x00 0x36ee80 0x53ec60 0x00 0x61a80>;
|
|
qcom,nominal = <0x249f00 0x00 0x249f00 0x53ec60 0x00 0x61a80>;
|
|
qcom,svs = <0x124f80 0x00 0x124f80 0x2ab980 0x00 0x249f0>;
|
|
qcom,svs2 = <0x00 0x00 0x00 0x13d620 0x00 0x12c00>;
|
|
qcom,no-vote = <0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
interrupts = <0x00 0x28f 0x04 0x00 0x1b0 0x04>;
|
|
interconnect-names = "ipa_to_llcc\0llcc_to_ebi1\0appss_to_ipa";
|
|
interconnects = <0x44 0x2a 0x78 0x229 0x45 0x03 0x45 0x201 0x78 0x02 0xf4 0x20f>;
|
|
qcom,ipa-wdi-opt-dpath;
|
|
qcom,interconnect,num-paths = <0x03>;
|
|
qcom,interconnect,num-cases = <0x05>;
|
|
qcom,scaling-exceptions;
|
|
qcom,throughput-threshold = <0x7d0 0xfa0 0x1f40>;
|
|
clocks = <0x35 0x0c>;
|
|
clock-names = "core_clk";
|
|
qcom,max_num_smmu_cb = <0x04>;
|
|
qcom,ulso-ip-id-max-windows-val = <0x7fff>;
|
|
qcom,ulso-ip-id-min-windows-val = <0x00>;
|
|
qcom,ulso-ip-id-max-linux-val = <0xffff>;
|
|
qcom,ulso-ip-id-min-linux-val = <0x00>;
|
|
qcom,ulso-supported;
|
|
qcom,ipa-gpi-event-rp-ddr;
|
|
qcom,tx-wrapper-cache-max-size = <0x190>;
|
|
qcom,ipa-holb-monitor-max-cnt-11ad = <0x0a>;
|
|
qcom,ipa-holb-monitor-max-cnt-usb = <0x0a>;
|
|
qcom,ipa-holb-monitor-max-cnt-wlan = <0x0a>;
|
|
qcom,ipa-holb-monitor-poll-period = <0x05>;
|
|
qcom,ipa-uc-holb-monitor;
|
|
qcom,rmnet-ll-enable;
|
|
qcom,rmnet-ctl-enable;
|
|
qcom,wan-use-skb-page;
|
|
qcom,non-tn-collection-on-crash;
|
|
qcom,testbus-collection-on-crash;
|
|
qcom,register-collection-on-crash;
|
|
qcom,tx-poll;
|
|
qcom,tx-napi;
|
|
qcom,lan-rx-napi;
|
|
qcom,ipa-endp-delay-wa-v2;
|
|
qcom,use-64-bit-dma-mask;
|
|
qcom,smmu-fast-map;
|
|
qcom,arm-smmu;
|
|
qcom,ipa-wdi3-over-gsi;
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,mhi-event-ring-id-limits = <0x09 0x0b>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,entire-ipa-block-size = <0x200000>;
|
|
qcom,ee = <0x00>;
|
|
qcom,platform-type = <0x01>;
|
|
qcom,ipa-hw-mode = <0x00>;
|
|
qcom,ipa-hw-ver = <0x18>;
|
|
interrupt-names = "ipa-irq\0gsi-irq";
|
|
qcom,ipa-cfg-offset = <0x140000>;
|
|
memory-regions = <0x366>;
|
|
firmware-names = "ipa_fws";
|
|
pas-ids = <0x0f>;
|
|
reg-names = "ipa-base\0gsi-base";
|
|
reg = <0x3e00000 0x84000 0x3e04000 0xfc000>;
|
|
compatible = "qcom,ipa";
|
|
|
|
qcom,smp2p_map_ipa_1_out {
|
|
qcom,smem-state-names = "ipa-smp2p-out";
|
|
qcom,smem-states = <0x374 0x00>;
|
|
compatible = "qcom,smp2p-map-ipa-1-out";
|
|
};
|
|
|
|
qcom,smp2p_map_ipa_1_in {
|
|
interrupt-names = "ipa-smp2p-in";
|
|
interrupts-extended = <0x375 0x00 0x00>;
|
|
compatible = "qcom,smp2p-map-ipa-1-in";
|
|
};
|
|
|
|
ipa_smmu_ap {
|
|
phandle = <0x59d>;
|
|
qcom,ipa-q6-smem-size = <0xd800>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,additional-mapping = <0x14683000 0x14683000 0x2000>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
iommus = <0x75 0x4a0 0x00>;
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
};
|
|
|
|
ipa_smmu_wlan {
|
|
phandle = <0x59e>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
iommus = <0x75 0x4a1 0x00>;
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
};
|
|
|
|
ipa_smmu_uc {
|
|
phandle = <0x59f>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
iommus = <0x75 0x4a2 0x00>;
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
};
|
|
|
|
ipa_smmu_11ad {
|
|
phandle = <0x5a0>;
|
|
qcom,iommu-group;
|
|
qcom,shared-cb;
|
|
dma-coherent;
|
|
iommus = <0x75 0x4a4 0x00>;
|
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
|
};
|
|
};
|
|
|
|
smem_mailbox {
|
|
interrupt-names = "smem-mailbox-smp2p-1-in\0smem-mailbox-smp2p-2-in\0smem-mailbox-smp2p-3-in\0smem-mailbox-smp2p-4-in";
|
|
interrupts-extended = <0x377 0x00 0x00 0x377 0x01 0x00 0x377 0x02 0x00 0x377 0x03 0x00>;
|
|
qcom,smem-state-names = "smem-mailbox-smp2p-out";
|
|
qcom,smem-states = <0x376 0x00>;
|
|
compatible = "qcom,smem_mailbox";
|
|
};
|
|
|
|
qcom,mmrm-test {
|
|
phandle = <0x5a1>;
|
|
clock_data = <0x01 0x0a 0x11e1a300 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x2b 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x00 0x00 0x01 0x39 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x3c 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x3f 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x01 0x00 0x00 0x01 0x45 0x1c4fecc0 0x2245cdc0 0x283baec0 0x312c8040 0x312c8040 0x01 0x00 0x00 0x01 0x4b 0xbebc200 0x17d78400 0x1c9c3800 0x23c34600 0x23c34600 0x01 0x00 0x00 0x01 0x4f 0x1cd94100 0x22eda680 0x29020c00 0x3220a440 0x3220a440 0x01 0x00 0x00 0x01 0x6c 0x1c9c3800 0x258d0980 0x2aad4b00 0x31a69240 0x31a69240 0x01 0x00 0x00 0x01 0x71 0x1c9c3800 0x258d0980 0x2aad4b00 0x31a69240 0x31a69240 0x01 0x00 0x00 0x01 0x76 0x1c9c3800 0x258d0980 0x2aad4b00 0x31a69240 0x31a69240 0x01 0x00 0x00 0x01 0x35 0x11e1a300 0x11e1a300 0x11e1a300 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x69 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x4c4b400 0x01 0x00 0x00 0x01 0x14 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x16 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x18 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x23c3460 0x01 0x00 0x00 0x01 0x1d 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x1f 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x21 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x23 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x25 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x27 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x29 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x17d78400 0x01 0x00 0x00 0x01 0x1a 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x0a 0x00 0x00 0x01 0x42 0x17d78400 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x1c9c3800 0x02 0x00 0x00 0x01 0x03 0x47868c00 0x50775d80 0x59682f00 0x62590080 0x62590080 0x01 0x00 0x00 0x01 0x42 0xc5691c0 0x14163640 0x18daea40 0x1fb5ad00 0x2245cdc0 0x01 0x00 0x00 0x01 0x03 0x3c706980 0x4b1a1300 0x4f64b500 0x5f5e1000 0x70a71c80 0x01 0x00 0x00>;
|
|
clocks = <0x3e 0x0a 0x3e 0x2b 0x3e 0x39 0x3e 0x3c 0x3e 0x3f 0x3e 0x45 0x3e 0x4b 0x3e 0x4f 0x3e 0x6c 0x3e 0x71 0x3e 0x76 0x3e 0x35 0x3e 0x69 0x3e 0x14 0x3e 0x16 0x3e 0x18 0x3e 0x1d 0x3e 0x1f 0x3e 0x21 0x3e 0x23 0x3e 0x25 0x3e 0x27 0x3e 0x29 0x3e 0x1a 0x3e 0x42 0x56 0x03 0x3f 0x42 0x55 0x03>;
|
|
clock-names = "cam_cc_camnoc_rt_axi_clk_src\0cam_cc_csid_clk_src\0cam_cc_icp_0_clk_src\0cam_cc_icp_1_clk_src\0cam_cc_ife_lite_clk_src\0cam_cc_ipe_nps_clk_src\0cam_cc_jpeg_clk_src\0cam_cc_ofe_clk_src\0cam_cc_tfe_0_clk_src\0cam_cc_tfe_1_clk_src\0cam_cc_tfe_2_clk_src\0cam_cc_fast_ahb_clk_src\0cam_cc_slow_ahb_clk_src\0cam_cc_cci_0_clk_src\0cam_cc_cci_1_clk_src\0cam_cc_cci_2_clk_src\0cam_cc_cre_clk_src\0cam_cc_csi0phytimer_clk_src\0cam_cc_csi1phytimer_clk_src\0cam_cc_csi2phytimer_clk_src\0cam_cc_csi3phytimer_clk_src\0cam_cc_csi4phytimer_clk_src\0cam_cc_csi5phytimer_clk_src\0cam_cc_cphy_rx_clk_src\0cam_cc_ife_lite_csid_clk_src\0eva_cc_mvs0_clk_src\0disp_cc_mdss_mdp_clk_src\0video_cc_mvs0_clk_src";
|
|
status = "disable";
|
|
compatible = "qcom,msm-mmrm-test\0qcom,sun-mmrm-test";
|
|
};
|
|
|
|
qcom,cam-req-mgr {
|
|
status = "ok";
|
|
compatible = "qcom,cam-req-mgr";
|
|
};
|
|
|
|
qcom,cam-sync {
|
|
status = "ok";
|
|
compatible = "qcom,cam-sync";
|
|
};
|
|
|
|
qcom,cam-i3c-id-table {
|
|
status = "disabled";
|
|
i3c-ois-id-table;
|
|
i3c-actuator-id-table;
|
|
i3c-eeprom-id-table;
|
|
i3c-sensor-id-table = <0x1b0 0x858>;
|
|
};
|
|
|
|
qcom,csiphy0@ada9000 {
|
|
phandle = <0x5f9>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x2d 0x3e 0x1f 0x3e 0x1e>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy0_clk\0csi0phytimer_clk_src\0csi0phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xe09c0>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x347>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x1dd 0x01>;
|
|
interrupt-names = "CSIPHY0";
|
|
reg-cam-base = <0x1a9000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xada9000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,csiphy1@adab000 {
|
|
phandle = <0x5fa>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x2e 0x3e 0x21 0x3e 0x20>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy1_clk\0csi1phytimer_clk_src\0csi1phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xe09c0>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x347>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x1de 0x01>;
|
|
interrupt-names = "CSIPHY1";
|
|
reg-cam-base = <0x1ab000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xadab000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x01>;
|
|
};
|
|
|
|
qcom,csiphy2@adad000 {
|
|
phandle = <0x5fb>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x2f 0x3e 0x23 0x3e 0x22>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy2_clk\0csi2phytimer_clk_src\0csi2phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xdea80>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x3d>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x1df 0x01>;
|
|
interrupt-names = "CSIPHY2";
|
|
reg-cam-base = <0x1ad000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xadad000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x02>;
|
|
};
|
|
|
|
qcom,csiphy3@adaf000 {
|
|
phandle = <0x5fc>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x30 0x3e 0x25 0x3e 0x24>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy3_clk\0csi3phytimer_clk_src\0csi3phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xe09c0>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x347>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x1c0 0x01>;
|
|
interrupt-names = "CSIPHY3";
|
|
reg-cam-base = <0x1af000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xadaf000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x03>;
|
|
};
|
|
|
|
qcom,csiphy4@adb1000 {
|
|
phandle = <0x5fd>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x31 0x3e 0x27 0x3e 0x26>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy4_clk\0csi4phytimer_clk_src\0csi4phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xdea80>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x3d>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x7a 0x01>;
|
|
interrupt-names = "CSIPHY4";
|
|
reg-cam-base = <0x1b1000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xadb1000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x04>;
|
|
};
|
|
|
|
qcom,csiphy5@adb3000 {
|
|
phandle = <0x5fe>;
|
|
status = "ok";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x17d78400 0x00 0x17d78400 0x00 0x1c9c3800 0x00 0x17d78400 0x00>;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clocks = <0x3e 0x1a 0x3e 0x32 0x3e 0x29 0x3e 0x28>;
|
|
clock-names = "cphy_rx_clk_src\0csiphy5_clk\0csi5phytimer_clk_src\0csi5phytimer_clk";
|
|
shared-clks = <0x01 0x00 0x00 0x00>;
|
|
rgltr-load-current = <0x00 0x1838 0x15888>;
|
|
rgltr-max-voltage = <0x00 0x132a40 0xe09c0>;
|
|
rgltr-min-voltage = <0x00 0x124f80 0xd6d80>;
|
|
rgltr-cntrl-support;
|
|
csi-vdd-0p9-supply = <0x347>;
|
|
csi-vdd-1p2-supply = <0x3c>;
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr\0csi-vdd-1p2\0csi-vdd-0p9";
|
|
interrupts = <0x00 0x59 0x01>;
|
|
interrupt-names = "CSIPHY5";
|
|
reg-cam-base = <0x1b3000>;
|
|
reg-names = "csiphy";
|
|
reg = <0xadb3000 0x2000>;
|
|
compatible = "qcom,csiphy-v2.3.0\0qcom,csiphy";
|
|
cell-index = <0x05>;
|
|
};
|
|
|
|
qcom,cci0@ac7b000 {
|
|
phandle = <0x5ff>;
|
|
status = "ok";
|
|
pinctrl-3 = <0x5a8 0x5a9>;
|
|
pinctrl-2 = <0x5a6 0x5a7>;
|
|
pinctrl-1 = <0x5a4 0x5a5>;
|
|
pinctrl-0 = <0x5a2 0x5a3>;
|
|
pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend";
|
|
pctrl-map-names = "m0\0m1";
|
|
pctrl-idx-mapping = <0x00 0x01>;
|
|
src-clock-name = "cci_0_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs";
|
|
clock-rates = <0x23c3460 0x00 0x23c3460 0x00>;
|
|
clocks = <0x3e 0x14 0x3e 0x13>;
|
|
clock-names = "cci_0_clk_src\0cci_0_clk";
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr";
|
|
interrupts = <0x00 0x1aa 0x01>;
|
|
interrupt-names = "CCI0";
|
|
reg-cam-base = <0x7b000>;
|
|
reg-names = "cci";
|
|
reg = <0xac7b000 0x1000>;
|
|
compatible = "qcom,cci\0simple-bus";
|
|
cell-index = <0x00>;
|
|
|
|
qcom,i2c_standard_mode {
|
|
phandle = <0x600>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0xe3>;
|
|
hw-thd-sta = <0xa2>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0xe7>;
|
|
hw-tsu-sto = <0xcc>;
|
|
hw-tlow = <0xae>;
|
|
hw-thigh = <0xc9>;
|
|
};
|
|
|
|
qcom,i2c_fast_mode {
|
|
phandle = <0x601>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tlow = <0x38>;
|
|
hw-thigh = <0x26>;
|
|
};
|
|
|
|
qcom,i2c_custom_mode {
|
|
phandle = <0x602>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x01>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
|
|
qcom,i2c_fast_plus_mode {
|
|
phandle = <0x603>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
};
|
|
|
|
qcom,cci1@ac7c000 {
|
|
phandle = <0x604>;
|
|
status = "ok";
|
|
pinctrl-3 = <0x5b0 0x5b1>;
|
|
pinctrl-2 = <0x5ae 0x5af>;
|
|
pinctrl-1 = <0x5ac 0x5ad>;
|
|
pinctrl-0 = <0x5aa 0x5ab>;
|
|
pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend";
|
|
pctrl-map-names = "m0\0m1";
|
|
pctrl-idx-mapping = <0x00 0x01>;
|
|
src-clock-name = "cci_1_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs";
|
|
clock-rates = <0x23c3460 0x00 0x23c3460 0x00>;
|
|
clocks = <0x3e 0x16 0x3e 0x15>;
|
|
clock-names = "cci_1_clk_src\0cci_1_clk";
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr";
|
|
interrupts = <0x00 0x1ab 0x01>;
|
|
interrupt-names = "CCI1";
|
|
reg-cam-base = <0x7c000>;
|
|
reg-names = "cci";
|
|
reg = <0xac7c000 0x1000>;
|
|
compatible = "qcom,cci\0simple-bus";
|
|
cell-index = <0x01>;
|
|
|
|
qcom,i2c_standard_mode {
|
|
phandle = <0x605>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0xe3>;
|
|
hw-thd-sta = <0xa2>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0xe7>;
|
|
hw-tsu-sto = <0xcc>;
|
|
hw-tlow = <0xae>;
|
|
hw-thigh = <0xc9>;
|
|
};
|
|
|
|
qcom,i2c_fast_mode {
|
|
phandle = <0x606>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tlow = <0x38>;
|
|
hw-thigh = <0x26>;
|
|
};
|
|
|
|
qcom,i2c_custom_mode {
|
|
phandle = <0x607>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x01>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
|
|
qcom,i2c_fast_plus_mode {
|
|
phandle = <0x608>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
};
|
|
|
|
qcom,cci2@ac7d000 {
|
|
phandle = <0x609>;
|
|
status = "ok";
|
|
pinctrl-3 = <0x5b8 0x5b9>;
|
|
pinctrl-2 = <0x5b6 0x5b7>;
|
|
pinctrl-1 = <0x5b4 0x5b5>;
|
|
pinctrl-0 = <0x5b2 0x5b3>;
|
|
pinctrl-names = "m0_active\0m0_suspend\0m1_active\0m1_suspend";
|
|
pctrl-map-names = "m0\0m1";
|
|
pctrl-idx-mapping = <0x00 0x01>;
|
|
src-clock-name = "cci_2_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs";
|
|
clock-rates = <0x23c3460 0x00 0x23c3460 0x00>;
|
|
clocks = <0x3e 0x18 0x3e 0x17>;
|
|
clock-names = "cci_2_clk_src\0cci_2_clk";
|
|
gdscr-supply = <0x5b>;
|
|
regulator-names = "gdscr";
|
|
interrupts = <0x00 0x1ac 0x01>;
|
|
interrupt-names = "CCI2";
|
|
reg-cam-base = <0x7d000>;
|
|
reg-names = "cci";
|
|
reg = <0xac7d000 0x1000>;
|
|
compatible = "qcom,cci\0simple-bus";
|
|
cell-index = <0x02>;
|
|
|
|
qcom,i2c_standard_mode {
|
|
phandle = <0x60a>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0xe3>;
|
|
hw-thd-sta = <0xa2>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0xe7>;
|
|
hw-tsu-sto = <0xcc>;
|
|
hw-tlow = <0xae>;
|
|
hw-thigh = <0xc9>;
|
|
};
|
|
|
|
qcom,i2c_fast_mode {
|
|
phandle = <0x60b>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x06>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x3e>;
|
|
hw-thd-sta = <0x23>;
|
|
hw-thd-dat = <0x16>;
|
|
hw-tsu-sta = <0x28>;
|
|
hw-tsu-sto = <0x28>;
|
|
hw-tlow = <0x38>;
|
|
hw-thigh = <0x26>;
|
|
};
|
|
|
|
qcom,i2c_custom_mode {
|
|
phandle = <0x60c>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x01>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
|
|
qcom,i2c_fast_plus_mode {
|
|
phandle = <0x60d>;
|
|
status = "ok";
|
|
cci-clk-src = <0x23c3460>;
|
|
hw-tsp = <0x03>;
|
|
hw-trdhld = <0x03>;
|
|
hw-scl-stretch-en = <0x00>;
|
|
hw-tbuf = <0x18>;
|
|
hw-thd-sta = <0x0f>;
|
|
hw-thd-dat = <0x10>;
|
|
hw-tsu-sta = <0x12>;
|
|
hw-tsu-sto = <0x11>;
|
|
hw-tlow = <0x16>;
|
|
hw-thigh = <0x10>;
|
|
};
|
|
};
|
|
|
|
qcom,cam_smmu {
|
|
#size-cells = <0x02>;
|
|
#address-cells = <0x02>;
|
|
need_shared_buffer_padding;
|
|
force_cache_allocs;
|
|
expanded_memory;
|
|
status = "ok";
|
|
compatible = "qcom,msm-cam-smmu\0simple-bus";
|
|
|
|
msm_cam_smmu_ife {
|
|
phandle = <0x5bb>;
|
|
memory-region = <0x5ba>;
|
|
multiple-client-devices;
|
|
cam-smmu-label = "ife";
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0non-fatal";
|
|
iommus = <0x75 0x1c00 0x00>;
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
|
|
cam_smmu_ife_resv_region {
|
|
phandle = <0x5ba>;
|
|
iommu-addresses = <0x5bb 0x00 0x00 0x00 0x100000 0x5bb 0x0f 0xfff00000 0x00 0x100000>;
|
|
};
|
|
|
|
iova-mem-map {
|
|
phandle = <0x60e>;
|
|
|
|
iova-mem-region-io {
|
|
status = "ok";
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x0f 0xffe00000>;
|
|
iova-region-start = <0x00 0x100000>;
|
|
iova-region-name = "io";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_jpeg {
|
|
phandle = <0x5bd>;
|
|
memory-region = <0x5bc>;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0non-fatal";
|
|
cam-smmu-label = "jpeg";
|
|
iommus = <0x75 0x18a0 0x00>;
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
|
|
cam_smmu_jpeg_resv_region {
|
|
phandle = <0x5bc>;
|
|
iommu-addresses = <0x5bd 0x00 0x00 0x00 0x100000 0x5bd 0x00 0xfff00000 0x0f 0x100000>;
|
|
};
|
|
|
|
iova-mem-map {
|
|
phandle = <0x60f>;
|
|
|
|
iova-mem-region-io {
|
|
status = "ok";
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x00 0xffe00000>;
|
|
iova-region-start = <0x00 0x100000>;
|
|
iova-region-name = "io";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_icp {
|
|
phandle = <0x5bf>;
|
|
memory-region = <0x5be>;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0non-fatal";
|
|
multiple-same-region-clients = "icp\0icp1";
|
|
multiple-client-devices;
|
|
cam-smmu-label = "icp\0icp1";
|
|
iommus = <0x75 0x1820 0x00 0x75 0x1800 0xc0 0x75 0x1980 0x00>;
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
|
|
cam_smmu_icp_resv_region {
|
|
phandle = <0x5be>;
|
|
iommu-addresses = <0x5bf 0x00 0x00 0x00 0xf1600000>;
|
|
};
|
|
|
|
iova-mem-map {
|
|
phandle = <0x610>;
|
|
|
|
iova-mem-region-shared1 {
|
|
status = "ok";
|
|
iova-region-id = <0x01>;
|
|
iova-region-len = <0x00 0x38400000>;
|
|
iova-region-start = <0x00 0x80e00000>;
|
|
iova-region-name = "shared";
|
|
};
|
|
|
|
iova-mem-region-shared2 {
|
|
status = "ok";
|
|
iova-region-id = <0x01>;
|
|
iova-region-len = <0x00 0x38400000>;
|
|
iova-region-start = <0x00 0xb9200000>;
|
|
iova-region-name = "shared";
|
|
};
|
|
|
|
iova-mem-region-fwuncached-region1 {
|
|
status = "ok";
|
|
subregion_support;
|
|
iova-region-id = <0x06>;
|
|
iova-region-len = <0x00 0x500000>;
|
|
iova-region-start = <0x00 0x80400000>;
|
|
iova-region-name = "fw_uncached";
|
|
|
|
iova-mem-region-generic-region {
|
|
iova-region-id = <0x00>;
|
|
iova-region-len = <0x00 0x200000>;
|
|
iova-region-start = <0x00 0x80500000>;
|
|
iova-region-name = "icp_hfi";
|
|
};
|
|
|
|
iova-mem-region-global-sync-region {
|
|
phy-addr = <0x82600000>;
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x00 0x100000>;
|
|
iova-region-start = <0x00 0x80400000>;
|
|
iova-region-name = "global_sync";
|
|
};
|
|
};
|
|
|
|
iova-mem-region-fwuncached-region2 {
|
|
status = "ok";
|
|
subregion_support;
|
|
iova-region-id = <0x06>;
|
|
iova-region-len = <0x00 0x500000>;
|
|
iova-region-start = <0x00 0x80900000>;
|
|
iova-region-name = "fw_uncached";
|
|
|
|
iova-mem-region-generic-region {
|
|
iova-region-id = <0x00>;
|
|
iova-region-len = <0x00 0x200000>;
|
|
iova-region-start = <0x00 0x80a00000>;
|
|
iova-region-name = "icp_hfi";
|
|
};
|
|
|
|
iova-mem-region-global-sync-region {
|
|
phy-addr = <0x82600000>;
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x00 0x100000>;
|
|
iova-region-start = <0x00 0x80900000>;
|
|
iova-region-name = "global_sync";
|
|
};
|
|
};
|
|
|
|
iova-mem-device-region {
|
|
status = "ok";
|
|
subregion_support;
|
|
iova-region-id = <0x07>;
|
|
iova-region-len = <0x00 0x300000>;
|
|
iova-region-start = <0x00 0x80100000>;
|
|
iova-region-name = "device";
|
|
|
|
iova-mem-region-synx-hwmutex {
|
|
phy-addr = <0x1f4a000>;
|
|
iova-region-id = <0x01>;
|
|
iova-region-len = <0x00 0x1000>;
|
|
iova-region-start = <0x00 0x80100000>;
|
|
iova-region-name = "synx_hwmutex";
|
|
};
|
|
|
|
iova-mem-region-ipc-hwmutex {
|
|
phy-addr = <0x1f4b000>;
|
|
iova-region-id = <0x02>;
|
|
iova-region-len = <0x00 0x1000>;
|
|
iova-region-start = <0x00 0x80101000>;
|
|
iova-region-name = "ipc_hwmutex";
|
|
};
|
|
|
|
iova-mem-region-global_cntr {
|
|
phy-addr = "\f\"\0";
|
|
iova-region-id = <0x04>;
|
|
iova-region-len = <0x00 0x1000>;
|
|
iova-region-start = <0x00 0x80102000>;
|
|
iova-region-name = "global_cntr";
|
|
};
|
|
|
|
iova-mem-region-llcc-register {
|
|
phy-addr = <0x26c00000>;
|
|
iova-region-id = <0x05>;
|
|
iova-region-len = <0x00 0x200000>;
|
|
iova-region-start = <0x00 0x80103000>;
|
|
iova-region-name = "llcc-register";
|
|
};
|
|
};
|
|
|
|
iova-mem-region-io {
|
|
status = "ok";
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x0f 0xea00000>;
|
|
iova-region-start = <0x00 0xf1600000>;
|
|
iova-region-name = "io";
|
|
};
|
|
|
|
iova-mem-qdss-region {
|
|
status = "ok";
|
|
qdss-phy-addr = "7y\0";
|
|
iova-region-id = <0x05>;
|
|
iova-region-len = <0x00 0x100000>;
|
|
iova-region-start = <0x00 0x80000000>;
|
|
iova-region-name = "qdss";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_cdm {
|
|
phandle = <0x5c1>;
|
|
memory-region = <0x5c0>;
|
|
multiple-client-devices;
|
|
dma-coherent;
|
|
qcom,iommu-faults = "stall-disable\0non-fatal";
|
|
cam-smmu-label = "rt-cdm";
|
|
iommus = <0x75 0x1860 0x00>;
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
|
|
cam_smmu_cdm_resv_region {
|
|
phandle = <0x5c0>;
|
|
iommu-addresses = <0x5c1 0x00 0x00 0x00 0x100000 0x5c1 0x00 0xfff00000 0x0f 0x100000>;
|
|
};
|
|
|
|
iova-mem-map {
|
|
phandle = <0x611>;
|
|
|
|
iova-mem-region-io {
|
|
status = "ok";
|
|
iova-region-id = <0x03>;
|
|
iova-region-len = <0x00 0xffe00000>;
|
|
iova-region-start = <0x00 0x100000>;
|
|
iova-region-name = "io";
|
|
};
|
|
};
|
|
};
|
|
|
|
msm_cam_smmu_secure {
|
|
qti,smmu-proxy-cb-id = <0x00>;
|
|
qcom,secure-cb;
|
|
cam-smmu-label = "cam-secure";
|
|
compatible = "qcom,msm-cam-smmu-cb";
|
|
};
|
|
};
|
|
|
|
qcom,cam-cpas@ac13000 {
|
|
status = "ok";
|
|
rt-wr-bw-ratio-scale-factor = <0x01>;
|
|
rt-wr-lowstress-indicator-threshold = <0x00>;
|
|
rt-wr-highstress-indicator-threshold = <0x32>;
|
|
rt-wr-moststressed-clamp-threshold = <0x06>;
|
|
rt-wr-leaststressed-clamp-threshold = <0x0a>;
|
|
rt-wr-slope-factor = <0x46>;
|
|
rt-wr-priority-clamp = <0x06>;
|
|
rt-wr-priority-max = <0x05>;
|
|
rt-wr-priority-min = <0x04>;
|
|
enable-cam-drv = <0x03>;
|
|
enable-smart-qos;
|
|
enable-secure-qos-update;
|
|
sys-cache-concur = <0x01 0x01 0x01 0x00 0x00>;
|
|
sys-cache-uids = <0x47 0x48 0x49 0x4a 0x4b>;
|
|
sys-cache-names = "ofe_ip\0ipe_rt_ip\0ipe_srt_ip\0ipe_rt_rf\0ipe_srt_rf";
|
|
client-names = "csiphy0\0csiphy1\0csiphy2\0csiphy3\0csiphy4\0csiphy5\0cci0\0cci1\0cci2\0csid0\0csid1\0csid2\0csid3\0csid4\0ife0\0ife1\0ife2\0ife3\0ife4\0ipe0\0rt-cdm0\0rt-cdm1\0rt-cdm2\0rt-cdm3\0rt-cdm4\0cam-cdm-intf0\0icp0\0icp1\0ofe0\0cre0\0jpeg-dma0\0jpeg-enc0\0jpeg-dma1\0jpeg-enc1\0tpg13\0tpg14\0tpg15";
|
|
client-id-based;
|
|
vdd-corner-ahb-mapping = "suspend\0lowsvs\0lowsvs\0svs\0svs_l1\0nominal\0nominal\0nominal\0turbo\0turbo";
|
|
vdd-corners = <0x10 0x30 0x40 0x80 0xc0 0x100 0x140 0x150 0x180 0x1a0>;
|
|
cam-ahb-bw-KBps = <0x00 0x00 0x00 0x12c00 0x00 0x12c00 0x00 0x249f0 0x00 0x249f0 0x00 0x493e0 0x00 0x493e0 0x00 0x493e0>;
|
|
cam-ahb-num-cases = <0x08>;
|
|
rpmh-bcm-info = <0x0d 0x04 0x800 0x00 0x04>;
|
|
interconnects = <0x78 0x02 0x79 0x205 0x5c 0x0a 0x45 0x201 0x5c 0x7d1 0x45 0x9d0 0x5c 0xbb9 0x45 0xdb8 0x5c 0xfa1 0x45 0x11a0 0x5c 0x0d 0x45 0x201 0x5c 0x0b 0x45 0x201>;
|
|
interconnect-names = "cam_ahb\0cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv\0cam_sf_0\0cam_sf_icp";
|
|
cam-icc-path-names = "cam_ahb";
|
|
domain-id = <0x01 0x10 0x00 0x00>;
|
|
camnoc-axi-clk-bw-margin-perc = <0x14>;
|
|
camnoc-bus-width = <0x20>;
|
|
cam-crmb-clk;
|
|
control-camnoc-axi-clk;
|
|
shared-clks-option = <0x00 0x00 0x00 0x01 0x00>;
|
|
clock-rates-option = <0x17d78400 0x00 0x00 0x00 0x00>;
|
|
clocks-option = <0x3e 0x41 0x3e 0x3d 0x3e 0x2b 0x3e 0x2a>;
|
|
clock-names-option = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk";
|
|
domain-id-support-clks = "ife_lite_csid_clk\0ife_lite_ahb\0csid_clk_src\0csid_clk";
|
|
src-clock-name = "camnoc_rt_axi_clk_src";
|
|
clock-cntl-level = "suspend\0lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0nominal_l1\0turbo";
|
|
clock-rates = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x35dac3c 0x00 0x00 0x00 0xcb73555 0x00 0xbebc200 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x11e1a300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x11e1a300 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x4c4b400 0x00 0x00 0x00 0x17d78400 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x34 0x06 0x34 0x07 0x34 0x08 0x3e 0x69 0x3e 0x00 0x3e 0x19 0x3e 0x33 0x3e 0x35 0x3e 0x01 0x3e 0x0a 0x3e 0x09 0x3e 0x03 0x3e 0x34 0x3e 0x54 0x3e 0x66>;
|
|
clock-names = "gcc_ahb_clk\0gcc_axi_hf_clk\0gcc_axi_sf_clk\0cam_cc_slow_ahb_clk_src\0cpas_ahb_clk\0cpas_core_ahb_clk\0cam_cc_drv_ahb_clk\0cam_cc_fast_ahb_clk_src\0cam_cc_top_fast_ahb_clk\0camnoc_rt_axi_clk_src\0camnoc_rt_axi_clk\0camnoc_nrt_axi_clk\0cam_cc_drv_xo_clk\0cam_cc_pll0\0cam_cc_qdss_debug_xo_clk";
|
|
top-gdsc-supply = <0x5b>;
|
|
regulator-names = "top-gdsc";
|
|
cam-max-rt-axi-bw = <0x03 0x60447100>;
|
|
camnoc-axi-min-ib-bw = <0xb2d05e00>;
|
|
interrupts = <0x00 0x115 0x01 0x00 0x10f 0x01>;
|
|
interrupt-names = "cpas_camnoc_rt\0cpas_camnoc_nrt";
|
|
reg-cam-base = <0x4000 0x62000 0x190000 0xbbf0000 0xadcb000>;
|
|
reg = <0xac04000 0x1000 0xac62000 0x9200 0xad90000 0x9000 0xbbf0000 0x1f00 0xadcb000 0x5000>;
|
|
reg-names = "cam_cpas_top\0cam_camnoc_nrt\0cam_camnoc_rt\0cam_rpmh\0cam_cesta";
|
|
arch-compat = "cpas_top";
|
|
label = "cpas";
|
|
compatible = "qcom,cam-cpas";
|
|
cell-index = <0x00>;
|
|
|
|
camera-bus-nodes {
|
|
|
|
level3-nodes {
|
|
level-index = <0x03>;
|
|
|
|
level3-rt-rd-wr-sum {
|
|
phandle = <0x5c2>;
|
|
rt-axi-port;
|
|
ib-bw-voting-needed;
|
|
traffic-merge-type = <0x00>;
|
|
node-name = "level3-rt-rd-wr-sum";
|
|
cell-index = <0x00>;
|
|
|
|
qcom,axi-port-mnoc {
|
|
cam-icc-path-names = "cam_hf_0\0cam_ife_0_drv\0cam_ife_1_drv\0cam_ife_2_drv";
|
|
};
|
|
};
|
|
|
|
level3-nrt0-rd-wr-sum {
|
|
phandle = <0x5c3>;
|
|
traffic-merge-type = <0x00>;
|
|
node-name = "level3-nrt0-rd-wr-sum";
|
|
cell-index = <0x01>;
|
|
|
|
qcom,axi-port-mnoc {
|
|
cam-icc-path-names = "cam_sf_0";
|
|
};
|
|
};
|
|
|
|
level3-nrt1-rd-wr-sum {
|
|
phandle = <0x5c4>;
|
|
traffic-merge-type = <0x00>;
|
|
node-name = "level3-nrt1-rd-wr-sum";
|
|
cell-index = <0x02>;
|
|
|
|
qcom,axi-port-mnoc {
|
|
cam-icc-path-names = "cam_sf_icp";
|
|
};
|
|
};
|
|
};
|
|
|
|
level2-nodes {
|
|
camnoc-max-needed;
|
|
level-index = <0x02>;
|
|
|
|
level2-rt-wr {
|
|
phandle = <0x5c5>;
|
|
traffic-merge-type = <0x01>;
|
|
parent-node = <0x5c2>;
|
|
node-name = "level2-rt-wr";
|
|
cell-index = <0x03>;
|
|
};
|
|
|
|
level2-rt-rd {
|
|
phandle = <0x5c6>;
|
|
traffic-merge-type = <0x01>;
|
|
parent-node = <0x5c2>;
|
|
node-name = "level2-rt-rd";
|
|
cell-index = <0x04>;
|
|
};
|
|
|
|
level2-nrt-wr {
|
|
phandle = <0x5c7>;
|
|
traffic-merge-type = <0x01>;
|
|
parent-node = <0x5c3>;
|
|
node-name = "level2-nrt-wr";
|
|
cell-index = <0x05>;
|
|
};
|
|
|
|
level2-nrt-rd {
|
|
phandle = <0x5c8>;
|
|
traffic-merge-type = <0x01>;
|
|
parent-node = <0x5c3>;
|
|
node-name = "level2-nrt-rd";
|
|
cell-index = <0x06>;
|
|
};
|
|
|
|
level2-icp-rd {
|
|
phandle = <0x5d2>;
|
|
bus-width-factor = <0x04>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c4>;
|
|
node-name = "level2-icp-rd";
|
|
cell-index = <0x07>;
|
|
};
|
|
};
|
|
|
|
level1-nodes {
|
|
camnoc-max-needed;
|
|
level-index = <0x01>;
|
|
|
|
level1-rt1-wr {
|
|
phandle = <0x5c9>;
|
|
priority-lut-high-offset = <0x4834>;
|
|
priority-lut-low-offset = <0x4830>;
|
|
niu-size = <0x86>;
|
|
rt-wr-niu;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c5>;
|
|
node-name = " level1-rt1-ife-ubwc-wr";
|
|
cell-index = <0x08>;
|
|
};
|
|
|
|
level1-rt2-wr {
|
|
phandle = <0x5cc>;
|
|
priority-lut-high-offset = <0x4a34>;
|
|
priority-lut-low-offset = <0x4a30>;
|
|
niu-size = <0x24>;
|
|
rt-wr-niu;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c5>;
|
|
node-name = "level1-rt2-ife-stats";
|
|
cell-index = <0x09>;
|
|
};
|
|
|
|
level1-rt3-wr {
|
|
phandle = <0x5cb>;
|
|
priority-lut-high-offset = <0x4c34>;
|
|
priority-lut-low-offset = <0x4c30>;
|
|
niu-size = <0x5c>;
|
|
rt-wr-niu;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c5>;
|
|
node-name = "level1-rt3-ife-pdaf-lite";
|
|
cell-index = <0x0a>;
|
|
};
|
|
|
|
level1-rt4-wr1 {
|
|
phandle = <0x5ca>;
|
|
priority-lut-high-offset = <0x5234>;
|
|
priority-lut-low-offset = <0x5230>;
|
|
niu-size = <0x86>;
|
|
rt-wr-niu;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c5>;
|
|
node-name = "level1-rt4-ife-rdi-wr";
|
|
cell-index = <0x0b>;
|
|
};
|
|
|
|
level1-rt3-rd {
|
|
phandle = <0x5d1>;
|
|
priority-lut-high-offset = <0x4c34>;
|
|
priority-lut-low-offset = <0x4c30>;
|
|
niu-size = <0x5c>;
|
|
rt-wr-niu;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c6>;
|
|
node-name = "level1-rt3-cdm-rd";
|
|
cell-index = <0x0c>;
|
|
};
|
|
|
|
level1-nrt2-wr {
|
|
phandle = <0x5cd>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c7>;
|
|
node-name = "level1-nrt2-wr";
|
|
cell-index = <0x0d>;
|
|
};
|
|
|
|
level1-nrt6-wr {
|
|
phandle = <0x5ce>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c7>;
|
|
node-name = "level1-nrt6-wr";
|
|
cell-index = <0x0e>;
|
|
};
|
|
|
|
level1-nrt6-rd {
|
|
phandle = <0x5d0>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt6-rd";
|
|
cell-index = <0x0f>;
|
|
};
|
|
|
|
level1-nrt0-rd {
|
|
phandle = <0x612>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt0-rd";
|
|
cell-index = <0x10>;
|
|
};
|
|
|
|
level1-nrt5-rd {
|
|
phandle = <0x5cf>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt5-rd";
|
|
cell-index = <0x11>;
|
|
};
|
|
|
|
level1-nrt4-rd {
|
|
phandle = <0x5d3>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt4-rd";
|
|
cell-index = <0x12>;
|
|
};
|
|
|
|
level1-nrt3-wr {
|
|
phandle = <0x5d4>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt3-wr";
|
|
cell-index = <0x13>;
|
|
};
|
|
|
|
level1-nrt9-rd {
|
|
phandle = <0x613>;
|
|
traffic-merge-type = <0x00>;
|
|
parent-node = <0x5c8>;
|
|
node-name = "level1-nrt3-wr";
|
|
cell-index = <0x14>;
|
|
};
|
|
};
|
|
|
|
level0-nodes {
|
|
level-index = <0x00>;
|
|
|
|
ife0-ubwc-wr {
|
|
phandle = <0x614>;
|
|
parent-node = <0x5c9>;
|
|
drv-voting-index = <0x01>;
|
|
constituent-paths = <0x0a 0x0b 0x0f>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x106>;
|
|
client-name = "ife0";
|
|
node-name = "ife0-ubwc-wr";
|
|
cell-index = <0x15>;
|
|
};
|
|
|
|
ife1-ubwc-wr {
|
|
phandle = <0x615>;
|
|
parent-node = <0x5c9>;
|
|
drv-voting-index = <0x02>;
|
|
constituent-paths = <0x0a 0x0b 0x0f>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x106>;
|
|
client-name = "ife1";
|
|
node-name = "ife1-ubwc-wr";
|
|
cell-index = <0x16>;
|
|
};
|
|
|
|
ife2-ubwc-wr {
|
|
phandle = <0x616>;
|
|
parent-node = <0x5ca>;
|
|
drv-voting-index = <0x03>;
|
|
constituent-paths = <0x0a 0x0b 0x0f>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x106>;
|
|
client-name = "ife2";
|
|
node-name = "ife2-ubwc-wr";
|
|
cell-index = <0x17>;
|
|
};
|
|
|
|
ife0-rdi-pixel-raw-wr {
|
|
phandle = <0x617>;
|
|
parent-node = <0x5ca>;
|
|
drv-voting-index = <0x01>;
|
|
constituent-paths = <0x04 0x05 0x06 0x07 0x0e 0x0c 0x0d 0x12>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x105>;
|
|
client-name = "ife0";
|
|
node-name = "ife0-rdi-pixel-raw-wr";
|
|
cell-index = <0x18>;
|
|
};
|
|
|
|
ife1-rdi-pixel-raw-wr {
|
|
phandle = <0x618>;
|
|
parent-node = <0x5ca>;
|
|
drv-voting-index = <0x02>;
|
|
constituent-paths = <0x04 0x05 0x06 0x07 0x0e 0x0c 0x0d 0x12>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x104>;
|
|
client-name = "ife1";
|
|
node-name = "ife1-rdi-pixel-raw-wr";
|
|
cell-index = <0x19>;
|
|
};
|
|
|
|
ife2-rdi-pixel-raw-wr {
|
|
phandle = <0x619>;
|
|
parent-node = <0x5c9>;
|
|
drv-voting-index = <0x03>;
|
|
constituent-paths = <0x04 0x05 0x06 0x07 0x0e 0x0c 0x0d 0x12>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x104>;
|
|
client-name = "ife2";
|
|
node-name = "ife2-rdi-pixel-raw-wr";
|
|
cell-index = <0x1a>;
|
|
};
|
|
|
|
ife0-pdaf-linear-wr {
|
|
phandle = <0x61a>;
|
|
parent-node = <0x5cb>;
|
|
drv-voting-index = <0x01>;
|
|
constituent-paths = <0x08 0x10 0x11 0x13>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x109>;
|
|
client-name = "ife0";
|
|
node-name = "ife0-pdaf-linear-wr";
|
|
cell-index = <0x1b>;
|
|
};
|
|
|
|
ife1-pdaf-linear-wr {
|
|
phandle = <0x61b>;
|
|
parent-node = <0x5cb>;
|
|
drv-voting-index = <0x02>;
|
|
constituent-paths = <0x08 0x10 0x11 0x13>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x109>;
|
|
client-name = "ife1";
|
|
node-name = "ife1-pdaf-linear-wr";
|
|
cell-index = <0x1c>;
|
|
};
|
|
|
|
ife2-pdaf-linear-wr {
|
|
phandle = <0x61c>;
|
|
parent-node = <0x5cb>;
|
|
drv-voting-index = <0x03>;
|
|
constituent-paths = <0x08 0x10 0x11 0x13>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x109>;
|
|
client-name = "ife2";
|
|
node-name = "ife2-pdaf-linear-wr";
|
|
cell-index = <0x1d>;
|
|
};
|
|
|
|
ife4-rdi-stats-pixel-raw-wr {
|
|
phandle = <0x61d>;
|
|
parent-node = <0x5cb>;
|
|
constituent-paths = <0x04 0x05 0x06 0x07 0x03>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ife4";
|
|
node-name = "ife4-rdi-stats-pixel-raw-wr";
|
|
cell-index = <0x1e>;
|
|
};
|
|
|
|
ife3-rdi-stats-pixel-raw-wr {
|
|
phandle = <0x61e>;
|
|
parent-node = <0x5cb>;
|
|
constituent-paths = <0x04 0x05 0x06 0x07 0x03>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ife3";
|
|
node-name = "ife3-rdi-stats-pixel-raw-wr";
|
|
cell-index = <0x1f>;
|
|
};
|
|
|
|
ife0-stats-wr {
|
|
phandle = <0x61f>;
|
|
parent-node = <0x5cc>;
|
|
drv-voting-index = <0x01>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x03>;
|
|
client-name = "ife0";
|
|
node-name = "ife0-stats-wr";
|
|
cell-index = <0x20>;
|
|
};
|
|
|
|
ife1-stats-wr {
|
|
phandle = <0x620>;
|
|
parent-node = <0x5cc>;
|
|
drv-voting-index = <0x02>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x03>;
|
|
client-name = "ife1";
|
|
node-name = "ife1-stats-wr";
|
|
cell-index = <0x21>;
|
|
};
|
|
|
|
ife2-stats-wr {
|
|
phandle = <0x621>;
|
|
parent-node = <0x5cc>;
|
|
drv-voting-index = <0x03>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x03>;
|
|
client-name = "ife2";
|
|
node-name = "ife2-stats-wr";
|
|
cell-index = <0x22>;
|
|
};
|
|
|
|
ipe0-all-wr {
|
|
phandle = <0x622>;
|
|
parent-node = <0x5c7>;
|
|
constituent-paths = <0x22 0x23 0x24 0x25>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ipe0";
|
|
node-name = "ipe0-all-wr";
|
|
cell-index = <0x23>;
|
|
};
|
|
|
|
cre0-all-wr {
|
|
phandle = <0x623>;
|
|
parent-node = <0x5cd>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "cre0";
|
|
node-name = "cre0-all-wr";
|
|
cell-index = <0x24>;
|
|
};
|
|
|
|
jpeg-enc0-all-wr {
|
|
phandle = <0x624>;
|
|
parent-node = <0x5ce>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-enc0";
|
|
node-name = "jpeg-enc0-all-wr";
|
|
cell-index = <0x25>;
|
|
};
|
|
|
|
jpeg-dma0-all-wr {
|
|
phandle = <0x625>;
|
|
parent-node = <0x5ce>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-dma0";
|
|
node-name = "jpeg-dma0-all-wr";
|
|
cell-index = <0x26>;
|
|
};
|
|
|
|
jpeg-enc1-all-wr {
|
|
phandle = <0x626>;
|
|
parent-node = <0x5ce>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-enc1";
|
|
node-name = "jpeg-enc1-all-wr";
|
|
cell-index = <0x27>;
|
|
};
|
|
|
|
jpeg-dma1-all-wr {
|
|
phandle = <0x627>;
|
|
parent-node = <0x5ce>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-dma1";
|
|
node-name = "jpeg-dma1-all-wr";
|
|
cell-index = <0x28>;
|
|
};
|
|
|
|
cre0-all-rd {
|
|
phandle = <0x628>;
|
|
parent-node = <0x5cf>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "cre0";
|
|
node-name = "cre0-all-rd";
|
|
cell-index = <0x29>;
|
|
};
|
|
|
|
jpeg0-enc0-all-rd {
|
|
phandle = <0x629>;
|
|
parent-node = <0x5d0>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-enc0";
|
|
node-name = "jpeg-enc0-rd";
|
|
cell-index = <0x2a>;
|
|
};
|
|
|
|
jpeg0-dma0-all-rd {
|
|
phandle = <0x62a>;
|
|
parent-node = <0x5d0>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-dma0";
|
|
node-name = "jpeg-dma0-rd";
|
|
cell-index = <0x2b>;
|
|
};
|
|
|
|
jpeg1-enc1-all-rd {
|
|
phandle = <0x62b>;
|
|
parent-node = <0x5d0>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-enc1";
|
|
node-name = "jpeg-enc1-rd";
|
|
cell-index = <0x2c>;
|
|
};
|
|
|
|
jpeg1-dma1-all-rd {
|
|
phandle = <0x62c>;
|
|
parent-node = <0x5d0>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "jpeg-dma1";
|
|
node-name = "jpeg-dma1-rd";
|
|
cell-index = <0x2d>;
|
|
};
|
|
|
|
ipe0-ref-rd {
|
|
phandle = <0x62d>;
|
|
parent-node = <0x5c8>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x21>;
|
|
client-name = "ipe0";
|
|
node-name = "ipe0-ref-rd";
|
|
cell-index = <0x2e>;
|
|
};
|
|
|
|
ipe0-in-rd {
|
|
phandle = <0x62e>;
|
|
parent-node = <0x5c8>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x20>;
|
|
client-name = "ipe0";
|
|
node-name = "ipe0-in-rd";
|
|
cell-index = <0x2f>;
|
|
};
|
|
|
|
rt-cdm0-all-rd {
|
|
phandle = <0x62f>;
|
|
parent-node = <0x5d1>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "rt-cdm0";
|
|
node-name = "rt-cdm0-all-rd";
|
|
cell-index = <0x30>;
|
|
};
|
|
|
|
rt-cdm1-all-rd {
|
|
phandle = <0x630>;
|
|
parent-node = <0x5d1>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "rt-cdm1";
|
|
node-name = "rt-cdm1-all-rd";
|
|
cell-index = <0x31>;
|
|
};
|
|
|
|
rt-cdm2-all-rd {
|
|
phandle = <0x631>;
|
|
parent-node = <0x5d1>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "rt-cdm2";
|
|
node-name = "rt-cdm2-all-rd";
|
|
cell-index = <0x32>;
|
|
};
|
|
|
|
rt-cdm3-all-rd {
|
|
phandle = <0x632>;
|
|
parent-node = <0x5d1>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "rt-cdm3";
|
|
node-name = "rt-cdm3-all-rd";
|
|
cell-index = <0x33>;
|
|
};
|
|
|
|
rt-cdm4-all-rd {
|
|
phandle = <0x633>;
|
|
parent-node = <0x5d1>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "rt-cdm4";
|
|
node-name = "rt-cdm4-all-rd";
|
|
cell-index = <0x34>;
|
|
};
|
|
|
|
icp0-all-rd {
|
|
phandle = <0x634>;
|
|
parent-node = <0x5d2>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "icp0";
|
|
node-name = "icp0-all-rd";
|
|
cell-index = <0x35>;
|
|
};
|
|
|
|
icp1-all-rd {
|
|
phandle = <0x635>;
|
|
parent-node = <0x5d2>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "icp1";
|
|
node-name = "icp1-all-rd";
|
|
cell-index = <0x36>;
|
|
};
|
|
|
|
ofe0-linear-wr {
|
|
phandle = <0x636>;
|
|
parent-node = <0x5cd>;
|
|
constituent-paths = <0xa7 0xa8 0xa9 0xaa 0xab>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ofe0";
|
|
node-name = "ofe0-linear-wr";
|
|
cell-index = <0x37>;
|
|
};
|
|
|
|
ofe0-in-rd {
|
|
phandle = <0x637>;
|
|
parent-node = <0x5d3>;
|
|
constituent-paths = <0xa0 0xa1 0xa2>;
|
|
traffic-transaction-type = <0x00>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ofe0";
|
|
node-name = "ofe0-in-rd";
|
|
cell-index = <0x38>;
|
|
};
|
|
|
|
ofe0-ubwc-wr {
|
|
phandle = <0x638>;
|
|
parent-node = <0x5d4>;
|
|
constituent-paths = <0xa3 0xa4 0xa5 0xa6>;
|
|
traffic-transaction-type = <0x01>;
|
|
traffic-data = <0x100>;
|
|
client-name = "ofe0";
|
|
node-name = "ofe0-ubwc-wr";
|
|
cell-index = <0x39>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,cam-cdm-intf {
|
|
status = "ok";
|
|
cdm-client-names = "vfe\0jpegdma\0jpegenc";
|
|
num-hw-cdm = <0x01>;
|
|
label = "cam-cdm-intf";
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-cdm-intf";
|
|
};
|
|
|
|
qcom,rt-cdm0@ac7f000 {
|
|
status = "ok";
|
|
single-context-cdm;
|
|
cam-hw-mid = <0x00>;
|
|
cam_hw_pid = <0x18>;
|
|
fifo-depths = <0x40 0x00 0x00 0x00>;
|
|
config-fifo;
|
|
cdm-client-names = "ife0";
|
|
nrt-device;
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x00>;
|
|
clocks = <0x3e 0x00>;
|
|
clock-names = "cam_cc_cam_top_ahb_clk";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x1c8 0x01>;
|
|
interrupt-names = "rt-cdm0";
|
|
reg-cam-base = <0x7f000>;
|
|
reg-names = "rt-cdm0";
|
|
reg = <0xac7f000 0x580>;
|
|
label = "rt-cdm";
|
|
compatible = "qcom,cam-rt-cdm2_2";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,rt-cdm1@ac80000 {
|
|
status = "ok";
|
|
single-context-cdm;
|
|
cam-hw-mid = <0x00>;
|
|
cam_hw_pid = <0x19>;
|
|
fifo-depths = <0x40 0x00 0x00 0x00>;
|
|
config-fifo;
|
|
cdm-client-names = "ife1";
|
|
nrt-device;
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x00>;
|
|
clocks = <0x3e 0x00>;
|
|
clock-names = "cam_cc_cam_top_ahb_clk";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x298 0x01>;
|
|
interrupt-names = "rt-cdm1";
|
|
reg-cam-base = <0x80000>;
|
|
reg-names = "rt-cdm1";
|
|
reg = <0xac80000 0x580>;
|
|
label = "rt-cdm";
|
|
compatible = "qcom,cam-rt-cdm2_2";
|
|
cell-index = <0x01>;
|
|
};
|
|
|
|
qcom,rt-cdm2@ac81000 {
|
|
status = "ok";
|
|
single-context-cdm;
|
|
cam-hw-mid = <0x00>;
|
|
cam_hw_pid = <0x1a>;
|
|
fifo-depths = <0x40 0x00 0x00 0x00>;
|
|
config-fifo;
|
|
cdm-client-names = "ife2";
|
|
nrt-device;
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x00>;
|
|
clocks = <0x3e 0x00>;
|
|
clock-names = "cam_cc_cam_top_ahb_clk";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x2be 0x01>;
|
|
interrupt-names = "rt-cdm2";
|
|
reg-cam-base = <0x81000>;
|
|
reg-names = "rt-cdm2";
|
|
reg = <0xac81000 0x580>;
|
|
label = "rt-cdm";
|
|
compatible = "qcom,cam-rt-cdm2_2";
|
|
cell-index = <0x02>;
|
|
};
|
|
|
|
qcom,rt-cdm3@ac82000 {
|
|
status = "ok";
|
|
single-context-cdm;
|
|
cam-hw-mid = <0x00>;
|
|
cam_hw_pid = <0x1b>;
|
|
fifo-depths = <0x40 0x00 0x00 0x00>;
|
|
config-fifo;
|
|
cdm-client-names = "ife3";
|
|
nrt-device;
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x00>;
|
|
clocks = <0x3e 0x00>;
|
|
clock-names = "cam_cc_cam_top_ahb_clk";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x15c 0x01>;
|
|
interrupt-names = "rt-cdm3";
|
|
reg-cam-base = "\0\b ";
|
|
reg-names = "rt-cdm3";
|
|
reg = <0xac82000 0x580>;
|
|
label = "rt-cdm";
|
|
compatible = "qcom,cam-rt-cdm2_2";
|
|
cell-index = <0x03>;
|
|
};
|
|
|
|
qcom,rt-cdm4@ac83000 {
|
|
status = "ok";
|
|
single-context-cdm;
|
|
cam-hw-mid = <0x00>;
|
|
cam_hw_pid = <0x1c>;
|
|
fifo-depths = <0x40 0x00 0x00 0x00>;
|
|
config-fifo;
|
|
cdm-client-names = "ife4";
|
|
nrt-device;
|
|
clock-cntl-level = "turbo";
|
|
clock-rates = <0x00>;
|
|
clocks = <0x3e 0x00>;
|
|
clock-names = "cam_cc_cam_top_ahb_clk";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x15d 0x01>;
|
|
interrupt-names = "rt-cdm4";
|
|
reg-cam-base = "\0\b0";
|
|
reg-names = "rt-cdm4";
|
|
reg = <0xac83000 0x580>;
|
|
label = "rt-cdm";
|
|
compatible = "qcom,cam-rt-cdm2_2";
|
|
cell-index = <0x04>;
|
|
};
|
|
|
|
qcom,cam-isp {
|
|
status = "ok";
|
|
arch-compat = "mc_tfe";
|
|
compatible = "qcom,cam-isp";
|
|
};
|
|
|
|
qcom,csid0@ad26000 {
|
|
phandle = <0x639>;
|
|
status = "ok";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "csid_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0xfe502ab 0x00 0x00 0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>;
|
|
clocks = <0x3e 0x2b 0x3e 0x2a 0x3e 0x2c>;
|
|
clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x259 0x01>;
|
|
interrupt-names = "csid0";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = <0x127000>;
|
|
reg = <0xad27000 0x2b00>;
|
|
reg-names = "csid";
|
|
compatible = "qcom,csid980";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,ife0@ac86000 {
|
|
phandle = <0x63a>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x08 0x0d 0x10 0x04>;
|
|
ubwc-static-cfg = <0x1026 0x1036>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "tfe_0_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x15796fc0 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x258d0980 0x00 0x00 0x00 0x00 0x00 0x00 0x2aad4b00 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x6e 0x3e 0x6c 0x3e 0x6d 0x3e 0x0d 0x3e 0x6b 0x3e 0x6a 0x3e 0x0c>;
|
|
clock-names = "tfe_0_main_fast_ahb\0tfe_0_clk_src\0tfe_0_main_clk\0cam_cc_camnoc_rt_tfe_0_main_clk\0tfe_0_bayer_fast_ahb\0tfe_0_bayer_clk\0cam_cc_camnoc_rt_tfe_0_bayer_clk";
|
|
tfe0-supply = <0x436>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc\0tfe0";
|
|
interrupts = <0x00 0x1b1 0x01>;
|
|
interrupt-names = "tfe0";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = "\0\b`";
|
|
reg = <0xac86000 0x10000>;
|
|
reg-names = "ife";
|
|
compatible = "qcom,mc_tfe980";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,csid1@ad29000 {
|
|
phandle = <0x63b>;
|
|
status = "ok";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "csid_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0xfe502ab 0x00 0x00 0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>;
|
|
clocks = <0x3e 0x2b 0x3e 0x2a 0x3e 0x2c>;
|
|
clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x25b 0x01>;
|
|
interrupt-names = "csid1";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = <0x12a000>;
|
|
reg = <0xad2a000 0x2b00>;
|
|
reg-names = "csid";
|
|
compatible = "qcom,csid980";
|
|
cell-index = <0x01>;
|
|
};
|
|
|
|
qcom,ife1@ac96000 {
|
|
phandle = <0x63c>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x09 0x0e 0x11 0x05>;
|
|
ubwc-static-cfg = <0x1026 0x1036>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "tfe_1_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x15796fc0 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x258d0980 0x00 0x00 0x00 0x00 0x00 0x00 0x2aad4b00 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x73 0x3e 0x71 0x3e 0x72 0x3e 0x0f 0x3e 0x70 0x3e 0x6f 0x3e 0x0e>;
|
|
clock-names = "tfe_1_main_fast_ahb\0tfe_1_clk_src\0tfe_1_main_clk\0cam_cc_camnoc_rt_tfe_1_main_clk\0tfe_1_bayer_fast_ahb\0tfe_1_bayer_clk\0cam_cc_camnoc_rt_tfe_1_bayer_clk";
|
|
tfe1-supply = <0x437>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc\0tfe1";
|
|
interrupts = <0x00 0x1b4 0x01>;
|
|
interrupt-names = "tfe1";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = "\0\t`";
|
|
reg = <0xac96000 0x10000>;
|
|
reg-names = "ife";
|
|
compatible = "qcom,mc_tfe980";
|
|
cell-index = <0x01>;
|
|
};
|
|
|
|
qcom,csid2@ad2c000 {
|
|
phandle = <0x63d>;
|
|
status = "ok";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "csid_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0xfe502ab 0x00 0x00 0x17d78400 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00 0x1c9c3800 0x00 0x00>;
|
|
clocks = <0x3e 0x2b 0x3e 0x2a 0x3e 0x2c>;
|
|
clock-names = "csid_clk_src\0csid_clk\0csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x1af 0x01>;
|
|
interrupt-names = "csid2";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = <0x12d000>;
|
|
reg = <0xad2d000 0x2b00>;
|
|
reg-names = "csid";
|
|
compatible = "qcom,csid980";
|
|
cell-index = <0x02>;
|
|
};
|
|
|
|
qcom,ife2@aca6000 {
|
|
phandle = <0x63e>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x0a 0x0c 0x12 0x06>;
|
|
ubwc-static-cfg = <0x1026 0x1036>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "tfe_2_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x15796fc0 0x00 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x00 0x258d0980 0x00 0x00 0x00 0x00 0x00 0x00 0x2aad4b00 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00 0x00 0x31a69240 0x00 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x78 0x3e 0x76 0x3e 0x77 0x3e 0x11 0x3e 0x75 0x3e 0x74 0x3e 0x10>;
|
|
clock-names = "tfe_2_main_fast_ahb\0tfe_2_clk_src\0tfe_2_main_clk\0cam_cc_camnoc_rt_tfe_2_main_clk\0tfe_2_bayer_fast_ahb\0tfe_2_bayer_clk\0cam_cc_camnoc_rt_tfe_2_bayer_clk";
|
|
tfe2-supply = <0x438>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc\0tfe2";
|
|
interrupts = <0x00 0x1c9 0x01>;
|
|
interrupt-names = "tfe2";
|
|
rt-wrapper-base = "\0\b`";
|
|
reg-cam-base = "\0\n`";
|
|
reg = <0xaca6000 0x10000>;
|
|
reg-names = "ife";
|
|
compatible = "qcom,mc_tfe980";
|
|
cell-index = <0x02>;
|
|
};
|
|
|
|
qcom,csid-lite0@ad6c000 {
|
|
phandle = <0x63f>;
|
|
status = "ok";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ife_lite_csid_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0xfe502ab 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x3d 0x3e 0x42 0x3e 0x41 0x3e 0x40 0x3e 0x3e 0x3e 0x0b>;
|
|
clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_camnoc_rt_ife_lite_clk";
|
|
shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x25d 0x01>;
|
|
interrupt-names = "csid-lite0";
|
|
rt-wrapper-base = <0x16c000>;
|
|
reg-cam-base = <0x16d000>;
|
|
reg = <0xad6d000 0xa00>;
|
|
reg-names = "csid-lite";
|
|
compatible = "qcom,csid-lite980";
|
|
cell-index = <0x03>;
|
|
};
|
|
|
|
qcom,ife-lite0@ad6c000 {
|
|
phandle = <0x640>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x13>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ife_lite_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x00 0x00 0xfe502ab 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>;
|
|
clocks = <0x3e 0x3d 0x3e 0x41 0x3e 0x40 0x3e 0x3f 0x3e 0x3e 0x3e 0x0b>;
|
|
clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_camnoc_rt_ife_lite_clk";
|
|
shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x25e 0x01>;
|
|
interrupt-names = "ife-lite0";
|
|
rt-wrapper-base = <0x16c000>;
|
|
reg-cam-base = <0x16d000>;
|
|
reg = <0xad6d000 0x2800>;
|
|
reg-names = "ife-lite";
|
|
compatible = "qcom,vfe-lite980";
|
|
cell-index = <0x03>;
|
|
};
|
|
|
|
qcom,csid-lite1@ad71000 {
|
|
phandle = <0x641>;
|
|
status = "ok";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ife_lite_csid_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0xfe502ab 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x3d 0x3e 0x42 0x3e 0x41 0x3e 0x40 0x3e 0x3e 0x3e 0x0b>;
|
|
clock-names = "ife_lite_ahb\0ife_lite_csid_clk_src\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk\0cam_cc_camnoc_rt_ife_lite_clk";
|
|
shared-clks = <0x00 0x01 0x00 0x00 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x178 0x01>;
|
|
interrupt-names = "csid-lite1";
|
|
rt-wrapper-base = <0x16c000>;
|
|
reg-cam-base = <0x172000>;
|
|
reg = <0xad72000 0xa00>;
|
|
reg-names = "csid-lite";
|
|
compatible = "qcom,csid-lite980";
|
|
cell-index = <0x04>;
|
|
};
|
|
|
|
qcom,ife-lite1@ad71000 {
|
|
phandle = <0x642>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x14>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ife_lite_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x00 0x00 0xfe502ab 0x00 0x00 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x00 0x00 0x1c9c3800 0x00 0x00>;
|
|
clocks = <0x3e 0x3d 0x3e 0x41 0x3e 0x40 0x3e 0x3f 0x3e 0x3e 0x3e 0x0b>;
|
|
clock-names = "ife_lite_ahb\0ife_lite_csid_clk\0ife_lite_cphy_rx_clk\0ife_lite_clk_src\0ife_lite_clk\0cam_cc_camnoc_rt_ife_lite_clk";
|
|
shared-clks = <0x00 0x00 0x00 0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x179 0x01>;
|
|
interrupt-names = "ife-lite1";
|
|
rt-wrapper-base = <0x16c000>;
|
|
reg-cam-base = <0x172000>;
|
|
reg = <0xad72000 0x2800>;
|
|
reg-names = "ife-lite";
|
|
compatible = "qcom,vfe-lite980";
|
|
cell-index = <0x04>;
|
|
};
|
|
|
|
qcom,tpg13@ad8b000 {
|
|
phandle = <0x643>;
|
|
status = "ok";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x1c9c3800 0x00>;
|
|
clocks = <0x3e 0x1a 0x3e 0x2c>;
|
|
clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00>;
|
|
interrupts = <0x00 0x19d 0x01>;
|
|
interrupt-names = "tpg0";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
reg-cam-base = <0x18b000 0x4000>;
|
|
reg = <0xad8b000 0x400 0xac04000 0x1000>;
|
|
reg-names = "tpg0\0cam_cpas_top";
|
|
compatible = "qcom,cam-tpg104";
|
|
phy-id = <0x00>;
|
|
cell-index = <0x0d>;
|
|
};
|
|
|
|
qcom,tpg14@ad8c000 {
|
|
phandle = <0x644>;
|
|
status = "ok";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x1c9c3800 0x00>;
|
|
clocks = <0x3e 0x1a 0x3e 0x2c>;
|
|
clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00>;
|
|
interrupts = <0x00 0x1a0 0x01>;
|
|
interrupt-names = "tpg1";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
reg-cam-base = <0x18c000 0x4000>;
|
|
reg = <0xad8c000 0x400 0xac04000 0x1000>;
|
|
reg-names = "tpg1\0cam_cpas_top";
|
|
compatible = "qcom,cam-tpg104";
|
|
phy-id = <0x01>;
|
|
cell-index = <0x0e>;
|
|
};
|
|
|
|
qcom,tpg15@ad8d000 {
|
|
phandle = <0x645>;
|
|
status = "ok";
|
|
src-clock-name = "cphy_rx_clk_src";
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0nominal";
|
|
clock-rates = <0xfe502ab 0x00 0x17d78400 0x00 0x1c9c3800 0x00>;
|
|
clocks = <0x3e 0x1a 0x3e 0x2c>;
|
|
clock-names = "cphy_rx_clk_src\0csid_csiphy_rx_clk";
|
|
shared-clks = <0x01 0x00>;
|
|
interrupts = <0x00 0x1a1 0x01>;
|
|
interrupt-names = "tpg2";
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
reg-cam-base = <0x18d000 0x4000>;
|
|
reg = <0xad8d000 0x400 0xac04000 0x1000>;
|
|
reg-names = "tpg2\0cam_cpas_top";
|
|
compatible = "qcom,cam-tpg104";
|
|
phy-id = <0x02>;
|
|
cell-index = <0x0f>;
|
|
};
|
|
|
|
qcom,cam-icp0 {
|
|
synx_signaling_en;
|
|
ipe_bps_pc_en;
|
|
icp_use_pil;
|
|
icp_pc_en;
|
|
status = "ok";
|
|
num-ipe = <0x01>;
|
|
num-icp = <0x01>;
|
|
compat-hw-name = "qcom,icp0\0qcom,ipe0";
|
|
cell-index = <0x00>;
|
|
compatible = "qcom,cam-icp0";
|
|
};
|
|
|
|
qcom,cam-icp1 {
|
|
ipe_bps_pc_en;
|
|
icp_use_pil;
|
|
icp_pc_en;
|
|
status = "ok";
|
|
num-ofe = <0x01>;
|
|
num-icp = <0x01>;
|
|
compat-hw-name = "qcom,icp1\0qcom,ofe";
|
|
cell-index = <0x01>;
|
|
compatible = "qcom,cam-icp1";
|
|
};
|
|
|
|
qcom,icp0@ac05000 {
|
|
phandle = <0x646>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x0b>;
|
|
fw-pas-id = <0x21>;
|
|
qos-val = <0x808>;
|
|
ubwc-ipe-write-cfg = <0x1620f 0x1620f>;
|
|
ubwc-ipe-fetch-cfg = <0x3f083 0x3f083>;
|
|
fw_name = "CAMERA_ICP";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "icp_clk_src";
|
|
nrt-device;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x11e1a300 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>;
|
|
clocks = <0x3e 0x37 0x3e 0x39 0x3e 0x38 0x3e 0x66>;
|
|
clock-names = "icp_ahb_clk\0icp_clk_src\0icp_clk\0camcc_debug_clk";
|
|
memory-region = <0x368>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x1cf 0x01>;
|
|
interrupt-names = "icp";
|
|
reg-cam-base = <0x6000 0x9000>;
|
|
reg-names = "icp_csr\0icp_wd0";
|
|
reg = <0xac06000 0x1000 0xac09000 0x1000>;
|
|
icp-version = <0x201>;
|
|
compatible = "qcom,cam-icp_v2_1";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,icp1@ac150000 {
|
|
phandle = <0x647>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x0a>;
|
|
fw-pas-id = <0x32>;
|
|
qos-val = <0x808>;
|
|
ubwc-ofe-write-cfg = <0x1620f 0x1620f>;
|
|
ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>;
|
|
fw_name = "CAMERA_ICP_1";
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "icp_1_clk_src";
|
|
nrt-device;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x11e1a300 0x00 0x00 0x00 0x17d78400 0x00 0x00 0x00 0x1c9c3800 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00 0x00 0x23c34600 0x00 0x00>;
|
|
clocks = <0x3e 0x3a 0x3e 0x3c 0x3e 0x3b 0x3e 0x66>;
|
|
clock-names = "icp_1_ahb_clk\0icp_1_clk_src\0icp_1_clk\0camcc_debug_clk";
|
|
memory-region = <0x369>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x291 0x01>;
|
|
interrupt-names = "icp1";
|
|
reg-cam-base = <0x16000 0x19000>;
|
|
reg-names = "icp_csr\0icp_wd0";
|
|
reg = <0xac16000 0x1000 0xac19000 0x1000>;
|
|
icp-version = <0x201>;
|
|
compatible = "qcom,cam-icp_v2_1";
|
|
cell-index = <0x01>;
|
|
};
|
|
|
|
qcom,ipe0@ac42000 {
|
|
phandle = <0x648>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x0f 0x0e 0x1a 0x1b>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ipe_nps_clk_src";
|
|
nrt-device;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x00 0x00 0x13d18c20 0x00 0x00 0x00 0x00 0x00 0x00 0x1c4fecc0 0x00 0x00 0x00 0x00 0x00 0x00 0x2245cdc0 0x00 0x00 0x00 0x00 0x00 0x00 0x283baec0 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00 0x00 0x00 0x00 0x312c8040 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x43 0x3e 0x46 0x3e 0x48 0x3e 0x45 0x3e 0x44 0x3e 0x47 0x3e 0x05>;
|
|
clock-names = "ipe_nps_ahb_clk\0ipe_nps_fast_ahb_clk\0ipe_pps_fast_ahb_clk\0ipe_nps_clk_src\0ipe_nps_clk\0ipe_pps_clk\0cam_cc_camnoc_nrt_ipe_nps_clk";
|
|
ipe0-vdd-supply = <0x434>;
|
|
regulator-names = "ipe0-vdd";
|
|
reg-cam-base = <0x42000>;
|
|
reg-names = "ipe0_top";
|
|
reg = <0xac42000 0x18000>;
|
|
compatible = "qcom,cam-ipe680";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,ofe@ac2a000 {
|
|
phandle = <0x649>;
|
|
status = "ok";
|
|
cam_hw_pid = <0x0d 0x1c 0x06>;
|
|
clock-control-debugfs = "true";
|
|
src-clock-name = "ofe_clk_src";
|
|
nrt-device;
|
|
clock-cntl-level = "lowsvsd1\0lowsvs\0svs\0svs_l1\0nominal\0turbo";
|
|
clock-rates = <0x00 0x00 0x1431ad80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1cd94100 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x22eda680 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x29020c00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3220a440 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3220a440 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
clocks = <0x3e 0x06 0x3e 0x07 0x3e 0x4f 0x3e 0x52 0x3e 0x08 0x3e 0x4c 0x3e 0x4d 0x3e 0x4e 0x3e 0x51 0x3e 0x50 0x3e 0x53>;
|
|
clock-names = "camnoc_nrt_ofe_anchor\0camnoc_nrt_ofe_hdr\0ofe_clk_src\0ofe_main_clk\0camnoc_nrt_ofe_main_clk\0ofe_ahb_clk\0ofe_anchor_clk\0ofe_anchor_fast_ahb\0ofe_hdr_fast_ahb\0ofe_hdr_clk\0ofe_main_fast_ahb";
|
|
ofe0-vdd-supply = <0x435>;
|
|
regulator-names = "ofe0-vdd";
|
|
reg-cam-base = <0x2a000>;
|
|
reg-names = "ofe0_top";
|
|
reg = <0xac2a000 0x18000>;
|
|
compatible = "qcom,cam-ofe";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,cam-jpeg {
|
|
status = "ok";
|
|
num-jpeg-dma = <0x01>;
|
|
num-jpeg-enc = <0x01>;
|
|
compat-hw-name = "qcom,jpegenc0\0qcom,jpegdma0";
|
|
compatible = "qcom,cam-jpeg";
|
|
};
|
|
|
|
qcom,jpegenc0@ac25000 {
|
|
phandle = <0x64a>;
|
|
status = "ok";
|
|
cam_hw_wr_mid = <0x01>;
|
|
cam_hw_rd_mid = <0x00>;
|
|
cam_hw_pid = <0x11 0x13>;
|
|
nrt-device;
|
|
clock-cntl-level = "nominal";
|
|
src-clock-name = "jpegenc_clk_src";
|
|
clock-rates = <0x23c34600 0x00 0x00>;
|
|
clocks = <0x3e 0x4b 0x3e 0x49 0x3e 0x4a>;
|
|
clock-names = "jpegenc_clk_src\0jpegenc_0_clk\0jpegenc_1_clk";
|
|
shared-clks = <0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x1db 0x01>;
|
|
interrupt-names = "jpeg_enc0";
|
|
reg-cam-base = <0x25000 0x62000>;
|
|
reg = <0xac25000 0x1000 0xac62000 0x9200>;
|
|
reg-names = "jpegenc_hw\0cam_camnoc_nrt";
|
|
compatible = "qcom,cam_jpeg_enc_780";
|
|
cell-index = <0x00>;
|
|
};
|
|
|
|
qcom,jpegdma0@ac26000 {
|
|
phandle = <0x64b>;
|
|
status = "ok";
|
|
cam_hw_wr_mid = <0x01>;
|
|
cam_hw_rd_mid = <0x00>;
|
|
cam_hw_pid = <0x10 0x12>;
|
|
nrt-device;
|
|
clock-cntl-level = "nominal";
|
|
src-clock-name = "jpegdma_clk_src";
|
|
clock-rates = <0x23c34600 0x00 0x00>;
|
|
clocks = <0x3e 0x4b 0x3e 0x49 0x3e 0x4a>;
|
|
clock-names = "jpegdma_clk_src\0jpegdma_0_clk\0jpegdma_1_clk";
|
|
shared-clks = <0x01 0x00 0x00>;
|
|
gdsc-supply = <0x5b>;
|
|
regulator-names = "gdsc";
|
|
interrupts = <0x00 0x174 0x01>;
|
|
interrupt-names = "jpeg_dma0";
|
|
reg-cam-base = <0x26000 0x62000>;
|
|
reg = <0xac26000 0x1000 0xac62000 0x9200>;
|
|
reg-names = "jpegdma_hw\0cam_camnoc_nrt";
|
|
compatible = "qcom,cam_jpeg_dma_780";
|
|
cell-index = <0x00>;
|
|
};
|
|
};
|
|
|
|
hypervisor {
|
|
phandle = <0x557>;
|
|
|
|
qcom,gh-watchdog {
|
|
phandle = <0x558>;
|
|
};
|
|
};
|
|
|
|
sched_walt {
|
|
panic_on_walt_bug = <0x4544de18>;
|
|
phandle = <0x559>;
|
|
};
|
|
|
|
__symbols__ {
|
|
cam_jpeg_dma0 = "/soc/qcom,jpegdma0@ac26000";
|
|
cam_jpeg_enc0 = "/soc/qcom,jpegenc0@ac25000";
|
|
cam_ofe = "/soc/qcom,ofe@ac2a000";
|
|
cam_ipe0 = "/soc/qcom,ipe0@ac42000";
|
|
cam_icp1 = "/soc/qcom,icp1@ac150000";
|
|
cam_icp0 = "/soc/qcom,icp0@ac05000";
|
|
cam_csiphy_tpg15 = "/soc/qcom,tpg15@ad8d000";
|
|
cam_csiphy_tpg14 = "/soc/qcom,tpg14@ad8c000";
|
|
cam_csiphy_tpg13 = "/soc/qcom,tpg13@ad8b000";
|
|
cam_vfe_lite1 = "/soc/qcom,ife-lite1@ad71000";
|
|
cam_csid_lite1 = "/soc/qcom,csid-lite1@ad71000";
|
|
cam_vfe_lite0 = "/soc/qcom,ife-lite0@ad6c000";
|
|
cam_csid_lite0 = "/soc/qcom,csid-lite0@ad6c000";
|
|
cam_vfe2 = "/soc/qcom,ife2@aca6000";
|
|
cam_csid2 = "/soc/qcom,csid2@ad2c000";
|
|
cam_vfe1 = "/soc/qcom,ife1@ac96000";
|
|
cam_csid1 = "/soc/qcom,csid1@ad29000";
|
|
cam_vfe0 = "/soc/qcom,ife0@ac86000";
|
|
cam_csid0 = "/soc/qcom,csid0@ad26000";
|
|
ofe0_ubwc_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ofe0-ubwc-wr";
|
|
ofe0_in_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ofe0-in-rd";
|
|
ofe0_linear_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ofe0-linear-wr";
|
|
icp1_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/icp1-all-rd";
|
|
icp0_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/icp0-all-rd";
|
|
rt_cdm4_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/rt-cdm4-all-rd";
|
|
rt_cdm3_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/rt-cdm3-all-rd";
|
|
rt_cdm2_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/rt-cdm2-all-rd";
|
|
rt_cdm1_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/rt-cdm1-all-rd";
|
|
rt_cdm0_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/rt-cdm0-all-rd";
|
|
ipe0_in_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ipe0-in-rd";
|
|
ipe0_ref_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ipe0-ref-rd";
|
|
jpeg_dma1_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg1-dma1-all-rd";
|
|
jpeg_enc1_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg1-enc1-all-rd";
|
|
jpeg_dma0_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg0-dma0-all-rd";
|
|
jpeg_enc0_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg0-enc0-all-rd";
|
|
cre0_all_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/cre0-all-rd";
|
|
jpeg_dma1_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg-dma1-all-wr";
|
|
jpeg_enc1_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg-enc1-all-wr";
|
|
jpeg_dma0_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg-dma0-all-wr";
|
|
jpeg_enc0_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/jpeg-enc0-all-wr";
|
|
cre0_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/cre0-all-wr";
|
|
ipe0_all_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ipe0-all-wr";
|
|
ife2_stats_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife2-stats-wr";
|
|
ife1_stats_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife1-stats-wr";
|
|
ife0_stats_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife0-stats-wr";
|
|
ife3_rdi_stats_pixel_raw_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife3-rdi-stats-pixel-raw-wr";
|
|
ife4_rdi_stats_pixel_raw_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife4-rdi-stats-pixel-raw-wr";
|
|
ife2_pdaf_linear_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife2-pdaf-linear-wr";
|
|
ife1_pdaf_linear_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife1-pdaf-linear-wr";
|
|
ife0_pdaf_linear_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife0-pdaf-linear-wr";
|
|
ife2_rdi_pixel_raw_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife2-rdi-pixel-raw-wr";
|
|
ife1_rdi_pixel_raw_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife1-rdi-pixel-raw-wr";
|
|
ife0_rdi_pixel_raw_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife0-rdi-pixel-raw-wr";
|
|
ife2_ubwc_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife2-ubwc-wr";
|
|
ife1_ubwc_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife1-ubwc-wr";
|
|
ife0_ubwc_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level0-nodes/ife0-ubwc-wr";
|
|
level1_nrt9_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt9-rd";
|
|
level1_nrt3_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt3-wr";
|
|
level1_nrt4_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt4-rd";
|
|
level1_nrt5_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt5-rd";
|
|
level1_nrt0_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt0-rd";
|
|
level1_nrt6_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt6-rd";
|
|
level1_nrt6_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt6-wr";
|
|
level1_nrt2_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-nrt2-wr";
|
|
level1_rt3_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-rt3-rd";
|
|
level1_rt4_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-rt4-wr1";
|
|
level1_rt3_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-rt3-wr";
|
|
level1_rt2_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-rt2-wr";
|
|
level1_rt1_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level1-nodes/level1-rt1-wr";
|
|
level2_icp_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level2-nodes/level2-icp-rd";
|
|
level2_nrt_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level2-nodes/level2-nrt-rd";
|
|
level2_nrt_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level2-nodes/level2-nrt-wr";
|
|
level2_rt_rd = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level2-nodes/level2-rt-rd";
|
|
level2_rt_wr = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level2-nodes/level2-rt-wr";
|
|
level3_nrt1_rd_wr_sum = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt1-rd-wr-sum";
|
|
level3_nrt0_rd_wr_sum = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-nrt0-rd-wr-sum";
|
|
level3_rt_rd_wr_sum = "/soc/qcom,cam-cpas@ac13000/camera-bus-nodes/level3-nodes/level3-rt-rd-wr-sum";
|
|
rt_cdm_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_cdm/iova-mem-map";
|
|
cam_smmu_cdm_resv_region = "/soc/qcom,cam_smmu/msm_cam_smmu_cdm/cam_smmu_cdm_resv_region";
|
|
msm_cam_smmu_cdm = "/soc/qcom,cam_smmu/msm_cam_smmu_cdm";
|
|
icp_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/iova-mem-map";
|
|
cam_smmu_icp_resv_region = "/soc/qcom,cam_smmu/msm_cam_smmu_icp/cam_smmu_icp_resv_region";
|
|
msm_cam_smmu_icp = "/soc/qcom,cam_smmu/msm_cam_smmu_icp";
|
|
jpeg_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/iova-mem-map";
|
|
cam_smmu_jpeg_resv_region = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg/cam_smmu_jpeg_resv_region";
|
|
msm_cam_smmu_jpeg = "/soc/qcom,cam_smmu/msm_cam_smmu_jpeg";
|
|
ife_iova_mem_map = "/soc/qcom,cam_smmu/msm_cam_smmu_ife/iova-mem-map";
|
|
cam_smmu_ife_resv_region = "/soc/qcom,cam_smmu/msm_cam_smmu_ife/cam_smmu_ife_resv_region";
|
|
msm_cam_smmu_ife = "/soc/qcom,cam_smmu/msm_cam_smmu_ife";
|
|
i2c_freq_1Mhz_cci2 = "/soc/qcom,cci2@ac7d000/qcom,i2c_fast_plus_mode";
|
|
i2c_freq_custom_cci2 = "/soc/qcom,cci2@ac7d000/qcom,i2c_custom_mode";
|
|
i2c_freq_400Khz_cci2 = "/soc/qcom,cci2@ac7d000/qcom,i2c_fast_mode";
|
|
i2c_freq_100Khz_cci2 = "/soc/qcom,cci2@ac7d000/qcom,i2c_standard_mode";
|
|
cam_cci2 = "/soc/qcom,cci2@ac7d000";
|
|
i2c_freq_1Mhz_cci1 = "/soc/qcom,cci1@ac7c000/qcom,i2c_fast_plus_mode";
|
|
i2c_freq_custom_cci1 = "/soc/qcom,cci1@ac7c000/qcom,i2c_custom_mode";
|
|
i2c_freq_400Khz_cci1 = "/soc/qcom,cci1@ac7c000/qcom,i2c_fast_mode";
|
|
i2c_freq_100Khz_cci1 = "/soc/qcom,cci1@ac7c000/qcom,i2c_standard_mode";
|
|
cam_cci1 = "/soc/qcom,cci1@ac7c000";
|
|
i2c_freq_1Mhz_cci0 = "/soc/qcom,cci0@ac7b000/qcom,i2c_fast_plus_mode";
|
|
i2c_freq_custom_cci0 = "/soc/qcom,cci0@ac7b000/qcom,i2c_custom_mode";
|
|
i2c_freq_400Khz_cci0 = "/soc/qcom,cci0@ac7b000/qcom,i2c_fast_mode";
|
|
i2c_freq_100Khz_cci0 = "/soc/qcom,cci0@ac7b000/qcom,i2c_standard_mode";
|
|
cam_cci0 = "/soc/qcom,cci0@ac7b000";
|
|
cam_csiphy5 = "/soc/qcom,csiphy5@adb3000";
|
|
cam_csiphy4 = "/soc/qcom,csiphy4@adb1000";
|
|
cam_csiphy3 = "/soc/qcom,csiphy3@adaf000";
|
|
cam_csiphy2 = "/soc/qcom,csiphy2@adad000";
|
|
cam_csiphy1 = "/soc/qcom,csiphy1@adab000";
|
|
cam_csiphy0 = "/soc/qcom,csiphy0@ada9000";
|
|
cam_sensor_ponv_rear_suspend = "/soc/pinctrl@f000000/cam_sensor_ponv_rear_suspend";
|
|
cam_sensor_ponv_rear_active = "/soc/pinctrl@f000000/cam_sensor_ponv_rear_active";
|
|
cam_sensor_i3cSelect_suspend = "/soc/pinctrl@f000000/cam_sensor_i3cSelect_suspend";
|
|
cam_sensor_i3cSelect_active = "/soc/pinctrl@f000000/cam_sensor_i3cSelect_active";
|
|
cam_sensor_suspend_rst7 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst7";
|
|
cam_sensor_active_rst7 = "/soc/pinctrl@f000000/cam_sensor_active_rst7";
|
|
cam_sensor_suspend_rst6 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst6";
|
|
cam_sensor_active_rst6 = "/soc/pinctrl@f000000/cam_sensor_active_rst6";
|
|
cam_sensor_suspend_rst5 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst5";
|
|
cam_sensor_active_rst5 = "/soc/pinctrl@f000000/cam_sensor_active_rst5";
|
|
cam_sensor_suspend_rst4 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst4";
|
|
cam_sensor_active_rst4 = "/soc/pinctrl@f000000/cam_sensor_active_rst4";
|
|
cam_sensor_suspend_rst3 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst3";
|
|
cam_sensor_active_rst3 = "/soc/pinctrl@f000000/cam_sensor_active_rst3";
|
|
cam_sensor_suspend_rst2 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst2";
|
|
cam_sensor_active_rst2 = "/soc/pinctrl@f000000/cam_sensor_active_rst2";
|
|
cam_sensor_suspend_rst1 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst1";
|
|
cam_sensor_active_rst1 = "/soc/pinctrl@f000000/cam_sensor_active_rst1";
|
|
cam_sensor_suspend_rst0 = "/soc/pinctrl@f000000/cam_sensor_suspend_rst0";
|
|
cam_sensor_active_rst0 = "/soc/pinctrl@f000000/cam_sensor_active_rst0";
|
|
cam_sensor_mclk7_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk7_suspend";
|
|
cam_sensor_mclk7_active = "/soc/pinctrl@f000000/cam_sensor_mclk7_active";
|
|
cam_sensor_mclk6_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk6_suspend";
|
|
cam_sensor_mclk6_active = "/soc/pinctrl@f000000/cam_sensor_mclk6_active";
|
|
cam_sensor_mclk5_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk5_suspend";
|
|
cam_sensor_mclk5_active = "/soc/pinctrl@f000000/cam_sensor_mclk5_active";
|
|
cam_sensor_mclk4_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk4_suspend";
|
|
cam_sensor_mclk4_active = "/soc/pinctrl@f000000/cam_sensor_mclk4_active";
|
|
cam_sensor_mclk3_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk3_suspend";
|
|
cam_sensor_mclk3_active = "/soc/pinctrl@f000000/cam_sensor_mclk3_active";
|
|
cam_sensor_mclk2_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk2_suspend";
|
|
cam_sensor_mclk2_active = "/soc/pinctrl@f000000/cam_sensor_mclk2_active";
|
|
cam_sensor_mclk1_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk1_suspend";
|
|
cam_sensor_mclk1_active = "/soc/pinctrl@f000000/cam_sensor_mclk1_active";
|
|
cam_sensor_mclk0_suspend = "/soc/pinctrl@f000000/cam_sensor_mclk0_suspend";
|
|
cam_sensor_mclk0_active = "/soc/pinctrl@f000000/cam_sensor_mclk0_active";
|
|
cci_i2c_scl5_suspend = "/soc/pinctrl@f000000/cci_i2c_scl5_suspend";
|
|
cci_i2c_scl5_active = "/soc/pinctrl@f000000/cci_i2c_scl5_active";
|
|
cci_i2c_sda5_suspend = "/soc/pinctrl@f000000/cci_i2c_sda5_suspend";
|
|
cci_i2c_sda5_active = "/soc/pinctrl@f000000/cci_i2c_sda5_active";
|
|
cci_i2c_scl4_suspend = "/soc/pinctrl@f000000/cci_i2c_scl4_suspend";
|
|
cci_i2c_scl4_active = "/soc/pinctrl@f000000/cci_i2c_scl4_active";
|
|
cci_i2c_sda4_suspend = "/soc/pinctrl@f000000/cci_i2c_sda4_suspend";
|
|
cci_i2c_sda4_active = "/soc/pinctrl@f000000/cci_i2c_sda4_active";
|
|
cci_i2c_scl3_suspend = "/soc/pinctrl@f000000/cci_i2c_scl3_suspend";
|
|
cci_i2c_sda3_active = "/soc/pinctrl@f000000/cci_i2c_sda3_active";
|
|
cci_i2c_sda3_suspend = "/soc/pinctrl@f000000/cci_i2c_sda3_suspend";
|
|
cci_i2c_scl3_active = "/soc/pinctrl@f000000/cci_i2c_scl3_active";
|
|
cci_i2c_scl2_suspend = "/soc/pinctrl@f000000/cci_i2c_scl2_suspend";
|
|
cci_i2c_scl2_active = "/soc/pinctrl@f000000/cci_i2c_scl2_active";
|
|
cci_i2c_sda2_suspend = "/soc/pinctrl@f000000/cci_i2c_sda2_suspend";
|
|
cci_i2c_sda2_active = "/soc/pinctrl@f000000/cci_i2c_sda2_active";
|
|
cci_i2c_scl1_suspend = "/soc/pinctrl@f000000/cci_i2c_scl1_suspend";
|
|
cci_i2c_scl1_active = "/soc/pinctrl@f000000/cci_i2c_scl1_active";
|
|
cci_i2c_sda1_suspend = "/soc/pinctrl@f000000/cci_i2c_sda1_suspend";
|
|
cci_i2c_sda1_active = "/soc/pinctrl@f000000/cci_i2c_sda1_active";
|
|
cci_i2c_scl0_suspend = "/soc/pinctrl@f000000/cci_i2c_scl0_suspend";
|
|
cci_i2c_scl0_active = "/soc/pinctrl@f000000/cci_i2c_scl0_active";
|
|
cci_i2c_sda0_suspend = "/soc/pinctrl@f000000/cci_i2c_sda0_suspend";
|
|
cci_i2c_sda0_active = "/soc/pinctrl@f000000/cci_i2c_sda0_active";
|
|
msm_mmrm_test = "/soc/qcom,mmrm-test";
|
|
ipa_smmu_11ad = "/soc/qcom,ipa@3e00000/ipa_smmu_11ad";
|
|
ipa_smmu_uc = "/soc/qcom,ipa@3e00000/ipa_smmu_uc";
|
|
ipa_smmu_wlan = "/soc/qcom,ipa@3e00000/ipa_smmu_wlan";
|
|
ipa_smmu_ap = "/soc/qcom,ipa@3e00000/ipa_smmu_ap";
|
|
ipa_hw = "/soc/qcom,ipa@3e00000";
|
|
audio_prm = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr/q6prm";
|
|
audio_gpr = "/soc/remoteproc-adsp@03000000/glink-edge/qcom,gpr";
|
|
lpass_audio_hw_vote = "/soc/vote_lpass_audio_hw";
|
|
lpass_core_hw_vote = "/soc/vote_lpass_core_hw";
|
|
sun_snd = "/soc/spf_core_platform/sound";
|
|
swr4 = "/soc/spf_core_platform/lpass_bt_swr@6CA0000/bt_swr_mstr";
|
|
lpass_bt_swr = "/soc/spf_core_platform/lpass_bt_swr@6CA0000";
|
|
swr3 = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000/wsa2_swr_master";
|
|
wsa2_macro = "/soc/spf_core_platform/lpass-cdc/wsa2-macro@6AA0000";
|
|
swr0 = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000/wsa_swr_master";
|
|
wsa_macro = "/soc/spf_core_platform/lpass-cdc/wsa-macro@6B00000";
|
|
swr1 = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000/rx_swr_master";
|
|
rx_macro = "/soc/spf_core_platform/lpass-cdc/rx-macro@6AC0000";
|
|
tx_macro = "/soc/spf_core_platform/lpass-cdc/tx-macro@6AE0000";
|
|
swr2 = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000/va_swr_master";
|
|
va_macro = "/soc/spf_core_platform/lpass-cdc/va-macro@7660000";
|
|
lpass_cdc = "/soc/spf_core_platform/lpass-cdc";
|
|
lpi_tlmm = "/soc/spf_core_platform/lpi_pinctrl@07760000";
|
|
msm_audio_ion_cma = "/soc/spf_core_platform/qcom,msm-audio-ion-cma";
|
|
audio_cnss_resv_region = "/soc/spf_core_platform/qcom,msm-audio-ion/audio_cnss_resv_region";
|
|
msm_audio_ion = "/soc/spf_core_platform/qcom,msm-audio-ion";
|
|
spf_core_platform = "/soc/spf_core_platform";
|
|
adsp_notify = "/soc/qcom,msm-adsp-notify";
|
|
adsp_loader = "/soc/qcom,msm-adsp-loader";
|
|
audio_pkt_core_platform = "/soc/qcom,audio-pkt-core-platform";
|
|
stub_codec = "/soc/qcom,msm-stub-codec";
|
|
funnel_gfx_in_cx_dbgc = "/soc/funnel@10963000/in-ports/port@1/endpoint";
|
|
funnel_gfx_in_gx_dbgc = "/soc/funnel@10963000/in-ports/port@0/endpoint";
|
|
gx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-gx/out-ports/port/endpoint";
|
|
coresight_gx_dgbc = "/soc/qcom,gpu-coresight-gx";
|
|
cx_dbgc_out_funnel_gfx = "/soc/qcom,gpu-coresight-cx/out-ports/port/endpoint";
|
|
coresight_cx_dgbc = "/soc/qcom,gpu-coresight-cx";
|
|
gmu = "/soc/qcom,gmu@3d37000";
|
|
gfx3d_secure = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_secure";
|
|
gfx3d_lpac = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_lpac";
|
|
gfx3d_user = "/soc/qcom,kgsl-iommu@3da0000/gfx3d_user";
|
|
kgsl_msm_iommu = "/soc/qcom,kgsl-iommu@3da0000";
|
|
secure_pixel_cb = "/soc/qcom,vidc@aa00000/secure_pixel_cb";
|
|
secure_bitstream_cb = "/soc/qcom,vidc@aa00000/secure_bitstream_cb";
|
|
secure_non_pixel_cb = "/soc/qcom,vidc@aa00000/secure_non_pixel_cb";
|
|
non_secure_cb = "/soc/qcom,vidc@aa00000/non_secure_cb";
|
|
non_secure_pixel_cb = "/soc/qcom,vidc@aa00000/non_secure_pixel_cb";
|
|
iommu_region_partition = "/soc/qcom,vidc@aa00000/iommu_region_partition";
|
|
msm_vidc = "/soc/qcom,vidc@aa00000";
|
|
msm_hw_fence = "/soc/qcom,hw-fence";
|
|
ipclite_cam = "/soc/ipclite/cam";
|
|
ipclite_cvp = "/soc/ipclite/cvp";
|
|
ipclite_cdsp = "/soc/ipclite/cdsp";
|
|
ipclite_apss = "/soc/ipclite/apss";
|
|
ipcc_compute_l0 = "/soc/qcom,ipcc_compute_l0@443000";
|
|
cvp_dsp_cb = "/soc/qcom,cvp@ab00000/cvp_dsp_cb";
|
|
cvp_secure_pixel_cb = "/soc/qcom,cvp@ab00000/cvp_secure_pixel_cb";
|
|
cvp_secure_nonpixel_cb = "/soc/qcom,cvp@ab00000/cvp_secure_nonpixel_cb";
|
|
cvp_non_secure_cb = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb";
|
|
cvp_iommu_region_partition = "/soc/qcom,cvp@ab00000/cvp_iommu_region_partition";
|
|
non_secure_cb_group = "/soc/qcom,cvp@ab00000/cvp_non_secure_cb_group";
|
|
msm_cvp = "/soc/qcom,cvp@ab00000";
|
|
msm_mmrm = "/soc/qcom,mmrm";
|
|
nfc_enable_suspend = "/soc/pinctrl@f000000/nfc/nfc_enable_suspend";
|
|
nfc_enable_active = "/soc/pinctrl@f000000/nfc/nfc_enable_active";
|
|
nfc_int_suspend = "/soc/pinctrl@f000000/nfc/nfc_int_suspend";
|
|
nfc_int_active = "/soc/pinctrl@f000000/nfc/nfc_int_active";
|
|
chosen = "/chosen";
|
|
aliases = "/aliases";
|
|
firmware = "/firmware";
|
|
qcom_scm = "/firmware/qcom_scm";
|
|
CPU0 = "/cpus/cpu@0";
|
|
L2_0 = "/cpus/cpu@0/l2-cache";
|
|
CPU1 = "/cpus/cpu@100";
|
|
CPU2 = "/cpus/cpu@200";
|
|
CPU3 = "/cpus/cpu@300";
|
|
CPU4 = "/cpus/cpu@400";
|
|
CPU5 = "/cpus/cpu@500";
|
|
CPU6 = "/cpus/cpu@10000";
|
|
L2_6 = "/cpus/cpu@10000/l2-cache";
|
|
CPU7 = "/cpus/cpu@10100";
|
|
MEDIUM_OFF_C4 = "/cpus/idle-states/medium-cluster0-c4";
|
|
LARGE_OFF_C4 = "/cpus/idle-states/large-cluster1-c4";
|
|
MEDIUM_CLUSTER_PWR_DN = "/cpus/idle-states/medium-cluster-cl5";
|
|
LARGE_CLUSTER_PWR_DN = "/cpus/idle-states/large-cluster-cl5";
|
|
APSS_OFF = "/cpus/idle-states/cluster-ss3";
|
|
reserved_memory = "/reserved-memory";
|
|
gunyah_hyp_mem = "/reserved-memory/gunyah_hyp_region@80000000";
|
|
cpucp_pdp_mem = "/reserved-memory/cpucp_pdp_region@81200000";
|
|
xbl_dtlog_mem = "/reserved-memory/xbl_dtlog_region@81a00000";
|
|
aop_image_mem = "/reserved-memory/aop_image_region@81c00000";
|
|
aop_cmd_db_mem = "/reserved-memory/aop_cmd_db_region@81c60000";
|
|
sp_mem = "/reserved-memory/sp_region";
|
|
qseecom_mem = "/reserved-memory/qseecom_region";
|
|
qseecom_ta_mem = "/reserved-memory/qseecom_ta_region";
|
|
aop_tme_uefi_merged_mem = "/reserved-memory/aop_tme_uefi_merged_region@81c80000";
|
|
smem_mem = "/reserved-memory/smem_region@81d00000";
|
|
pdp_ns_shared_mem = "/reserved-memory/pdp_ns_shared_region@81f00000";
|
|
cpucp_scandump_mem = "/reserved-memory/cpucp_scandump_region@82000000";
|
|
adsp_mhi_mem = "/reserved-memory/adsp_mhi_region@82380000";
|
|
soccp_sdi_mem = "/reserved-memory/soccp_sdi_region@823a0000";
|
|
pmic_minii_dump_mem = "/reserved-memory/pmic_minii_dump_region@823e0000";
|
|
pvm_fw_mem = "/reserved-memory/pvm_fw_region@824a0000";
|
|
global_sync_mem = "/reserved-memory/global_sync_region@82600000";
|
|
tz_stat_mem = "/reserved-memory/tz_stat_region@82700000";
|
|
qdss_apps_mem = "/reserved-memory/qdss_apps_region@82800000";
|
|
dsm_partition_1_mem = "/reserved-memory/dsm_partition_1_region@84a00000";
|
|
dsm_partition_2_mem = "/reserved-memory/dsm_partition_2_region@89300000";
|
|
mpss_mem = "/reserved-memory/mpss_region@8ba00000";
|
|
q6_mpss_dtb_mem = "/reserved-memory/q6_mpss_dtb_region@9b000000";
|
|
ipa_fw_mem = "/reserved-memory/ipa_fw_region@9b080000";
|
|
ipa_gsi_mem = "/reserved-memory/ipa_gsi_region@9b090000";
|
|
gpu_microcode_mem = "/reserved-memory/gpu_microcode_region@9b09a000";
|
|
spss_region_mem = "/reserved-memory/spss_region_region@9b0a0000";
|
|
spu_tz_shared_mem = "/reserved-memory/spu_secure_shared_memory_region@9b280000";
|
|
spu_modem_shared_mem = "/reserved-memory/spu_secure_shared_memory_region@9b2c0000";
|
|
camera_mem = "/reserved-memory/camera_region@9b300000";
|
|
camera_2_mem = "/reserved-memory/camera_2_region@9bb00000";
|
|
video_mem = "/reserved-memory/video_region@9c300000";
|
|
cvp_mem = "/reserved-memory/cvp_region@9cb00000";
|
|
cdsp_mem = "/reserved-memory/cdsp_region@9d200000";
|
|
q6_cdsp_dtb_mem = "/reserved-memory/q6_cdsp_dtb_region@9eb00000";
|
|
soccp_mem = "/reserved-memory/soccp_region@9ec00000";
|
|
q6_adsp_dtb_mem = "/reserved-memory/q6_adsp_dtb_region@9ed80000";
|
|
adspslpi_mem = "/reserved-memory/adspslpi_region@9ee00000";
|
|
xbl_ramdump_mem = "/reserved-memory/xbl_ramdump_region@b8000000";
|
|
reg_dump = "/reserved-memory/reg_dump_region@D7000000";
|
|
hwfence_shbuf = "/reserved-memory/hwfence-shmem";
|
|
tz_merged_mem = "/reserved-memory/tz_merged_region@d8000000";
|
|
trust_ui_vm_dump = "/reserved-memory/trust_ui_vm_dump@0xf37ff000";
|
|
trust_ui_vm_mem = "/reserved-memory/trust_ui_vm_region@f3800000";
|
|
vm_comm_mem = "/reserved-memory/vm_comm_mem_region";
|
|
llcc_lpi_mem = "/reserved-memory/llcc_lpi_region@ff800000";
|
|
system_cma = "/reserved-memory/linux,cma";
|
|
cdsp_eva_mem = "/reserved-memory/cdsp_eva_region";
|
|
adsp_mem_heap = "/reserved-memory/adsp_heap_region";
|
|
non_secure_display_memory = "/reserved-memory/non_secure_display_region";
|
|
kinfo_mem = "/reserved-memory/debug_kinfo_region";
|
|
va_md_mem = "/reserved-memory/va_md_mem_region";
|
|
ramoops_mem = "/reserved-memory/ramoops-region";
|
|
qmc_dma_mem = "/reserved-memory/qmc_dma_region";
|
|
cdsp_secure_heap_cma = "/reserved-memory/secure_cdsp_region";
|
|
dump_mem = "/reserved-memory/dump_mem_region";
|
|
soc = "/soc";
|
|
CPU_PD0 = "/soc/psci/cpu-pd0";
|
|
CPU_PD1 = "/soc/psci/cpu-pd1";
|
|
CPU_PD2 = "/soc/psci/cpu-pd2";
|
|
CPU_PD3 = "/soc/psci/cpu-pd3";
|
|
CPU_PD4 = "/soc/psci/cpu-pd4";
|
|
CPU_PD5 = "/soc/psci/cpu-pd5";
|
|
CPU_PD6 = "/soc/psci/cpu-pd6";
|
|
CPU_PD7 = "/soc/psci/cpu-pd7";
|
|
CLUSTER_PD0 = "/soc/psci/cluster-pd0";
|
|
CLUSTER_PD1 = "/soc/psci/cluster-pd1";
|
|
CLUSTER_PD2 = "/soc/psci/cluster-pd2";
|
|
ipcc_mproc = "/soc/qcom,ipcc@406000";
|
|
tcsr_mutex_block = "/soc/syscon@1f40000";
|
|
tcsr = "/soc/syscon@1fc0000";
|
|
tcsr_mutex = "/soc/hwlock";
|
|
pdc = "/soc/interrupt-controller@b220000";
|
|
pcie_pdc = "/soc/pdc@b360000";
|
|
aoss_qmp = "/soc/power-controller@c300000";
|
|
qmp_tme = "/soc/qcom,qmp-tme";
|
|
adsp_smp2p_out = "/soc/qcom,smp2p-adsp/master-kernel";
|
|
adsp_smp2p_in = "/soc/qcom,smp2p-adsp/slave-kernel";
|
|
sleepstate_smp2p_out = "/soc/qcom,smp2p-adsp/sleepstate-out";
|
|
sleepstate_smp2p_in = "/soc/qcom,smp2p-adsp/qcom,sleepstate-in";
|
|
smp2p_rdbg2_out = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-out";
|
|
smp2p_rdbg2_in = "/soc/qcom,smp2p-adsp/qcom,smp2p-rdbg2-in";
|
|
cdsp_smp2p_out = "/soc/qcom,smp2p-cdsp/master-kernel";
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cdsp_smp2p_in = "/soc/qcom,smp2p-cdsp/slave-kernel";
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smp2p_rdbg5_out = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-out";
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smp2p_rdbg5_in = "/soc/qcom,smp2p-cdsp/qcom,smp2p-rdbg5-in";
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modem_smp2p_out = "/soc/qcom,smp2p-modem/master-kernel";
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modem_smp2p_in = "/soc/qcom,smp2p-modem/slave-kernel";
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smp2p_ipa_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-out";
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smp2p_ipa_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-ipa-1-in";
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smp2p_smem_mailbox_1_out = "/soc/qcom,smp2p-modem/qcom,smp2p-smem-mailbox-1-out";
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smp2p_smem_mailbox_1_in = "/soc/qcom,smp2p-modem/qcom,smp2p-smem-mailbox-1-in";
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soccp_smp2p_out = "/soc/qcom,smp2p-soccp/master-kernel";
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soccp_smp2p_in = "/soc/qcom,smp2p-soccp/slave-kernel";
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qcom_tzlog = "/soc/tz-log@14680720";
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tlmm = "/soc/pinctrl@f000000";
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qupv3_se7_2uart_pins = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins";
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qupv3_se7_2uart_tx_active = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_tx_active";
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qupv3_se7_2uart_rx_active = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_rx_active";
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qupv3_se7_2uart_sleep = "/soc/pinctrl@f000000/qupv3_se7_2uart_pins/qupv3_se7_2uart_sleep";
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i2s0_sck_sleep = "/soc/pinctrl@f000000/i2s0_sck/i2s0_sck_sleep";
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i2s0_sck_active = "/soc/pinctrl@f000000/i2s0_sck/i2s0_sck_active";
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i2s0_ws_sleep = "/soc/pinctrl@f000000/i2s0_ws/i2s0_ws_sleep";
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i2s0_ws_active = "/soc/pinctrl@f000000/i2s0_ws/i2s0_ws_active";
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trigout_a = "/soc/pinctrl@f000000/trigout_a";
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i2s0_sd0_sleep = "/soc/pinctrl@f000000/i2s0_sd0/i2s0_sd0_sleep";
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i2s0_sd0_active = "/soc/pinctrl@f000000/i2s0_sd0/i2s0_sd0_active";
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i2s0_sd1_sleep = "/soc/pinctrl@f000000/i2s0_sd1/i2s0_sd1_sleep";
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i2s0_sd1_active = "/soc/pinctrl@f000000/i2s0_sd1/i2s0_sd1_active";
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i2s1_sck_sleep = "/soc/pinctrl@f000000/i2s1_sck/i2s1_sck_sleep";
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i2s1_sck_active = "/soc/pinctrl@f000000/i2s1_sck/i2s1_sck_active";
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i2s1_ws_sleep = "/soc/pinctrl@f000000/i2s1_ws/i2s1_ws_sleep";
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i2s1_ws_active = "/soc/pinctrl@f000000/i2s1_ws/i2s1_ws_active";
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i2s1_sd0_sleep = "/soc/pinctrl@f000000/i2s1_sd0/i2s1_sd0_sleep";
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i2s1_sd0_active = "/soc/pinctrl@f000000/i2s1_sd0/i2s1_sd0_active";
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i2s1_sd1_sleep = "/soc/pinctrl@f000000/i2s1_sd1/i2s1_sd1_sleep";
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i2s1_sd1_active = "/soc/pinctrl@f000000/i2s1_sd1/i2s1_sd1_active";
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tdm0_clk_sleep = "/soc/pinctrl@f000000/tdm0_clk/tdm0_clk_sleep";
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tdm0_clk_active = "/soc/pinctrl@f000000/tdm0_clk/tdm0_clk_active";
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tdm0_ws_sleep = "/soc/pinctrl@f000000/tdm0_ws/tdm0_ws_sleep";
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tdm0_ws_active = "/soc/pinctrl@f000000/tdm0_ws/tdm0_ws_active";
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tdm0_sd0_sleep = "/soc/pinctrl@f000000/tdm0_sd0/tdm0_sd0_sleep";
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tdm0_sd0_active = "/soc/pinctrl@f000000/tdm0_sd0/tdm0_sd0_active";
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tdm0_sd1_sleep = "/soc/pinctrl@f000000/tdm0_sd1/tdm0_sd1_sleep";
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tdm0_sd1_active = "/soc/pinctrl@f000000/tdm0_sd1/tdm0_sd1_active";
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tdm1_clk_sleep = "/soc/pinctrl@f000000/tdm1_clk/tdm1_clk_sleep";
|
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tdm1_clk_active = "/soc/pinctrl@f000000/tdm1_clk/tdm1_clk_active";
|
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tdm1_ws_sleep = "/soc/pinctrl@f000000/tdm1_ws/tdm1_ws_sleep";
|
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tdm1_ws_active = "/soc/pinctrl@f000000/tdm1_ws/tdm1_ws_active";
|
|
tdm1_sd0_sleep = "/soc/pinctrl@f000000/tdm1_sd0/tdm1_sd0_sleep";
|
|
tdm1_sd0_active = "/soc/pinctrl@f000000/tdm1_sd0/tdm1_sd0_active";
|
|
tdm1_sd1_sleep = "/soc/pinctrl@f000000/tdm1_sd1/tdm1_sd1_sleep";
|
|
tdm1_sd1_active = "/soc/pinctrl@f000000/tdm1_sd1/tdm1_sd1_active";
|
|
pcie0_perst_default = "/soc/pinctrl@f000000/pcie0/pcie0_perst_default";
|
|
pcie0_clkreq_default = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_default";
|
|
pcie0_wake_default = "/soc/pinctrl@f000000/pcie0/pcie0_wake_default";
|
|
pcie0_clkreq_sleep = "/soc/pinctrl@f000000/pcie0/pcie0_clkreq_sleep";
|
|
sdc2_on = "/soc/pinctrl@f000000/sdc2_on";
|
|
sdc2_off = "/soc/pinctrl@f000000/sdc2_off";
|
|
wcd939x_reset_active = "/soc/pinctrl@f000000/wcd939x_reset_active";
|
|
wcd939x_reset_sleep = "/soc/pinctrl@f000000/wcd939x_reset_sleep";
|
|
spkr_02_sd_n_sleep = "/soc/pinctrl@f000000/spkr_02_sd_n/spkr_02_sd_n_sleep";
|
|
spkr_02_sd_n_active = "/soc/pinctrl@f000000/spkr_02_sd_n/spkr_02_sd_n_active";
|
|
spkr_13_sd_n_sleep = "/soc/pinctrl@f000000/spkr_13_sd_n/spkr_13_sd_n_sleep";
|
|
spkr_13_sd_n_active = "/soc/pinctrl@f000000/spkr_13_sd_n/spkr_13_sd_n_active";
|
|
qupv3_se14_4uart_pins = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins";
|
|
qupv3_se14_default_cts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_cts";
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|
qupv3_se14_default_rts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_rts";
|
|
qupv3_se14_default_tx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_tx";
|
|
qupv3_se14_default_rx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_default_rx";
|
|
qupv3_se14_cts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_cts";
|
|
qupv3_se14_rts = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_rts";
|
|
qupv3_se14_tx = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_tx";
|
|
qupv3_se14_rx_active = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_rx_active";
|
|
qupv3_se14_rx_wake = "/soc/pinctrl@f000000/qupv3_se14_4uart_pins/qupv3_se14_rx_wake";
|
|
qupv3_se0_i2c_pins = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins";
|
|
qupv3_se0_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sda_active";
|
|
qupv3_se0_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_scl_active";
|
|
qupv3_se0_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se0_i2c_pins/qupv3_se0_i2c_sleep";
|
|
qupv3_se0_i3c_pins = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins";
|
|
qupv3_se0_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_sda_active";
|
|
qupv3_se0_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_scl_active";
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|
qupv3_se0_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_sda_sleep";
|
|
qupv3_se0_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_scl_sleep";
|
|
qupv3_se0_i3c_disable = "/soc/pinctrl@f000000/qupv3_se0_i3c_pins/qupv3_se0_i3c_disable";
|
|
qupv3_se0_spi_pins = "/soc/pinctrl@f000000/qupv3_se0_spi_pins";
|
|
qupv3_se0_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_miso_active";
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|
qupv3_se0_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_mosi_active";
|
|
qupv3_se0_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_clk_active";
|
|
qupv3_se0_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_cs_active";
|
|
qupv3_se0_spi_sleep = "/soc/pinctrl@f000000/qupv3_se0_spi_pins/qupv3_se0_spi_sleep";
|
|
qupv3_se1_i2c_pins = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins";
|
|
qupv3_se1_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sda_active";
|
|
qupv3_se1_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_scl_active";
|
|
qupv3_se1_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se1_i2c_pins/qupv3_se1_i2c_sleep";
|
|
qupv3_se1_spi_pins = "/soc/pinctrl@f000000/qupv3_se1_spi_pins";
|
|
qupv3_se1_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_miso_active";
|
|
qupv3_se1_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_mosi_active";
|
|
qupv3_se1_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_clk_active";
|
|
qupv3_se1_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_cs_active";
|
|
qupv3_se1_spi_sleep = "/soc/pinctrl@f000000/qupv3_se1_spi_pins/qupv3_se1_spi_sleep";
|
|
qupv3_se1_i3c_pins = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins";
|
|
qupv3_se1_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins/qupv3_se1_i3c_sda_active";
|
|
qupv3_se1_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins/qupv3_se1_i3c_scl_active";
|
|
qupv3_se1_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins/qupv3_se1_i3c_sda_sleep";
|
|
qupv3_se1_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins/qupv3_se1_i3c_scl_sleep";
|
|
qupv3_se1_i3c_disable = "/soc/pinctrl@f000000/qupv3_se1_i3c_pins/qupv3_se1_i3c_disable";
|
|
qupv3_se2_i2c_pins = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins";
|
|
qupv3_se2_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sda_active";
|
|
qupv3_se2_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_scl_active";
|
|
qupv3_se2_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se2_i2c_pins/qupv3_se2_i2c_sleep";
|
|
qupv3_se2_spi_pins = "/soc/pinctrl@f000000/qupv3_se2_spi_pins";
|
|
qupv3_se2_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_miso_active";
|
|
qupv3_se2_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_mosi_active";
|
|
qupv3_se2_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_clk_active";
|
|
qupv3_se2_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_cs_active";
|
|
qupv3_se2_spi_sleep = "/soc/pinctrl@f000000/qupv3_se2_spi_pins/qupv3_se2_spi_sleep";
|
|
qupv3_se3_i2c_pins = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins";
|
|
qupv3_se3_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sda_active";
|
|
qupv3_se3_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_scl_active";
|
|
qupv3_se3_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se3_i2c_pins/qupv3_se3_i2c_sleep";
|
|
qupv3_se3_spi_pins = "/soc/pinctrl@f000000/qupv3_se3_spi_pins";
|
|
qupv3_se3_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_miso_active";
|
|
qupv3_se3_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_mosi_active";
|
|
qupv3_se3_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_clk_active";
|
|
qupv3_se3_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_cs_active";
|
|
qupv3_se3_spi_sleep = "/soc/pinctrl@f000000/qupv3_se3_spi_pins/qupv3_se3_spi_sleep";
|
|
qupv3_se4_i2c_pins = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins";
|
|
qupv3_se4_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sda_active";
|
|
qupv3_se4_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_scl_active";
|
|
qupv3_se4_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se4_i2c_pins/qupv3_se4_i2c_sleep";
|
|
qupv3_se4_i3c_pins = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins";
|
|
qupv3_se4_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_sda_active";
|
|
qupv3_se4_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_scl_active";
|
|
qupv3_se4_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_sda_sleep";
|
|
qupv3_se4_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_scl_sleep";
|
|
qupv3_se4_i3c_disable = "/soc/pinctrl@f000000/qupv3_se4_i3c_pins/qupv3_se4_i3c_disable";
|
|
qupv3_se4_spi_pins = "/soc/pinctrl@f000000/qupv3_se4_spi_pins";
|
|
qupv3_se4_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_miso_active";
|
|
qupv3_se4_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_mosi_active";
|
|
qupv3_se4_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_clk_active";
|
|
qupv3_se4_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_cs_active";
|
|
qupv3_se4_spi_sleep = "/soc/pinctrl@f000000/qupv3_se4_spi_pins/qupv3_se4_spi_sleep";
|
|
qupv3_se5_i2c_pins = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins";
|
|
qupv3_se5_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sda_active";
|
|
qupv3_se5_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_scl_active";
|
|
qupv3_se5_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se5_i2c_pins/qupv3_se5_i2c_sleep";
|
|
qupv3_se5_spi_pins = "/soc/pinctrl@f000000/qupv3_se5_spi_pins";
|
|
qupv3_se5_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_miso_active";
|
|
qupv3_se5_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_mosi_active";
|
|
qupv3_se5_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_clk_active";
|
|
qupv3_se5_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_cs_active";
|
|
qupv3_se5_spi_sleep = "/soc/pinctrl@f000000/qupv3_se5_spi_pins/qupv3_se5_spi_sleep";
|
|
qupv3_se6_i2c_pins = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins";
|
|
qupv3_se6_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sda_active";
|
|
qupv3_se6_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_scl_active";
|
|
qupv3_se6_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se6_i2c_pins/qupv3_se6_i2c_sleep";
|
|
qupv3_se6_spi_pins = "/soc/pinctrl@f000000/qupv3_se6_spi_pins";
|
|
qupv3_se6_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_miso_active";
|
|
qupv3_se6_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_mosi_active";
|
|
qupv3_se6_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_clk_active";
|
|
qupv3_se6_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_cs_active";
|
|
qupv3_se6_spi_sleep = "/soc/pinctrl@f000000/qupv3_se6_spi_pins/qupv3_se6_spi_sleep";
|
|
qupv3_se8_i2c_pins = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins";
|
|
qupv3_se8_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sda_active";
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qupv3_se8_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_scl_active";
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qupv3_se8_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se8_i2c_pins/qupv3_se8_i2c_sleep";
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qupv3_se8_spi_pins = "/soc/pinctrl@f000000/qupv3_se8_spi_pins";
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qupv3_se8_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_miso_active";
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qupv3_se8_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_mosi_active";
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qupv3_se8_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_clk_active";
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qupv3_se8_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_cs_active";
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qupv3_se8_spi_sleep = "/soc/pinctrl@f000000/qupv3_se8_spi_pins/qupv3_se8_spi_sleep";
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qupv3_se8_i3c_pins = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins";
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qupv3_se8_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_sda_active";
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qupv3_se8_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_scl_active";
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qupv3_se8_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_sda_sleep";
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qupv3_se8_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_scl_sleep";
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qupv3_se8_i3c_disable = "/soc/pinctrl@f000000/qupv3_se8_i3c_pins/qupv3_se8_i3c_disable";
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qupv3_se9_i2c_pins = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins";
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qupv3_se9_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sda_active";
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qupv3_se9_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_scl_active";
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qupv3_se9_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se9_i2c_pins/qupv3_se9_i2c_sleep";
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qupv3_se9_spi_pins = "/soc/pinctrl@f000000/qupv3_se9_spi_pins";
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qupv3_se9_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_miso_active";
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qupv3_se9_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_mosi_active";
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qupv3_se9_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_clk_active";
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qupv3_se9_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_cs_active";
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qupv3_se9_spi_sleep = "/soc/pinctrl@f000000/qupv3_se9_spi_pins/qupv3_se9_spi_sleep";
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qupv3_se9_i3c_pins = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins";
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qupv3_se9_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins/qupv3_se9_i3c_sda_active";
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qupv3_se9_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins/qupv3_se9_i3c_scl_active";
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qupv3_se9_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins/qupv3_se9_i3c_sda_sleep";
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qupv3_se9_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins/qupv3_se9_i3c_scl_sleep";
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qupv3_se9_i3c_disable = "/soc/pinctrl@f000000/qupv3_se9_i3c_pins/qupv3_se9_i3c_disable";
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qupv3_se10_i2c_pins = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins";
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qupv3_se10_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sda_active";
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qupv3_se10_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_scl_active";
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qupv3_se10_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se10_i2c_pins/qupv3_se10_i2c_sleep";
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qupv3_se10_spi_pins = "/soc/pinctrl@f000000/qupv3_se10_spi_pins";
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qupv3_se10_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_miso_active";
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qupv3_se10_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_mosi_active";
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qupv3_se10_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_clk_active";
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qupv3_se10_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_cs_active";
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qupv3_se10_spi_sleep = "/soc/pinctrl@f000000/qupv3_se10_spi_pins/qupv3_se10_spi_sleep";
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qupv3_se10_i3c_pins = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins";
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qupv3_se10_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_sda_active";
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qupv3_se10_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_scl_active";
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qupv3_se10_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_sda_sleep";
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qupv3_se10_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_scl_sleep";
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qupv3_se10_i3c_disable = "/soc/pinctrl@f000000/qupv3_se10_i3c_pins/qupv3_se10_i3c_disable";
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qupv3_se11_i2c_pins = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins";
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qupv3_se11_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sda_active";
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qupv3_se11_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_scl_active";
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qupv3_se11_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se11_i2c_pins/qupv3_se11_i2c_sleep";
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qupv3_se11_spi_pins = "/soc/pinctrl@f000000/qupv3_se11_spi_pins";
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qupv3_se11_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_miso_active";
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qupv3_se11_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_mosi_active";
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qupv3_se11_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_clk_active";
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qupv3_se11_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_cs_active";
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qupv3_se11_spi_sleep = "/soc/pinctrl@f000000/qupv3_se11_spi_pins/qupv3_se11_spi_sleep";
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qupv3_se11_i3c_pins = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins";
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qupv3_se11_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_sda_active";
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qupv3_se11_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_scl_active";
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qupv3_se11_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_sda_sleep";
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qupv3_se11_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_scl_sleep";
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qupv3_se11_i3c_disable = "/soc/pinctrl@f000000/qupv3_se11_i3c_pins/qupv3_se11_i3c_disable";
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qupv3_se12_i2c_pins = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins";
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qupv3_se12_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_sda_active";
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qupv3_se12_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_scl_active";
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qupv3_se12_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se12_i2c_pins/qupv3_se12_i2c_sleep";
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qupv3_se12_spi_pins = "/soc/pinctrl@f000000/qupv3_se12_spi_pins";
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qupv3_se12_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_miso_active";
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qupv3_se12_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_mosi_active";
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qupv3_se12_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_clk_active";
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qupv3_se12_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_cs_active";
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qupv3_se12_spi_sleep = "/soc/pinctrl@f000000/qupv3_se12_spi_pins/qupv3_se12_spi_sleep";
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qupv3_se13_i2c_pins = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins";
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qupv3_se13_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_sda_active";
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qupv3_se13_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_scl_active";
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qupv3_se13_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se13_i2c_pins/qupv3_se13_i2c_sleep";
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qupv3_se13_spi_pins = "/soc/pinctrl@f000000/qupv3_se13_spi_pins";
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qupv3_se13_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_miso_active";
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qupv3_se13_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_mosi_active";
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qupv3_se13_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_clk_active";
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qupv3_se13_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_cs_active";
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qupv3_se13_spi_sleep = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_sleep";
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qupv3_se13_spi_cs_sleep = "/soc/pinctrl@f000000/qupv3_se13_spi_pins/qupv3_se13_spi_cs_sleep";
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qupv3_se13_q2spi_pins = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins";
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qupv3_se13_q2spi_default = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_default";
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qupv3_se13_q2spi_miso_default = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_default";
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qupv3_se13_q2spi_miso_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_active";
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qupv3_se13_q2spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_mosi_active";
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qupv3_se13_q2spi_clk_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_clk_active";
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qupv3_se13_q2spi_doorbell_active = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_doorbell_active";
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qupv3_se13_q2spi_doorbell_sleep = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_doorbell_sleep";
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qupv3_se13_q2spi_miso_sleep = "/soc/pinctrl@f000000/qupv3_se13_q2spi_pins/qupv3_se13_q2spi_miso_sleep";
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qupv3_se15_i2c_pins = "/soc/pinctrl@f000000/qupv3_se15_i2c_pins";
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qupv3_se15_i2c_sda_active = "/soc/pinctrl@f000000/qupv3_se15_i2c_pins/qupv3_se15_i2c_sda_active";
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qupv3_se15_i2c_scl_active = "/soc/pinctrl@f000000/qupv3_se15_i2c_pins/qupv3_se15_i2c_scl_active";
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qupv3_se15_i2c_sleep = "/soc/pinctrl@f000000/qupv3_se15_i2c_pins/qupv3_se15_i2c_sleep";
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qupv3_se15_spi_pins = "/soc/pinctrl@f000000/qupv3_se15_spi_pins";
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qupv3_se15_spi_miso_active = "/soc/pinctrl@f000000/qupv3_se15_spi_pins/qupv3_se15_spi_miso_active";
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qupv3_se15_spi_mosi_active = "/soc/pinctrl@f000000/qupv3_se15_spi_pins/qupv3_se15_spi_mosi_active";
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qupv3_se15_spi_clk_active = "/soc/pinctrl@f000000/qupv3_se15_spi_pins/qupv3_se15_spi_clk_active";
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qupv3_se15_spi_cs_active = "/soc/pinctrl@f000000/qupv3_se15_spi_pins/qupv3_se15_spi_cs_active";
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qupv3_se15_spi_sleep = "/soc/pinctrl@f000000/qupv3_se15_spi_pins/qupv3_se15_spi_sleep";
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qupv3_se15_i3c_pins = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins";
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qupv3_se15_i3c_sda_active = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins/qupv3_se15_i3c_sda_active";
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qupv3_se15_i3c_scl_active = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins/qupv3_se15_i3c_scl_active";
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qupv3_se15_i3c_sda_sleep = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins/qupv3_se15_i3c_sda_sleep";
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qupv3_se15_i3c_scl_sleep = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins/qupv3_se15_i3c_scl_sleep";
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qupv3_se15_i3c_disable = "/soc/pinctrl@f000000/qupv3_se15_i3c_pins/qupv3_se15_i3c_disable";
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|
qupv3_hub_i2c0_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins";
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qupv3_hub_i2c0_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_sda_active";
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qupv3_hub_i2c0_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_scl_active";
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qupv3_hub_i2c0_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c0_pins/qupv3_hub_i2c0_sleep";
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qupv3_hub_i2c1_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins";
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|
qupv3_hub_i2c1_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_sda_active";
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qupv3_hub_i2c1_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_scl_active";
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qupv3_hub_i2c1_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c1_pins/qupv3_hub_i2c1_sleep";
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|
qupv3_hub_i2c2_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins";
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|
qupv3_hub_i2c2_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_sda_active";
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|
qupv3_hub_i2c2_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_scl_active";
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|
qupv3_hub_i2c2_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c2_pins/qupv3_hub_i2c2_sleep";
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|
qupv3_hub_i2c3_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins";
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|
qupv3_hub_i2c3_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_sda_active";
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|
qupv3_hub_i2c3_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_scl_active";
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|
qupv3_hub_i2c3_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c3_pins/qupv3_hub_i2c3_sleep";
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|
qupv3_hub_i2c4_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins";
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|
qupv3_hub_i2c4_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_sda_active";
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|
qupv3_hub_i2c4_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_scl_active";
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|
qupv3_hub_i2c4_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c4_pins/qupv3_hub_i2c4_sleep";
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|
qupv3_hub_i2c5_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins";
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|
qupv3_hub_i2c5_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_sda_active";
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|
qupv3_hub_i2c5_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_scl_active";
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|
qupv3_hub_i2c5_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c5_pins/qupv3_hub_i2c5_sleep";
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|
qupv3_hub_i2c6_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins";
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|
qupv3_hub_i2c6_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_sda_active";
|
|
qupv3_hub_i2c6_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_scl_active";
|
|
qupv3_hub_i2c6_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c6_pins/qupv3_hub_i2c6_sleep";
|
|
qupv3_hub_i2c7_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins";
|
|
qupv3_hub_i2c7_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_sda_active";
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|
qupv3_hub_i2c7_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_scl_active";
|
|
qupv3_hub_i2c7_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c7_pins/qupv3_hub_i2c7_sleep";
|
|
qupv3_hub_i2c8_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins";
|
|
qupv3_hub_i2c8_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_sda_active";
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|
qupv3_hub_i2c8_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_scl_active";
|
|
qupv3_hub_i2c8_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c8_pins/qupv3_hub_i2c8_sleep";
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|
qupv3_hub_i2c9_pins = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins";
|
|
qupv3_hub_i2c9_sda_active = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_sda_active";
|
|
qupv3_hub_i2c9_scl_active = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_scl_active";
|
|
qupv3_hub_i2c9_sleep = "/soc/pinctrl@f000000/qupv3_hub_i2c9_pins/qupv3_hub_i2c9_sleep";
|
|
usb_phy_ps = "/soc/pinctrl@f000000/usb_phy_ps";
|
|
usb3phy_portselect_default = "/soc/pinctrl@f000000/usb_phy_ps/usb3phy_portselect_default";
|
|
usb3phy_portselect_gpio = "/soc/pinctrl@f000000/usb_phy_ps/usb3phy_portselect_gpio";
|
|
ts_active = "/soc/pinctrl@f000000/pmx_ts_active/ts_active";
|
|
ts_reset_suspend = "/soc/pinctrl@f000000/pmx_ts_reset_suspend/ts_reset_suspend";
|
|
ts_int_suspend = "/soc/pinctrl@f000000/pmx_ts_int_suspend/ts_int_suspend";
|
|
ts_release = "/soc/pinctrl@f000000/pmx_ts_release/ts_release";
|
|
slimbam = "/soc/bamdma@6C04000";
|
|
slim_msm = "/soc/slim@6C40000";
|
|
intc = "/soc/interrupt-controller@16000000";
|
|
gic_its = "/soc/interrupt-controller@16000000/msi-controller@0x16040000";
|
|
memtimer = "/soc/timer@16800000";
|
|
eud = "/soc/qcom,msm-eud@88e0000";
|
|
arch_timer = "/soc/timer";
|
|
pcie_crm_hw_0_bcm_voter = "/soc/bcm_voter@0";
|
|
disp_crm_hw_0_bcm_voter = "/soc/bcm_voter@1";
|
|
disp_crm_hw_1_bcm_voter = "/soc/bcm_voter@2";
|
|
disp_crm_hw_2_bcm_voter = "/soc/bcm_voter@3";
|
|
disp_crm_hw_3_bcm_voter = "/soc/bcm_voter@4";
|
|
disp_crm_hw_4_bcm_voter = "/soc/bcm_voter@5";
|
|
disp_crm_hw_5_bcm_voter = "/soc/bcm_voter@6";
|
|
disp_crm_sw_0_bcm_voter = "/soc/bcm_voter@7";
|
|
clk_virt = "/soc/interconnect@0";
|
|
mc_virt = "/soc/interconnect@1";
|
|
config_noc = "/soc/interconnect@1600000";
|
|
cnoc_main = "/soc/interconnect@1500000";
|
|
system_noc = "/soc/interconnect@1680000";
|
|
pcie_noc = "/soc/interconnect@16c0000";
|
|
aggre1_noc = "/soc/interconnect@16e0000";
|
|
aggre2_noc = "/soc/interconnect@1700000";
|
|
mmss_noc = "/soc/interconnect@1780000";
|
|
gem_noc = "/soc/interconnect@24100000";
|
|
nsp_noc = "/soc/interconnect@320c0000";
|
|
lpass_ag_noc = "/soc/interconnect@7e40000";
|
|
lpass_lpiaon_noc = "/soc/interconnect@7400000";
|
|
lpass_lpicx_noc = "/soc/interconnect@7420000";
|
|
apps_rsc = "/soc/rsc@16500000";
|
|
apps_rsc_drv2 = "/soc/rsc@16500000/drv@2";
|
|
apps_bcm_voter = "/soc/rsc@16500000/drv@2/bcm_voter";
|
|
rpmhcc = "/soc/rsc@16500000/drv@2/clock-controller";
|
|
dcvs_fp = "/soc/rsc@16500000/drv@2/qcom,dcvs-fp";
|
|
VDD_GFX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v8d-s5-level";
|
|
S5D_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v8d-s5-level";
|
|
pm_v8d_s5_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-gfxlvl/regulator-pm-v8d-s5-level";
|
|
VDD_GFX_MXC_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gmxclvl/regulator-pm-v8d-s2-level";
|
|
S2D_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gmxclvl/regulator-pm-v8d-s2-level";
|
|
pm_v8d_s2_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-gmxclvl/regulator-pm-v8d-s2-level";
|
|
VDD_GFX_MXC_GFX_VOTER_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gmxclvl/regulator-pm-v8d-s2-gfx-voter-level";
|
|
VDD_GFX_GFX_MXC_VOTER_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-gmxclvl/regulator-pm-v8d-s2-gfx-voter-level";
|
|
VDD_MXA_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
VDD_MX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
S6F_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
pm_v6f_s6_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
S8F_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
pm_v8f_s8_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level";
|
|
VDD_MXA_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
VDD_MX_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
S6F_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
pm_v6f_s6_level_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
S8F_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
pm_v8f_s8_level_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxlvl/regulator-vdd-mxa-level-ao";
|
|
VDD_EBI_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v8g-s2-level";
|
|
S2G_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v8g-s2-level";
|
|
pm_v8g_s2_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-ebilvl/regulator-pm-v8g-s2-level";
|
|
VDD_MODEM_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-msslvl/regulator-pm-v8g-s5-level";
|
|
S5G_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-msslvl/regulator-pm-v8g-s5-level";
|
|
pm_v8g_s5_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-msslvl/regulator-pm-v8g-s5-level";
|
|
VDD_NSP1_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8g-s7-level";
|
|
S7G_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8g-s7-level";
|
|
pm_v8g_s7_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsplvl/regulator-pm-v8g-s7-level";
|
|
VDD_NSP2_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v8i-s1-level";
|
|
S1I_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v8i-s1-level";
|
|
pm_v8i_s1_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-nsp2lvl/regulator-pm-v8i-s1-level";
|
|
VDD_CX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level";
|
|
S1J_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level";
|
|
pm_v6j_s1_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level";
|
|
VDD_CX_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level-ao";
|
|
S1J_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level-ao";
|
|
pm_v6j_s1_level_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-level-ao";
|
|
VDD_CX_MMCX_SUPPLY_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-cxlvl/regulator-pm-v6j-s1-mmcx-sup-level";
|
|
VDD_MMCX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level";
|
|
VDD_MM_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level";
|
|
S3I_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level";
|
|
pm_v8i_s3_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level";
|
|
VDD_MMCX_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level-ao";
|
|
VDD_MM_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level-ao";
|
|
S3I_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level-ao";
|
|
pm_v8i_s3_level_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-mmcxlvl/regulator-pm-v8i-s3-level-ao";
|
|
VDD_LPI_CX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v8i-s5-level";
|
|
S5I_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v8i-s5-level";
|
|
pm_v8i_s5_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-lcxlvl/regulator-pm-v8i-s5-level";
|
|
VDD_MXC_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level";
|
|
S6I_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level";
|
|
pm_v8i_s6_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level";
|
|
VDD_MXC_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level-ao";
|
|
S6I_LEVEL_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level-ao";
|
|
pm_v8i_s6_level_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-level-ao";
|
|
VDD_MXC_MMCX_VOTER_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-mmcx-voter-level";
|
|
VDD_MXC_MM_VOTER_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-mmcx-voter-level";
|
|
VDD_MM_MXC_VOTER_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-mxclvl/regulator-pm-v8i-s6-mmcx-voter-level";
|
|
VDD_LPI_MX_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6j-l3-level";
|
|
L3J_LEVEL = "/soc/rsc@16500000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6j-l3-level";
|
|
pm_v6j_l3_level = "/soc/rsc@16500000/drv@2/rpmh-regulator-lmxlvl/regulator-pm-v6j-l3-level";
|
|
L1B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob1/regulator-pm-humu-l1";
|
|
pm_humu_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob1/regulator-pm-humu-l1";
|
|
L2B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob2/regulator-pm-humu-l2";
|
|
pm_humu_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob2/regulator-pm-humu-l2";
|
|
L4B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob4/regulator-pm-humu-l4";
|
|
pm_humu_l4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob4/regulator-pm-humu-l4";
|
|
L5B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob5/regulator-pm-humu-l5";
|
|
pm_humu_l5 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob5/regulator-pm-humu-l5";
|
|
L6B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob6/regulator-pm-humu-l6";
|
|
pm_humu_l6 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob6/regulator-pm-humu-l6";
|
|
L7B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob7/regulator-pm-humu-l7";
|
|
pm_humu_l7 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob7/regulator-pm-humu-l7";
|
|
L8B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob8/regulator-pm-humu-l8";
|
|
pm_humu_l8 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob8/regulator-pm-humu-l8";
|
|
L9B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob9/regulator-pm-humu-l9";
|
|
pm_humu_l9 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob9/regulator-pm-humu-l9";
|
|
L10B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob10/regulator-pm-humu-l10";
|
|
pm_humu_l10 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob10/regulator-pm-humu-l10";
|
|
L11B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob11/regulator-pm-humu-l11";
|
|
pm_humu_l11 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob11/regulator-pm-humu-l11";
|
|
L12B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob12/regulator-pm-humu-l12";
|
|
pm_humu_l12 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob12/regulator-pm-humu-l12";
|
|
L13B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob13/regulator-pm-humu-l13";
|
|
pm_humu_l13 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob13/regulator-pm-humu-l13";
|
|
L14B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob14/regulator-pm-humu-l14";
|
|
pm_humu_l14 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob14/regulator-pm-humu-l14";
|
|
L15B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob15/regulator-pm-humu-l15";
|
|
pm_humu_l15 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob15/regulator-pm-humu-l15";
|
|
L16B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob16/regulator-pm-humu-l16";
|
|
pm_humu_l16 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob16/regulator-pm-humu-l16";
|
|
L17B = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob17/regulator-pm-humu-l17";
|
|
pm_humu_l17 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldob17/regulator-pm-humu-l17";
|
|
BOB1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-bobb1/regulator-pm-humu-bob1";
|
|
pm_humu_bob1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-bobb1/regulator-pm-humu-bob1";
|
|
BOB2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-bobb2/regulator-pm-humu-bob2";
|
|
pm_humu_bob2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-bobb2/regulator-pm-humu-bob2";
|
|
S1D = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd1/regulator-pm-v8d-s1";
|
|
pm_v8d_s1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd1/regulator-pm-v8d-s1";
|
|
S3D = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd3/regulator-pm-v8d-s3";
|
|
pm_v8d_s3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd3/regulator-pm-v8d-s3";
|
|
S4D = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd4/regulator-pm-v8d-s4";
|
|
pm_v8d_s4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpd4/regulator-pm-v8d-s4";
|
|
L1D = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod1/regulator-pm-v8d-l1";
|
|
pm_v8d_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod1/regulator-pm-v8d-l1";
|
|
L2D = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod2/regulator-pm-v8d-l2";
|
|
pm_v8d_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod2/regulator-pm-v8d-l2";
|
|
L3D = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod3/regulator-pm-v8d-l3";
|
|
pm_v8d_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldod3/regulator-pm-v8d-l3";
|
|
VRM_S5F = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpf5";
|
|
S5F = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpf5/regulator-pm-v8f-s5";
|
|
pm_v8f_s5 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpf5/regulator-pm-v8f-s5";
|
|
L1F = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1";
|
|
pm_v6f_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1";
|
|
pm_v8f_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1";
|
|
L1F_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-ao";
|
|
pm_v6f_l1_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-ao";
|
|
pm_v8f_l1_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-ao";
|
|
L1F_SO = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-so";
|
|
pm_v6f_l1_so = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-so";
|
|
pm_v8f_l1_so = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof1/regulator-pm-vxf-l1-so";
|
|
L2F = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof2/regulator-pm-vxf-l2";
|
|
pm_v6f_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof2/regulator-pm-vxf-l2";
|
|
pm_v8f_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof2/regulator-pm-vxf-l2";
|
|
L3F = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof3/regulator-pm-vxf-l3";
|
|
pm_v6f_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof3/regulator-pm-vxf-l3";
|
|
pm_v8f_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldof3/regulator-pm-vxf-l3";
|
|
S1G = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg1/regulator-pm-v8g-s1";
|
|
pm_v8g_s1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg1/regulator-pm-v8g-s1";
|
|
S3G = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg3/regulator-pm-v8g-s3";
|
|
pm_v8g_s3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg3/regulator-pm-v8g-s3";
|
|
S4G = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg4/regulator-pm-v8g-s4";
|
|
pm_v8g_s4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpg4/regulator-pm-v8g-s4";
|
|
L1G = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog1/regulator-pm-v8g-l1";
|
|
pm_v8g_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog1/regulator-pm-v8g-l1";
|
|
L2G = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog2/regulator-pm-v8g-l2";
|
|
pm_v8g_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog2/regulator-pm-v8g-l2";
|
|
L3G = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog3/regulator-pm-v8g-l3";
|
|
pm_v8g_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog3/regulator-pm-v8g-l3";
|
|
L3G_AO = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog3/regulator-pm-v8g-l3-ao";
|
|
pm_v8g_l3_ao = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldog3/regulator-pm-v8g-l3-ao";
|
|
S7I = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpi7/regulator-pm-v8i-s7";
|
|
pm_v8i_s7 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpi7/regulator-pm-v8i-s7";
|
|
S8I = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpi8/regulator-pm-v8i-s8";
|
|
pm_v8i_s8 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpi8/regulator-pm-v8i-s8";
|
|
L1I = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8i-l1";
|
|
pm_v8i_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi1/regulator-pm-v8i-l1";
|
|
L2I = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi2/regulator-pm-v8i-l2";
|
|
pm_v8i_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi2/regulator-pm-v8i-l2";
|
|
L3I = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8i-l3";
|
|
pm_v8i_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoi3/regulator-pm-v8i-l3";
|
|
S2J = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj2/regulator-pm-v6j-s2";
|
|
pm_v6j_s2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj2/regulator-pm-v6j-s2";
|
|
S3J = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj3/regulator-pm-v6j-s3";
|
|
pm_v6j_s3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj3/regulator-pm-v6j-s3";
|
|
VRM_S4J = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj4";
|
|
S4J = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj4/regulator-pm-v6j-s4";
|
|
pm_v6j_s4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-smpj4/regulator-pm-v6j-s4";
|
|
L1J = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoj1/regulator-pm-v6j-l1";
|
|
pm_v6j_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoj1/regulator-pm-v6j-l1";
|
|
L2J = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoj2/regulator-pm-v6j-l2";
|
|
pm_v6j_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldoj2/regulator-pm-v6j-l2";
|
|
L1K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok1/regulator-pmr-nalojr-l1";
|
|
pmr_nalojr_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok1/regulator-pmr-nalojr-l1";
|
|
L2K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok2/regulator-pmr-nalojr-l2";
|
|
pmr_nalojr_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok2/regulator-pmr-nalojr-l2";
|
|
L3K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok3/regulator-pmr-nalojr-l3";
|
|
pmr_nalojr_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok3/regulator-pmr-nalojr-l3";
|
|
L4K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok4/regulator-pmr-nalojr-l4";
|
|
pmr_nalojr_l4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok4/regulator-pmr-nalojr-l4";
|
|
L5K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok5/regulator-pmr-nalojr-l5";
|
|
pmr_nalojr_l5 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok5/regulator-pmr-nalojr-l5";
|
|
L6K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok6/regulator-pmr-nalojr-l6";
|
|
pmr_nalojr_l6 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok6/regulator-pmr-nalojr-l6";
|
|
L7K = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok7/regulator-pmr-nalojr-l7";
|
|
pmr_nalojr_l7 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldok7/regulator-pmr-nalojr-l7";
|
|
L1M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom1/regulator-pm8010m-l1";
|
|
pm8010m_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom1/regulator-pm8010m-l1";
|
|
L2M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom2/regulator-pm8010m-l2";
|
|
pm8010m_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom2/regulator-pm8010m-l2";
|
|
L3M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom3/regulator-pm8010m-l3";
|
|
pm8010m_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom3/regulator-pm8010m-l3";
|
|
L4M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom4/regulator-pm8010m-l4";
|
|
pm8010m_l4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom4/regulator-pm8010m-l4";
|
|
L5M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom5/regulator-pm8010m-l5";
|
|
pm8010m_l5 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom5/regulator-pm8010m-l5";
|
|
L6M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom6/regulator-pm8010m-l6";
|
|
pm8010m_l6 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom6/regulator-pm8010m-l6";
|
|
L7M = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom7/regulator-pm8010m-l7";
|
|
pm8010m_l7 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldom7/regulator-pm8010m-l7";
|
|
L1N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon1/regulator-pm8010n-l1";
|
|
pm8010n_l1 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon1/regulator-pm8010n-l1";
|
|
L2N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon2/regulator-pm8010n-l2";
|
|
pm8010n_l2 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon2/regulator-pm8010n-l2";
|
|
L3N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon3/regulator-pm8010n-l3";
|
|
pm8010n_l3 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon3/regulator-pm8010n-l3";
|
|
L4N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon4/regulator-pm8010n-l4";
|
|
pm8010n_l4 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon4/regulator-pm8010n-l4";
|
|
L5N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon5/regulator-pm8010n-l5";
|
|
pm8010n_l5 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon5/regulator-pm8010n-l5";
|
|
L6N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon6/regulator-pm8010n-l6";
|
|
pm8010n_l6 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon6/regulator-pm8010n-l6";
|
|
L7N = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon7/regulator-pm8010n-l7";
|
|
pm8010n_l7 = "/soc/rsc@16500000/drv@2/rpmh-regulator-ldon7/regulator-pm8010n-l7";
|
|
cam_rsc = "/soc/rsc@adc8000";
|
|
cam_rsc_drv0 = "/soc/rsc@adc8000/drv@0";
|
|
cam_bcm_voter0 = "/soc/rsc@adc8000/drv@0/bcm_voter";
|
|
cam_rsc_drv1 = "/soc/rsc@adc8000/drv@1";
|
|
cam_bcm_voter1 = "/soc/rsc@adc8000/drv@1/bcm_voter";
|
|
cam_rsc_drv2 = "/soc/rsc@adc8000/drv@2";
|
|
cam_bcm_voter2 = "/soc/rsc@adc8000/drv@2/bcm_voter";
|
|
disp_rsc = "/soc/rsc@af20000";
|
|
disp_rsc_drv0 = "/soc/rsc@af20000/drv@0";
|
|
disp_crm = "/soc/crm@af21000";
|
|
cam_crm = "/soc/crm@adcb000";
|
|
pcie_crm = "/soc/crm@1d01000";
|
|
spss_pas = "/soc/remoteproc-spss@1880000";
|
|
spss_utils = "/soc/qcom,spss_utils";
|
|
xo_board = "/soc/clocks/xo_board";
|
|
sleep_clk = "/soc/clocks/sleep_clk";
|
|
pcie_0_pipe_clk = "/soc/clocks/pcie_0_pipe_clk";
|
|
ufs_phy_rx_symbol_0_clk = "/soc/clocks/ufs_phy_rx_symbol_0_clk";
|
|
ufs_phy_rx_symbol_1_clk = "/soc/clocks/ufs_phy_rx_symbol_1_clk";
|
|
ufs_phy_tx_symbol_0_clk = "/soc/clocks/ufs_phy_tx_symbol_0_clk";
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk = "/soc/clocks/usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
cpufreq_thermal = "/soc/qcom,cpufreq-thermal";
|
|
cambistmclkcc = "/soc/clock-controller@1760000";
|
|
camcc_crmc = "/soc/syscon@0adcd600";
|
|
camcc = "/soc/clock-controller@ade0000";
|
|
dispcc_crmc = "/soc/syscon@af27800";
|
|
dispcc = "/soc/clock-controller@af00000";
|
|
dispcc_mx = "/soc/clock-controller@af00000/clock-controller@af02000";
|
|
evacc = "/soc/clock-controller@abf0000";
|
|
gcc = "/soc/clock-controller@100000";
|
|
gpucc = "/soc/clock-controller@3d90000";
|
|
gxclkctl = "/soc/clock-controller@3d68024";
|
|
tcsrcc = "/soc/clock-controller@f204008";
|
|
videocc = "/soc/clock-controller@aaf0000";
|
|
apsscc = "/soc/syscon@16450000";
|
|
mccc = "/soc/syscon@240ba000";
|
|
gxclkctldebugcc = "/soc/syscon@3d64000";
|
|
debugcc = "/soc/qcom,cc-debug";
|
|
cam_cc_ipe_0_gdsc = "/soc/qcom,gdsc@adf017c";
|
|
cam_cc_ofe_gdsc = "/soc/qcom,gdsc@adf00c8";
|
|
cam_cc_tfe_0_gdsc = "/soc/qcom,gdsc@adf1004";
|
|
cam_cc_tfe_1_gdsc = "/soc/qcom,gdsc@adf1084";
|
|
cam_cc_tfe_2_gdsc = "/soc/qcom,gdsc@adf10ec";
|
|
cam_cc_titan_top_gdsc = "/soc/qcom,gdsc@adf134c";
|
|
disp_cc_mdss_core_gdsc = "/soc/qcom,gdsc@af09000";
|
|
disp_cc_mdss_core_int2_gdsc = "/soc/qcom,gdsc@af0b000";
|
|
eva_cc_mvs0_gdsc = "/soc/qcom,gdsc@abf8068";
|
|
eva_cc_mvs0c_gdsc = "/soc/qcom,gdsc@abf8034";
|
|
gcc_apcs_gdsc_vote_ctrl = "/soc/syscon@15214c";
|
|
gcc_pcie_0_gdsc = "/soc/qcom,gdsc@16b004";
|
|
gcc_pcie_0_phy_gdsc = "/soc/qcom,gdsc@16c000";
|
|
gcc_ufs_mem_phy_gdsc = "/soc/qcom,gdsc@19e000";
|
|
gcc_ufs_phy_gdsc = "/soc/qcom,gdsc@177004";
|
|
gcc_usb30_prim_gdsc = "/soc/qcom,gdsc@139004";
|
|
gcc_usb3_phy_gdsc = "/soc/qcom,gdsc@150018";
|
|
gpu_cc_cx_gdsc_hw_ctrl = "/soc/syscon@3d99094";
|
|
gpu_cc_cx_gdsc = "/soc/qcom,gdsc@3d99080";
|
|
gx_clkctl_gx_gdsc = "/soc/qcom,gdsc@3d68024";
|
|
video_cc_mvs0_gdsc = "/soc/qcom,gdsc@aaf8068";
|
|
video_cc_mvs0c_gdsc = "/soc/qcom,gdsc@aaf8034";
|
|
trust_ui_vm_vblk0_ring = "/soc/trust_ui_vm_vblk0_ring";
|
|
trust_ui_vm_vblk1_ring = "/soc/trust_ui_vm_vblk1_ring";
|
|
trust_ui_vm_vsock_ring = "/soc/trust_ui_vm_vsock_ring";
|
|
trust_ui_vm_swiotlb = "/soc/trust_ui_vm_swiotlb";
|
|
trust_ui_vm = "/soc/qcom,trust_ui_vm";
|
|
trust_ui_vm_virt_be0 = "/soc/trust_ui_vm_virt_be0@11";
|
|
trust_ui_vm_virt_be1 = "/soc/trust_ui_vm_virt_be1@10";
|
|
trust_ui_vm_virt_be2 = "/soc/trust_ui_vm_virt_be2@15";
|
|
ufsphy_mem = "/soc/ufsphy_mem@1d80000";
|
|
ice_cfg = "/soc/shared_ice";
|
|
qcom_cedev = "/soc/qcedev@1de0000";
|
|
rng = "/soc/rng@10c3000";
|
|
ufshc_dma_resv = "/soc/ufshc_dma_resv_region";
|
|
ufshc_mem = "/soc/ufshc@1d84000";
|
|
sdhc2_opp_table = "/soc/sdhc2-opp-table";
|
|
sdhc_2_dma_resv = "/soc/sdhc_2_dma_resv_region";
|
|
sdhc_2 = "/soc/sdhci@8804000";
|
|
cpu_pmu = "/soc/cpu-pmu";
|
|
msm_gpu = "/soc/qcom,kgsl-3d0@3d00000";
|
|
spmi_bus = "/soc/qcom,spmi@c42d000";
|
|
spmi0_bus = "/soc/qcom,spmi@c42d000";
|
|
spmi1_bus = "/soc/qcom,spmi@c432000";
|
|
spmi0_debug_bus = "/soc/spmi-debug@10b14000";
|
|
adsp_sleepmon = "/soc/adsp-sleepmon";
|
|
adsp_pas = "/soc/remoteproc-adsp@03000000";
|
|
remoteproc_adsp_glink = "/soc/remoteproc-adsp@03000000/glink-edge";
|
|
modem_pas = "/soc/remoteproc-mss@04080000";
|
|
cdsp_pas = "/soc/remoteproc-cdsp@32300000";
|
|
remoteproc_cdsp_glink = "/soc/remoteproc-cdsp@32300000/glink-edge";
|
|
msm_cdsp_rm = "/soc/remoteproc-cdsp@32300000/glink-edge/qcom,msm_cdsprm_rpmsg/qcom,msm_cdsp_rm";
|
|
battery_charger = "/soc/qcom,pmic_glink/qcom,battery_charger";
|
|
ucsi = "/soc/qcom,pmic_glink/qcom,ucsi";
|
|
altmode = "/soc/qcom,pmic_glink/qcom,altmode";
|
|
pmic_glink_debug = "/soc/qcom,pmic_glink_log/qcom,pmic_glink_debug";
|
|
pmih010x_glink_debug = "/soc/qcom,pmic_glink_log/qcom,pmic_glink_debug/spmi@0/qcom,pmih010x-debug@7";
|
|
pmic_glink_adc = "/soc/qcom,pmic_glink_log/qcom,glink-adc";
|
|
thermal_zones = "/soc/thermal-zones";
|
|
cpu0_emerg0 = "/soc/thermal-zones/cpu-0-0-0/trips/cpu0-emerg0-cfg";
|
|
cpu0_emerg0_1 = "/soc/thermal-zones/cpu-0-0-0/trips/cpu0-emerg0-1-cfg";
|
|
cpu0_emerg1 = "/soc/thermal-zones/cpu-0-0-1/trips/cpu0-emerg1-cfg";
|
|
cpu0_emerg1_1 = "/soc/thermal-zones/cpu-0-0-1/trips/cpu0-emerg1-1-cfg";
|
|
cpu1_emerg0 = "/soc/thermal-zones/cpu-0-1-0/trips/cpu1-emerg0-cfg";
|
|
cpu1_emerg0_1 = "/soc/thermal-zones/cpu-0-1-0/trips/cpu1-emerg0-1-cfg";
|
|
cpu1_emerg1 = "/soc/thermal-zones/cpu-0-1-1/trips/cpu1-emerg1-cfg";
|
|
cpu1_emerg1_1 = "/soc/thermal-zones/cpu-0-1-1/trips/cpu1-emerg1-1-cfg";
|
|
cpu2_emerg0 = "/soc/thermal-zones/cpu-0-2-0/trips/cpu2-emerg0-cfg";
|
|
cpu2_emerg0_1 = "/soc/thermal-zones/cpu-0-2-0/trips/cpu2-emerg0-1-cfg";
|
|
cpu2_emerg1 = "/soc/thermal-zones/cpu-0-2-1/trips/cpu2-emerg1-cfg";
|
|
cpu2_emerg1_1 = "/soc/thermal-zones/cpu-0-2-1/trips/cpu2-emerg1-1-cfg";
|
|
cpu3_emerg0 = "/soc/thermal-zones/cpu-0-3-0/trips/cpu3-emerg0-cfg";
|
|
cpu3_emerg0_1 = "/soc/thermal-zones/cpu-0-3-0/trips/cpu3-emerg0-1-cfg";
|
|
cpu3_emerg1 = "/soc/thermal-zones/cpu-0-3-1/trips/cpu3-emerg1-cfg";
|
|
cpu3_emerg1_1 = "/soc/thermal-zones/cpu-0-3-1/trips/cpu3-emerg1-1-cfg";
|
|
cpu4_emerg0 = "/soc/thermal-zones/cpu-0-4-0/trips/cpu4-emerg0-cfg";
|
|
cpu4_emerg0_1 = "/soc/thermal-zones/cpu-0-4-0/trips/cpu4-emerg0-1-cfg";
|
|
cpu4_emerg1 = "/soc/thermal-zones/cpu-0-4-1/trips/cpu4-emerg1-cfg";
|
|
cpu4_emerg1_1 = "/soc/thermal-zones/cpu-0-4-1/trips/cpu4-emerg1-1-cfg";
|
|
cpu5_emerg0 = "/soc/thermal-zones/cpu-0-5-0/trips/cpu5-emerg0-cfg";
|
|
cpu5_emerg0_1 = "/soc/thermal-zones/cpu-0-5-0/trips/cpu5-emerg0-1-cfg";
|
|
cpu5_emerg1 = "/soc/thermal-zones/cpu-0-5-1/trips/cpu5-emerg1-cfg";
|
|
cpu5_emerg1_1 = "/soc/thermal-zones/cpu-0-5-1/trips/cpu5-emerg1-1-cfg";
|
|
cpu6_emerg0 = "/soc/thermal-zones/cpu-1-0-0/trips/cpu6-emerg0-cfg";
|
|
cpu6_emerg0_1 = "/soc/thermal-zones/cpu-1-0-0/trips/cpu6-emerg0-1-cfg";
|
|
cpu6_emerg1 = "/soc/thermal-zones/cpu-1-0-1/trips/cpu6-emerg1-cfg";
|
|
cpu6_emerg1_1 = "/soc/thermal-zones/cpu-1-0-1/trips/cpu6-emerg1-1-cfg";
|
|
cpu7_emerg0 = "/soc/thermal-zones/cpu-1-1-0/trips/cpu7-emerg0-cfg";
|
|
cpu7_emerg0_1 = "/soc/thermal-zones/cpu-1-1-0/trips/cpu7-emerg0-1-cfg";
|
|
cpu7_emerg1 = "/soc/thermal-zones/cpu-1-1-1/trips/cpu7-emerg1-cfg";
|
|
cpu7_emerg1_1 = "/soc/thermal-zones/cpu-1-1-1/trips/cpu7-emerg1-1-cfg";
|
|
ddr_config0 = "/soc/thermal-zones/ddr/trips/ddr0-config";
|
|
gpu0_tj_cfg = "/soc/thermal-zones/gpuss-0/trips/tj_cfg";
|
|
gpu1_tj_cfg = "/soc/thermal-zones/gpuss-1/trips/tj_cfg";
|
|
gpu2_tj_cfg = "/soc/thermal-zones/gpuss-2/trips/tj_cfg";
|
|
gpu3_tj_cfg = "/soc/thermal-zones/gpuss-3/trips/tj_cfg";
|
|
gpu4_tj_cfg = "/soc/thermal-zones/gpuss-4/trips/tj_cfg";
|
|
gpu5_tj_cfg = "/soc/thermal-zones/gpuss-5/trips/tj_cfg";
|
|
gpu6_tj_cfg = "/soc/thermal-zones/gpuss-6/trips/tj_cfg";
|
|
gpu7_tj_cfg = "/soc/thermal-zones/gpuss-7/trips/tj_cfg";
|
|
mdmss0_config0 = "/soc/thermal-zones/mdmss-0/trips/mdmss0-config0";
|
|
mdmss0_config1 = "/soc/thermal-zones/mdmss-0/trips/mdmss0-config1";
|
|
mdmss1_config0 = "/soc/thermal-zones/mdmss-1/trips/mdmss1-config0";
|
|
mdmss1_config1 = "/soc/thermal-zones/mdmss-1/trips/mdmss1-config1";
|
|
mdmss2_config0 = "/soc/thermal-zones/mdmss-2/trips/mdmss2-config0";
|
|
mdmss2_config1 = "/soc/thermal-zones/mdmss-2/trips/mdmss2-config1";
|
|
mdmss3_config0 = "/soc/thermal-zones/mdmss-3/trips/mdmss3-config0";
|
|
mdmss3_config1 = "/soc/thermal-zones/mdmss-3/trips/mdmss3-config1";
|
|
mmio_sram = "/soc/mmio-sram@0x17b4e000";
|
|
cpu_scp_lpri = "/soc/mmio-sram@0x17b4e000/scmi-shmem@0";
|
|
cpucp_rx = "/soc/mmio-sram@0x17b4e000/scmi-shmem@1";
|
|
cpucp = "/soc/qcom,cpucp@0x17830000";
|
|
pdp0 = "/soc/qcom,pdp0@0x18980000";
|
|
pdp1 = "/soc/qcom,pdp1@0x19980000";
|
|
scmi = "/soc/qcom,scmi";
|
|
scmi_perf = "/soc/qcom,scmi/protocol@13";
|
|
scmi_clk = "/soc/qcom,scmi/protocol@14";
|
|
scmi_qcom = "/soc/qcom,scmi/protocol@80";
|
|
cpucp_fast = "/soc/qcom,cpucp_fast";
|
|
cpucp_log = "/soc/qcom,cpucp_log@0x81210000";
|
|
pdp0_log = "/soc/qcom,pdp0_log@0x81f41000";
|
|
pdp1_log = "/soc/qcom,pdp1_log@0x81f61000";
|
|
qcom_mpam = "/soc/qcom,mpam";
|
|
cpu_mpam = "/soc/qcom,cpu_mpam";
|
|
noc_bw_mpam = "/soc/qcom,noc_bw_mpam";
|
|
qcom_slc_mpam = "/soc/qcom,slc_mpam";
|
|
llcc_pmu = "/soc/llcc-pmu@24095000";
|
|
qcom_pmu = "/soc/qcom,pmu";
|
|
ddr_freq_table = "/soc/ddr-freq-table";
|
|
llcc_freq_table = "/soc/llcc-freq-table";
|
|
ddrqos_freq_table = "/soc/ddrqos-freq-table";
|
|
qcom_dcvs = "/soc/qcom,dcvs";
|
|
qcom_ddr_dcvs_hw = "/soc/qcom,dcvs/ddr";
|
|
ddr_dcvs_sp = "/soc/qcom,dcvs/ddr/sp";
|
|
ddr_dcvs_fp = "/soc/qcom,dcvs/ddr/fp";
|
|
qcom_llcc_dcvs_hw = "/soc/qcom,dcvs/llcc";
|
|
llcc_dcvs_sp = "/soc/qcom,dcvs/llcc/sp";
|
|
llcc_dcvs_fp = "/soc/qcom,dcvs/llcc/fp";
|
|
qcom_ddrqos_dcvs_hw = "/soc/qcom,dcvs/ddrqos";
|
|
ddrqos_dcvs_sp = "/soc/qcom,dcvs/ddrqos/sp";
|
|
qcom_memlat = "/soc/qcom,memlat";
|
|
ddrqos_gold_lat = "/soc/qcom,memlat/ddrqos/gold";
|
|
ddrqos_prime_lat = "/soc/qcom,memlat/ddrqos/prime";
|
|
ddrqos_prime_latfloor = "/soc/qcom,memlat/ddrqos/prime-latfloor";
|
|
qcom_llcc_ddr_vote = "/soc/qcom,llcc-ddr-vote";
|
|
bwmon_llcc_gold = "/soc/qcom,bwmon-llcc-gold@240B3300";
|
|
bwmon_llcc_prime = "/soc/qcom,bwmon-llcc-prime@240B7300";
|
|
soccp_pas = "/soc/remoteproc-soccp@a3380000";
|
|
qfprom = "/soc/qfprom@221c8000";
|
|
gpu_speed_bin = "/soc/qfprom@221c8000/gpu_speed_bin@138";
|
|
ssip_config = "/soc/qfprom@221c8000/ssip_config@13e";
|
|
cnss_audio_iommu_group0 = "/soc/cnss_audio_iommu_group0";
|
|
ipcb_tgu = "/soc/tgu@10b0e000";
|
|
spmi_tgu0 = "/soc/tgu@10b0f000";
|
|
spmi_tgu1 = "/soc/tgu@10b10000";
|
|
csr = "/soc/csr@10001000";
|
|
swao_csr = "/soc/csr@10b11000";
|
|
tpdm_gfx = "/soc/tpdm@10900000";
|
|
tpdm_gfx_out_funnel_gfx_dl = "/soc/tpdm@10900000/out-ports/port/endpoint";
|
|
funnel_gfx = "/soc/funnel@10963000";
|
|
funnel_gfx_out_funnel_gfx_dl = "/soc/funnel@10963000/out-ports/port/endpoint";
|
|
funnel_gfx_dl = "/soc/funnel@10902000";
|
|
funnel_gfx_dl_in_tpdm_gfx = "/soc/funnel@10902000/in-ports/port@0/endpoint";
|
|
funnel_gfx_dl_in_funnel_gfx = "/soc/funnel@10902000/in-ports/port@1/endpoint";
|
|
replicator_dummy_out_tpda_dlet = "/soc/funnel@10902000/out-ports/port@0/endpoint";
|
|
replicator_dummy_out_funnel_dlet = "/soc/funnel@10902000/out-ports/port@1/endpoint";
|
|
tpda_dlet = "/soc/tpda@10c38000";
|
|
tpda_dlet_in_replicator_dummy = "/soc/tpda@10c38000/in-ports/port@0/endpoint";
|
|
tpda_dlet_out_funnel_dlet = "/soc/tpda@10c38000/out-ports/port/endpoint";
|
|
funnel_dlet = "/soc/funnel@10c39000";
|
|
funnel_dlet_in_tpda_dlet = "/soc/funnel@10c39000/in-ports/port@0/endpoint";
|
|
funnel_dlet_in_replicator_dummy = "/soc/funnel@10c39000/in-ports/port@1/endpoint";
|
|
funnel_dlet_out_tn_ag = "/soc/funnel@10c39000/out-ports/port/endpoint";
|
|
tpdm_video = "/soc/tpdm@10830000";
|
|
tpdm_video_out_funnel_video = "/soc/tpdm@10830000/out-ports/port/endpoint";
|
|
funnel_vide0 = "/soc/funnel@10832000";
|
|
funnel_video_in_tpdm_video = "/soc/funnel@10832000/in-ports/port@0/endpoint";
|
|
funnel_video_out_tpda_dlmm = "/soc/funnel@10832000/out-ports/port@0/endpoint";
|
|
tpdm_eva = "/soc/tpdm@109c0000";
|
|
tpdm_eva_out_funnel_eva = "/soc/tpdm@109c0000/out-ports/port/endpoint";
|
|
funnel_eva = "/soc/funnel@109c2000";
|
|
funnel_eva_in_tpdm_eva = "/soc/funnel@109c2000/in-ports/port@0/endpoint";
|
|
funnel_eva_out_tpda_dlmm = "/soc/funnel@109c2000/out-ports/port@0/endpoint";
|
|
tpdm_mdss = "/soc/tpdm@10c60000";
|
|
tpdm_mdss_out_funnel_mdss = "/soc/tpdm@10c60000/out-ports/port/endpoint";
|
|
tpdm_mdss_rscc = "/soc/tpdm@10c61000";
|
|
tpdm_mdss_rscc_out_funnel_mdss = "/soc/tpdm@10c61000/out-ports/port/endpoint";
|
|
funnel_dlmm = "/soc/funnel@10c09000";
|
|
funnel_mdss = "/soc/funnel@10c09000";
|
|
funnel_dlmm_in_tpda_dlmm = "/soc/funnel@10c09000/in-ports/port@0/endpoint";
|
|
funnel_mdss_in_tpdm_mdss = "/soc/funnel@10c09000/in-ports/port@0/endpoint";
|
|
funnel_mdss_in_tpdm_mdss_rscc = "/soc/funnel@10c09000/in-ports/port@1/endpoint";
|
|
funnel_dlmm_out_tn_ag = "/soc/funnel@10c09000/out-ports/port@0/endpoint";
|
|
funnel_mdss0_out_tpda_dlmm = "/soc/funnel@10c09000/out-ports/port@0/endpoint";
|
|
funnel_mdss1_out_tpda_dlmm = "/soc/funnel@10c09000/out-ports/port@1/endpoint";
|
|
tpda_dlmm = "/soc/tpda@10c08000";
|
|
tpda_dlmm_in_funnel_video = "/soc/tpda@10c08000/in-ports/port@0/endpoint";
|
|
tpda_dlmm_in_funnel_eva = "/soc/tpda@10c08000/in-ports/port@1/endpoint";
|
|
tpda_dlmm_in_funnel_mdss0 = "/soc/tpda@10c08000/in-ports/port@2/endpoint";
|
|
tpda_dlmm_in_funnel_mdss1 = "/soc/tpda@10c08000/in-ports/port@3/endpoint";
|
|
tpda_dlmm_out_funnel_dlmm = "/soc/tpda@10c08000/out-ports/port/endpoint";
|
|
tpdm_soccp = "/soc/tpdm@10ba4000";
|
|
tpdm_soccp_crdl_out_tn_soccp = "/soc/tpdm@10ba4000/out-ports/port/endpoint";
|
|
tn_soccp = "/soc/traceNoc@10ba0000";
|
|
tn_soccp_in_tpdm_soccp_crdl = "/soc/traceNoc@10ba0000/in-ports/port@0/endpoint";
|
|
tn_soccp_out_tn_ag = "/soc/traceNoc@10ba0000/out-ports/port/endpoint";
|
|
tpdm_turing = "/soc/tpdm@10980000";
|
|
tpdm_turing_out_tpda_turing = "/soc/tpdm@10980000/out-ports/port/endpoint";
|
|
tpdm_turing_llm = "/soc/tpdm@10981000";
|
|
tpdm_turing_llm_out_tpda_turing = "/soc/tpdm@10981000/out-ports/port/endpoint";
|
|
tpdm_turing_llm2 = "/soc/tpdm@10982000";
|
|
tpdm_turing_llm2_out_tpda_turing = "/soc/tpdm@10982000/out-ports/port/endpoint";
|
|
tpdm_dpm1 = "/soc/tpdm@10983000";
|
|
tpdm_dpm1_out_tpda_turing = "/soc/tpdm@10983000/out-ports/port/endpoint";
|
|
tpdm_dmp2 = "/soc/tpdm@10984000";
|
|
tpdm_dmp2_out_tpda_turing = "/soc/tpdm@10984000/out-ports/port/endpoint";
|
|
tpda_turing = "/soc/tpda@10986000";
|
|
tpda_turing_in_tpdm_turing = "/soc/tpda@10986000/in-ports/port@0/endpoint";
|
|
tpda_turing_in_tpdm_turing_llm = "/soc/tpda@10986000/in-ports/port@1/endpoint";
|
|
tpda_turing_in_tpdm_turing_llm2 = "/soc/tpda@10986000/in-ports/port@2/endpoint";
|
|
tpda_turing_in_tpdm_dpm1 = "/soc/tpda@10986000/in-ports/port@3/endpoint";
|
|
tpda_turing_in_tpdm_dmp2 = "/soc/tpda@10986000/in-ports/port@4/endpoint";
|
|
tpda_turing_out_funnel_turing = "/soc/tpda@10986000/out-ports/port@0/endpoint";
|
|
turing_etm0 = "/soc/turing-etm0";
|
|
turing_etm0_out_funnel_turing_dup = "/soc/turing-etm0/out-ports/port@0/endpoint";
|
|
turing_etm0_out_qmi = "/soc/turing-etm0/out-ports/port@1/endpoint";
|
|
funnel_turing_dup = "/soc/funnel@10940000";
|
|
funnel_turing_dup_in_turing_etm0 = "/soc/funnel@10940000/in-ports/port@3/endpoint";
|
|
funnel_turing_dup_out_funnel_turing = "/soc/funnel@10940000/out-ports/port/endpoint";
|
|
funnel_turing = "/soc/funnel@10987000";
|
|
funnel_turing_in_tpda_turing = "/soc/funnel@10987000/in-ports/port@0/endpoint";
|
|
funnel_turing_in_funnel_turing_dup = "/soc/funnel@10987000/in-ports/port@4/endpoint";
|
|
funnel_turing_out_tn_ag = "/soc/funnel@10987000/out-ports/port@0/endpoint";
|
|
tpdm_modem0 = "/soc/tpdm@10800000";
|
|
tpdm_modem0_out_tpda_modem = "/soc/tpdm@10800000/out-ports/port/endpoint";
|
|
tpdm_modem1 = "/soc/tpdm@10801000";
|
|
tpdm_modem1_out_tpda_modem = "/soc/tpdm@10801000/out-ports/port/endpoint";
|
|
tpdm_modem_rscc = "/soc/tpdm@1080d000";
|
|
tpdm_modem_rscc_out_funnel_modem_q6 = "/soc/tpdm@1080d000/out-ports/port/endpoint";
|
|
modem_etm0_out_funnel_modem_q6_dup = "/soc/modem-etm0/out-ports/port@0/endpoint";
|
|
modem_etm0_out_qmi = "/soc/modem-etm0/out-ports/port@1/endpoint";
|
|
modem2_etm0_out_funnel_modem = "/soc/modem2-etm0/out-ports/port@0/endpoint";
|
|
modem2_etm0_out_qmi = "/soc/modem2-etm0/out-ports/port@1/endpoint";
|
|
modem_diag = "/soc/modem_diag";
|
|
modem_diag_out_funnel_modem_q6 = "/soc/modem_diag/out-ports/port/endpoint";
|
|
tpda_modem = "/soc/tpda@10803000";
|
|
tpda_modem_in_tpdm_modem0 = "/soc/tpda@10803000/in-ports/port@0/endpoint";
|
|
tpda_modem_in_tpdm_modem1 = "/soc/tpda@10803000/in-ports/port@1/endpoint";
|
|
tpda_modem_out_funnel_modem_dl = "/soc/tpda@10803000/out-ports/port/endpoint";
|
|
funnel_modem_q6_dup = "/soc/funnel@1080d000";
|
|
funnel_modem_q6_dup_in_modem_etm0 = "/soc/funnel@1080d000/in-ports/port@0/endpoint";
|
|
funnel_modem_q6_dup_out_funnel_modem_q6 = "/soc/funnel@1080d000/out-ports/port/endpoint";
|
|
funnel_modem_q6 = "/soc/funnel@1080c000";
|
|
funnel_modem_q6_in_funnel_modem_q6_dup = "/soc/funnel@1080c000/in-ports/port@1/endpoint";
|
|
funnel_modem_q6_in_modem_diag = "/soc/funnel@1080c000/in-ports/port@2/endpoint";
|
|
funnel_modem_q6_in_tpdm_modem_rscc = "/soc/funnel@1080c000/in-ports/port@3/endpoint";
|
|
funnel_modem_q6_out_funnel_modem_dl = "/soc/funnel@1080c000/out-ports/port/endpoint";
|
|
funnel_modem_dl = "/soc/funnel@10804000";
|
|
funnel_modem_dl_in_tpda_modem = "/soc/funnel@10804000/in-ports/port@0/endpoint";
|
|
funnel_modem_in_modem2_etm0 = "/soc/funnel@10804000/in-ports/port@1/endpoint";
|
|
funnel_modem_dl_in_funnel_modem_q6 = "/soc/funnel@10804000/in-ports/port@3/endpoint";
|
|
funnel_modem_dl_out_tn_ag = "/soc/funnel@10804000/out-ports/port/endpoint";
|
|
tpdm_tmess_prng = "/soc/tpdm@10cc9000";
|
|
tpdm_tmess_prng_out_tpda_tmess = "/soc/tpdm@10cc9000/out-ports/port/endpoint";
|
|
tpdm_tmess0 = "/soc/tpdm@10cc0000";
|
|
tpdm_tmess0_out_tpda_tmess = "/soc/tpdm@10cc0000/out-ports/port/endpoint";
|
|
tpdm_tmess1 = "/soc/tpdm@10cc1000";
|
|
tpdm_tmess1_out_tpda_tmess = "/soc/tpdm@10cc1000/out-ports/port/endpoint";
|
|
tpda_tmess = "/soc/tpda@10cc4000";
|
|
tpda_tmess_in_tpdm_tmess_prng = "/soc/tpda@10cc4000/in-ports/port@0/endpoint";
|
|
tpda_tmess_in_tpdm_tmess0 = "/soc/tpda@10cc4000/in-ports/port@1/endpoint";
|
|
tpda_tmess_in_tpdm_tmess1 = "/soc/tpda@10cc4000/in-ports/port@2/endpoint";
|
|
tpda_tmess_out_funnel_tmess = "/soc/tpda@10cc4000/out-ports/port/endpoint";
|
|
funnel_tmess = "/soc/funnel@10cc5000";
|
|
funnel_tmess_in_tpda_tmess = "/soc/funnel@10cc5000/in-ports/port@0/endpoint";
|
|
funnel_tmess_out_tn_ag = "/soc/funnel@10cc5000/out-ports/port@0/endpoint";
|
|
tpdm_titan = "/soc/tpdm@10a04000";
|
|
tpdm_titan_dsb_out_tn_titan = "/soc/tpdm@10a04000/out-ports/port/endpoint";
|
|
tpdm_titan_rscc = "/soc/tpdm@10a0e000";
|
|
tpdm_titan_rscc_out_tpda_titan = "/soc/tpdm@10a0e000/out-ports/port/endpoint";
|
|
tpda_titan = "/soc/tpda@10a0f000";
|
|
tpda_titan_in_tpdm_titan_rscc = "/soc/tpda@10a0f000/in-ports/port@0/endpoint";
|
|
tpda_titan_out_tn_titan = "/soc/tpda@10a0f000/out-ports/port@0/endpoint";
|
|
tn_titan = "/soc/tn@0x10a00000";
|
|
tn_titan_in_tpda_titan = "/soc/tn@0x10a00000/in-ports/port@4/endpoint";
|
|
tn_titan_in_tpdm_titan_dsb = "/soc/tn@0x10a00000/in-ports/port@5/endpoint";
|
|
tn_titan_out_tn_ag = "/soc/tn@0x10a00000/out-ports/port@0/endpoint";
|
|
tpdm_spss = "/soc/tpdm@10880000";
|
|
tpdm_spss_out_funnel_spss = "/soc/tpdm@10880000/out-ports/port/endpoint";
|
|
funnel_spss = "/soc/funnel@10883000";
|
|
funnel_spss_in_tpdm_spss = "/soc/funnel@10883000/in-ports/port@0/endpoint";
|
|
funnel_spss_out_tn_ag = "/soc/funnel@10883000/out-ports/port/endpoint";
|
|
tpdm_rscc = "/soc/tpdm@10c70000";
|
|
tpdm_rscc_out_tpda_rscc = "/soc/tpdm@10c70000/out-ports/port/endpoint";
|
|
tpda_pcie_rscc = "/soc/tpda@10c71000";
|
|
tpda_rscc_in_tpdm_rscc = "/soc/tpda@10c71000/in-ports/port@0/endpoint";
|
|
tpda_pcie_out_tn_ag = "/soc/tpda@10c71000/out-ports/port/endpoint";
|
|
tpdm_mm_bcv = "/soc/tpdm@1084e000";
|
|
tpdm_mm_bcv_out_tpda_mm = "/soc/tpdm@1084e000/out-ports/port/endpoint";
|
|
tpdm_mm_lmh = "/soc/tpdm@1084f00";
|
|
tpdm_mm_lmh_out_tpda_mm = "/soc/tpdm@1084f00/out-ports/port/endpoint";
|
|
tpdm_mm_dpm = "/soc/tpdm@10850000";
|
|
tpdm_mm_dpm_out_tpda_mm = "/soc/tpdm@10850000/out-ports/port/endpoint";
|
|
tpda_mm = "/soc/tpda@10851000";
|
|
tpda_mm_in_tpdm_mm_bcv = "/soc/tpda@10851000/in-ports/port@0/endpoint";
|
|
tpda_mm_in_tpdm_mm_lmh = "/soc/tpda@10851000/in-ports/port@1/endpoint";
|
|
tpda_mm_in_tpdm_mm_dpm = "/soc/tpda@10851000/in-ports/port@2/endpoint";
|
|
tpda_mm_out_tn_ag = "/soc/tpda@10851000/out-ports/port@0/endpoint";
|
|
tpdm_llm_lmh0 = "/soc/tpdm@1218f000";
|
|
tpdm_llm_silver_out_tpda_apss = "/soc/tpdm@1218f000/out-ports/port/endpoint";
|
|
tpdm_llm_lmh1 = "/soc/tpdm@12190000";
|
|
tpdm_llm_gold_out_tpda_apss = "/soc/tpdm@12190000/out-ports/port/endpoint";
|
|
tpdm_ext_dsb0 = "/soc/tpdm@1218a000";
|
|
tpdm_llm_ext_out_tpda_apss = "/soc/tpdm@1218a000/out-ports/port/endpoint";
|
|
tpdm_ext_dsb1 = "/soc/tpdm@1218b000";
|
|
tpdm_llm_gold_apc_out_tpda_apss = "/soc/tpdm@1218b000/out-ports/port/endpoint";
|
|
tpdm_ext_dsb2 = "/soc/tpdm@1218c000";
|
|
tpdm_apss_ubwcp_out_tpda_apss = "/soc/tpdm@1218c000/out-ports/port/endpoint";
|
|
tpdm_ext_dsb3 = "/soc/tpdm@1218d000";
|
|
tpdm_apss_apc2_out_tpda_apss = "/soc/tpdm@1218d000/out-ports/port/endpoint";
|
|
tpdm_ext_dsb4 = "/soc/tpdm@1218e000";
|
|
tpdm_apss_0_out_tpda_apss = "/soc/tpdm@1218e000/out-ports/port/endpoint";
|
|
tpdm_ext_cmb0 = "/soc/tpdm@12181000";
|
|
tpdm_apss1_out_tpda_apss = "/soc/tpdm@12181000/out-ports/port/endpoint";
|
|
tpdm_ext_cmb1 = "/soc/tpdm@12183000";
|
|
tpdm_ext_cmb1_out_tpda_apss = "/soc/tpdm@12183000/out-ports/port/endpoint";
|
|
tpdm_ext_cmb2 = "/soc/tpdm@12185000";
|
|
tpdm_ext_cmb2_out_tpda_apss = "/soc/tpdm@12185000/out-ports/port/endpoint";
|
|
tpdm_ext_cmb3 = "/soc/tpdm@12187000";
|
|
tpdm_ext_cmb3_out_tpda_apss = "/soc/tpdm@12187000/out-ports/port/endpoint";
|
|
tpdm_int_cmb = "/soc/tpdm@12194000";
|
|
tpdm_int_cmb_out_tpda_apss = "/soc/tpdm@12194000/out-ports/port/endpoint";
|
|
tpda_apss = "/soc/tpda@12196000";
|
|
tpda_apss_in_tpdm_llm_silver = "/soc/tpda@12196000/in-ports/port@0/endpoint";
|
|
tpda_apss_in_tpdm_llm_gold = "/soc/tpda@12196000/in-ports/port@1/endpoint";
|
|
tpda_apss_in_tpdm_llm_ext = "/soc/tpda@12196000/in-ports/port@2/endpoint";
|
|
tpda_apss_in_tpdm_llm_gold_apc = "/soc/tpda@12196000/in-ports/port@3/endpoint";
|
|
tpda_apss_in_tpdm_apss_ubwcp = "/soc/tpda@12196000/in-ports/port@4/endpoint";
|
|
tpda_apss_in_tpdm_apss_apc2 = "/soc/tpda@12196000/in-ports/port@5/endpoint";
|
|
tpda_apss_in_tpdm_apss_0 = "/soc/tpda@12196000/in-ports/port@6/endpoint";
|
|
tpda_apss_in_tpdm_apss1 = "/soc/tpda@12196000/in-ports/port@7/endpoint";
|
|
tpda_apss_in_tpdm_ext_cmb1 = "/soc/tpda@12196000/in-ports/port@8/endpoint";
|
|
tpda_apss_in_tpdm_ext_cmb2 = "/soc/tpda@12196000/in-ports/port@9/endpoint";
|
|
tpda_apss_in_tpdm_ext_cmb3 = "/soc/tpda@12196000/in-ports/port@a/endpoint";
|
|
tpda_apss_in_tpdm_int_cmb = "/soc/tpda@12196000/in-ports/port@b/endpoint";
|
|
tpda_apss_out_funnel_apss = "/soc/tpda@12196000/out-ports/port/endpoint";
|
|
etm0_out_funnel_etm0 = "/soc/etm@12c21000/out-ports/port/endpoint";
|
|
uetm0_out_funnel_etm0 = "/soc/uetm0/out-ports/port/endpoint";
|
|
etm0_out_replicator_ncc0_0 = "/soc/funnel-etm0/out-ports/port/endpoint";
|
|
funnel_etm0_in_etm0 = "/soc/funnel-etm0/in-ports/port@0/endpoint";
|
|
funnel_etm0_in_uetm0 = "/soc/funnel-etm0/in-ports/port@1/endpoint";
|
|
replicator_ncc0_0 = "/soc/replicator@13490000";
|
|
replicator_ncc0_0_in_etm0 = "/soc/replicator@13490000/in-ports/port/endpoint";
|
|
rep_ncc0_0_out_funnel_ncc0_lv1 = "/soc/replicator@13490000/out-ports/port@0/endpoint";
|
|
etm1_out_funnel_etm1 = "/soc/etm@12d21000/out-ports/port/endpoint";
|
|
uetm1_out_funnel_etm1 = "/soc/uetm1/out-ports/port/endpoint";
|
|
etm1_out_replicator_ncc0_1 = "/soc/funnel-etm1/out-ports/port/endpoint";
|
|
funnel_etm1_in_etm1 = "/soc/funnel-etm1/in-ports/port@0/endpoint";
|
|
funnel_etm1_in_uetm1 = "/soc/funnel-etm1/in-ports/port@1/endpoint";
|
|
replicator_ncc0_1 = "/soc/replicator@134a0000";
|
|
replicator_ncc0_1_in_etm1 = "/soc/replicator@134a0000/in-ports/port/endpoint";
|
|
rep_ncc0_1_out_funnel_ncc0_lv1 = "/soc/replicator@134a0000/out-ports/port@0/endpoint";
|
|
etm2_out_funnel_etm2 = "/soc/etm@12e21000/out-ports/port/endpoint";
|
|
uetm2_out_funnel_etm2 = "/soc/uetm2/out-ports/port/endpoint";
|
|
etm2_out_replicator_ncc0_2 = "/soc/funnel-etm2/out-ports/port/endpoint";
|
|
funnel_etm2_in_etm2 = "/soc/funnel-etm2/in-ports/port@0/endpoint";
|
|
funnel_etm2_in_uetm2 = "/soc/funnel-etm2/in-ports/port@1/endpoint";
|
|
replicator_ncc0_2 = "/soc/replicator@134b0000";
|
|
replicator_ncc0_2_in_etm2 = "/soc/replicator@134b0000/in-ports/port/endpoint";
|
|
rep_ncc0_2_out_funnel_ncc0_lv1 = "/soc/replicator@134b0000/out-ports/port@0/endpoint";
|
|
etm3_out_funnel_etm3 = "/soc/etm@12f21000/out-ports/port/endpoint";
|
|
uetm3_out_funnel_etm3 = "/soc/uetm3/out-ports/port/endpoint";
|
|
etm3_out_replicator_ncc0_3 = "/soc/funnel-etm3/out-ports/port/endpoint";
|
|
funnel_etm3_in_etm3 = "/soc/funnel-etm3/in-ports/port@0/endpoint";
|
|
funnel_etm3_in_uetm3 = "/soc/funnel-etm3/in-ports/port@1/endpoint";
|
|
replicator_ncc0_3 = "/soc/replicator@134c0000";
|
|
replicator_ncc0_3_in_etm3 = "/soc/replicator@134c0000/in-ports/port/endpoint";
|
|
rep_ncc0_3_out_funnel_ncc0_lv1 = "/soc/replicator@134c0000/out-ports/port@0/endpoint";
|
|
etm4_out_funnel_etm4 = "/soc/etm@13021000/out-ports/port/endpoint";
|
|
uetm4_out_funnel_etm4 = "/soc/uetm4/out-ports/port/endpoint";
|
|
etm4_out_replicator_ncc0_4 = "/soc/funnel-etm4/out-ports/port/endpoint";
|
|
funnel_etm4_in_etm4 = "/soc/funnel-etm4/in-ports/port@0/endpoint";
|
|
funnel_etm4_in_uetm4 = "/soc/funnel-etm4/in-ports/port@1/endpoint";
|
|
replicator_ncc0_4 = "/soc/replicator@134d0000";
|
|
replicator_ncc0_4_in_etm4 = "/soc/replicator@134d0000/in-ports/port/endpoint";
|
|
rep_ncc0_4_out_funnel_ncc0_lv1 = "/soc/replicator@134d0000/out-ports/port@0/endpoint";
|
|
etm5_out_funnel_etm5 = "/soc/etm@13121000/out-ports/port/endpoint";
|
|
uetm5_out_funnel_etm5 = "/soc/uetm5/out-ports/port/endpoint";
|
|
etm5_out_replicator_ncc0_5 = "/soc/funnel-etm5/out-ports/port/endpoint";
|
|
funnel_etm5_in_etm5 = "/soc/funnel-etm5/in-ports/port@0/endpoint";
|
|
funnel_etm5_in_uetm5 = "/soc/funnel-etm5/in-ports/port@1/endpoint";
|
|
replicator_ncc0_5 = "/soc/replicator@134e0000";
|
|
replicator_ncc0_5_in_etm5 = "/soc/replicator@134e0000/in-ports/port/endpoint";
|
|
rep_ncc0_5_out_funnel_ncc0_lv1 = "/soc/replicator@134e0000/out-ports/port@0/endpoint";
|
|
funnel_ncc0_lv1 = "/soc/funnel@13481000";
|
|
funnel_ncc0_lv1_in_rep_ncc0_0 = "/soc/funnel@13481000/in-ports/port@0/endpoint";
|
|
funnel_ncc0_lv1_in_rep_ncc0_1 = "/soc/funnel@13481000/in-ports/port@1/endpoint";
|
|
funnel_ncc0_lv1_in_rep_ncc0_2 = "/soc/funnel@13481000/in-ports/port@2/endpoint";
|
|
funnel_ncc0_lv1_in_rep_ncc0_3 = "/soc/funnel@13481000/in-ports/port@3/endpoint";
|
|
funnel_ncc0_lv1_in_rep_ncc0_4 = "/soc/funnel@13481000/in-ports/port@4/endpoint";
|
|
funnel_ncc0_lv1_in_rep_ncc0_5 = "/soc/funnel@13481000/in-ports/port@5/endpoint";
|
|
funnel_ncc0_lv1_out_funnel_ncc0_lv2 = "/soc/funnel@13481000/out-ports/port/endpoint";
|
|
uetm_uc0_out_etf_uc0 = "/soc/uc_uetm0/out-ports/port/endpoint";
|
|
uc0_etf = "/soc/tmc@13408000";
|
|
etf_uc0_in_uetm_uc0 = "/soc/tmc@13408000/in-ports/port/endpoint";
|
|
etf_uc0_out_replicator_uc0 = "/soc/tmc@13408000/out-ports/port/endpoint";
|
|
replicator_uc0 = "/soc/replicator@1340a000";
|
|
replicator_uc0_in_etf_uc0 = "/soc/replicator@1340a000/in-ports/port/endpoint";
|
|
rep_uc0_out_funnel_ncc0_lv2 = "/soc/replicator@1340a000/out-ports/port@0/endpoint";
|
|
funnel_ncc0_lv2 = "/soc/funnel@13401000";
|
|
funnel_ncc0_lv2_in_rep_uc0 = "/soc/funnel@13401000/in-ports/port@1/endpoint";
|
|
funnel_ncc0_lv2_in_funnel_ncc0_lv1 = "/soc/funnel@13401000/in-ports/port@2/endpoint";
|
|
funnel_ncc0_lv2_out_apss_etf = "/soc/funnel@13401000/out-ports/port/endpoint";
|
|
ncc_etf = "/soc/tmc@13409000";
|
|
apss_etf_in_funnel_ncc0_lv2 = "/soc/tmc@13409000/in-ports/port/endpoint";
|
|
apss_etf_out_funnel_apss = "/soc/tmc@13409000/out-ports/port/endpoint";
|
|
etm6_out_funnel_etm6 = "/soc/etm@13521000/out-ports/port/endpoint";
|
|
uetm6_out_funnel_etm6 = "/soc/uetm6/out-ports/port/endpoint";
|
|
etm6_out_replicator_ncc1_0 = "/soc/funnel-etm6/out-ports/port/endpoint";
|
|
funnel_etm6_in_etm6 = "/soc/funnel-etm6/in-ports/port@0/endpoint";
|
|
funnel_etm6_in_uetm6 = "/soc/funnel-etm6/in-ports/port@1/endpoint";
|
|
replicator_ncc1_0 = "/soc/replicator@13d90000";
|
|
replicator_ncc1_0_in_etm6 = "/soc/replicator@13d90000/in-ports/port/endpoint";
|
|
rep_ncc1_0_out_funnel_ncc1_lv1 = "/soc/replicator@13d90000/out-ports/port@0/endpoint";
|
|
etm7_out_funnel_etm7 = "/soc/etm@13621000/out-ports/port/endpoint";
|
|
uetm7_out_funnel_etm7 = "/soc/uetm7/out-ports/port/endpoint";
|
|
etm7_out_replicator_ncc1_1 = "/soc/funnel-etm7/out-ports/port/endpoint";
|
|
funnel_etm7_in_etm7 = "/soc/funnel-etm7/in-ports/port@0/endpoint";
|
|
funnel_etm7_in_uetm7 = "/soc/funnel-etm7/in-ports/port@1/endpoint";
|
|
replicator_ncc1_1 = "/soc/replicator@13da0000";
|
|
replicator_ncc1_1_in_etm7 = "/soc/replicator@13da0000/in-ports/port/endpoint";
|
|
rep_ncc1_1_out_funnel_ncc1_lv1 = "/soc/replicator@13da0000/out-ports/port@0/endpoint";
|
|
funnel_ncc1_lv1 = "/soc/funnel@13d81000";
|
|
funnel_ncc1_lv1_in_rep_ncc1_0 = "/soc/funnel@13d81000/in-ports/port@0/endpoint";
|
|
funnel_ncc1_lv1_in_rep_ncc1_1 = "/soc/funnel@13d81000/in-ports/port@1/endpoint";
|
|
funnel_ncc1_lv1_out_funnel_ncc1_lv2 = "/soc/funnel@13d81000/out-ports/port/endpoint";
|
|
uetm_uc1_out_etf_uc1 = "/soc/uc_uetm1/out-ports/port/endpoint";
|
|
uc1_etf = "/soc/tmc@13d08000";
|
|
etf_uc1_in_uetm_uc1 = "/soc/tmc@13d08000/in-ports/port/endpoint";
|
|
etf_uc1_out_replicator_uc1 = "/soc/tmc@13d08000/out-ports/port/endpoint";
|
|
replicator_uc1 = "/soc/replicator@13d0a000";
|
|
replicator_uc1_in_etf_uc1 = "/soc/replicator@13d0a000/in-ports/port/endpoint";
|
|
rep_uc1_out_funnel_ncc1_lv2 = "/soc/replicator@13d0a000/out-ports/port@0/endpoint";
|
|
funnel_ncc1_lv2 = "/soc/funnel@13d01000";
|
|
funnel_ncc1_lv2_in_rep_uc1 = "/soc/funnel@13d01000/in-ports/port@1/endpoint";
|
|
funnel_ncc1_lv2_in_funnel_ncc1_lv1 = "/soc/funnel@13d01000/in-ports/port@2/endpoint";
|
|
funnel_ncc1_lv2_out_apss_etf = "/soc/funnel@13d01000/out-ports/port/endpoint";
|
|
apss_etf_in_funnel_ncc1_lv2 = "/soc/tmc@13d09000/in-ports/port/endpoint";
|
|
apss_etf1_out_funnel_apss = "/soc/tmc@13d09000/out-ports/port/endpoint";
|
|
funnel_apss = "/soc/funnel@12080000";
|
|
funnel_apss_in_apss_etf = "/soc/funnel@12080000/in-ports/port@0/endpoint";
|
|
funnel_apss_in_apss_etf1 = "/soc/funnel@12080000/in-ports/port@1/endpoint";
|
|
funnel_apss_in_tpda_apss = "/soc/funnel@12080000/in-ports/port@5/endpoint";
|
|
funnel_apss_out_tn_ag = "/soc/funnel@12080000/out-ports/port/endpoint";
|
|
tpdm_ddr_lpi = "/soc/tpdm@10b34000";
|
|
tpdm_ddr_lpi_out_funnel_aoss = "/soc/tpdm@10b34000/out-ports/port@0/endpoint";
|
|
ddr_lpi_out_qmi = "/soc/tpdm@10b34000/out-ports/port@1/endpoint";
|
|
tpdm_ubwcp = "/soc/tpdm@10f80000";
|
|
tpdm_ddr_ubwcp_out_tn_ddr = "/soc/tpdm@10f80000/out-ports/port/endpoint";
|
|
tpdm_ddr_llcc0 = "/soc/tpdm@10f82000";
|
|
tpdm_ddr_llcc0_out_tn_ddr = "/soc/tpdm@10f82000/out-ports/port/endpoint";
|
|
tpdm_ddr_llcc1 = "/soc/tpdm@10f84000";
|
|
tpdm_ddr_llcc1_out_tn_ddr = "/soc/tpdm@10f84000/out-ports/port/endpoint";
|
|
tpdm_ddr_llcc2 = "/soc/tpdm@10f83000";
|
|
tpdm_ddr_llcc2_out_tn_ddr = "/soc/tpdm@10f83000/out-ports/port/endpoint";
|
|
tpdm_ddr_llcc3 = "/soc/tpdm@10f85000";
|
|
tpdm_ddr_llcc3_out_tn_ddr = "/soc/tpdm@10f85000/out-ports/port/endpoint";
|
|
tpdm_ddr_dpm = "/soc/tpdm@10d04000";
|
|
tpdm_ddr_dpm_out_tn_ddr = "/soc/tpdm@10d04000/out-ports/port/endpoint";
|
|
tpdm_ddr_shrm = "/soc/tpdm@10d03000";
|
|
tpdm_ddr_shrm_out_tn_ddr = "/soc/tpdm@10d03000/out-ports/port/endpoint";
|
|
tpdm_ddr_ch02 = "/soc/tpdm@10d06000";
|
|
tpdm_ddr_ch02_out_tn_ddr = "/soc/tpdm@10d06000/out-ports/port/endpoint";
|
|
tpdm_ddr_ch13 = "/soc/tpdm@10d08000";
|
|
tpdm_ddr_ch13_out_tn_ddr = "/soc/tpdm@10d08000/out-ports/port/endpoint";
|
|
gladiator_out_tn_ddr = "/soc/gladiator/out-ports/port/endpoint";
|
|
ddr_tn = "/soc/TN@10d00000";
|
|
tn_ddr_in_gladiator = "/soc/TN@10d00000/in-ports/port@6/endpoint";
|
|
tn_ddr_in_tpdm_ddr_ubwcp = "/soc/TN@10d00000/in-ports/port@8/endpoint";
|
|
tn_ddr_in_tpdm_ddr_llcc0 = "/soc/TN@10d00000/in-ports/port@9/endpoint";
|
|
tn_ddr_in_tpdm_ddr_llcc1 = "/soc/TN@10d00000/in-ports/port@a/endpoint";
|
|
tn_ddr_in_tpdm_ddr_llcc2 = "/soc/TN@10d00000/in-ports/port@b/endpoint";
|
|
tn_ddr_in_tpdm_ddr_llcc3 = "/soc/TN@10d00000/in-ports/port@c/endpoint";
|
|
tn_ddr_in_tpdm_ddr_dpm = "/soc/TN@10d00000/in-ports/port@d/endpoint";
|
|
tn_ddr_in_tpdm_ddr_shrm = "/soc/TN@10d00000/in-ports/port@e/endpoint";
|
|
tn_ddr_in_tpdm_ddr_ch02 = "/soc/TN@10d00000/in-ports/port@f/endpoint";
|
|
tn_ddr_in_tpdm_ddr_ch13 = "/soc/TN@10d00000/in-ports/port@10/endpoint";
|
|
tn_ddr_out_tn_ag = "/soc/TN@10d00000/out-ports/port/endpoint";
|
|
audio_etm0_out_funnel_lpass_lpi = "/soc/audio_etm0/out-ports/port@0/endpoint";
|
|
audio_etm0_out_qmi = "/soc/audio_etm0/out-ports/port@1/endpoint";
|
|
tpdm_lpass_lpi = "/soc/tpdm@10b46000";
|
|
tpdm_lpass_lpi_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b46000/out-ports/port@0/endpoint";
|
|
lpass_lpi_out_qmi = "/soc/tpdm@10b46000/out-ports/port@1/endpoint";
|
|
tpdm_lpass_rscc = "/soc/tpdm@10b52000";
|
|
tpdm_lpass_rscc_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b52000/out-ports/port@0/endpoint";
|
|
lpass_rscc_out_qmi = "/soc/tpdm@10b52000/out-ports/port@1/endpoint";
|
|
tpdm_lpass_audio = "/soc/tpdm@10b54000";
|
|
tpdm_lpass_audio_out_funnel_lpass_lpi_1 = "/soc/tpdm@10b54000/out-ports/port@0/endpoint";
|
|
lpass_audio_out_qmi = "/soc/tpdm@10b54000/out-ports/port@1/endpoint";
|
|
tpdm_lpass_crdl = "/soc/tpdm@10bb4000";
|
|
tpdm_lpass_crdl_out_tn_lpass = "/soc/tpdm@10bb4000/out-ports/port/endpoint";
|
|
tn_lpass = "/soc/TN@10b80000";
|
|
tn_lpass_in_tpdm_lpass_crdl = "/soc/TN@10b80000/in-ports/port@0/endpoint";
|
|
tn_lpass_out_tn_ag = "/soc/TN@10b80000/out-ports/port/endpoint";
|
|
lpass_stm = "/soc/lpass-stm";
|
|
lpass_stm_out_funnel_lpass_lpi_1 = "/soc/lpass-stm/out-ports/port@0/endpoint";
|
|
lpass_stm_out_qmi = "/soc/lpass-stm/out-ports/port@1/endpoint";
|
|
funnel_lpass_lpi_1 = "/soc/funnel@10b50000";
|
|
funnel_lpass_lpi_1_in_lpass_stm = "/soc/funnel@10b50000/in-ports/port@0/endpoint";
|
|
funnel_lpass_lpi_1_in_tpdm_lpass_lpi = "/soc/funnel@10b50000/in-ports/port@1/endpoint";
|
|
funnel_lpass_lpi_1_in_tpdm_lpass_rscc = "/soc/funnel@10b50000/in-ports/port@4/endpoint";
|
|
funnel_lpass_lpi_1_in_tpdm_lpass_audio = "/soc/funnel@10b50000/in-ports/port@5/endpoint";
|
|
funnel_lpass_lpi_1_out_funnel_lpass_lpi_0 = "/soc/funnel@10b50000/out-ports/port/endpoint";
|
|
funnel_lpass_lpi_0 = "/soc/funnel@10b44000";
|
|
funnel_lpass_lpi_in_audio_etm0 = "/soc/funnel@10b44000/in-ports/port@0/endpoint";
|
|
funnel_lpass_lpi_0_in_funnel_lpass_lpi_1 = "/soc/funnel@10b44000/in-ports/port@7/endpoint";
|
|
funnel_lpass_lpi_out_funnel_aoss = "/soc/funnel@10b44000/out-ports/port/endpoint";
|
|
stm = "/soc/stm@10002000";
|
|
stm_out_funnel_in0 = "/soc/stm@10002000/out-ports/port/endpoint";
|
|
tpdm_dcc = "/soc/tpdm@10003000";
|
|
tpdm_dcc_out_tpda_qdss = "/soc/tpdm@10003000/out-ports/port/endpoint";
|
|
tpdm_ufs = "/soc/tpdm@10c23000";
|
|
tpdm_ufs_out_tn_ag = "/soc/tpdm@10c23000/out-ports/port/endpoint";
|
|
tpdm_sdcc5_4 = "/soc/tpdm@10c21000";
|
|
tpdm_sdcc5_4_out_tn_ag = "/soc/tpdm@10c21000/out-ports/port/endpoint";
|
|
tpdm_sdcc5_2 = "/soc/tpdm@10c20000";
|
|
tpdm_sdcc5_2_out_tn_ag = "/soc/tpdm@10c20000/out-ports/port/endpoint";
|
|
tpdm_ipa = "/soc/tpdm@10c22000";
|
|
tpdm_ipa_out_tn_ag = "/soc/tpdm@10c22000/out-ports/port/endpoint";
|
|
tpdm_vsense = "/soc/tpdm@10840000";
|
|
tpdm_vsense_out_tn_ag = "/soc/tpdm@10840000/out-ports/port/endpoint";
|
|
tpdm_qm = "/soc/tpdm@109d0000";
|
|
tpdm_qm_out_tn_ag = "/soc/tpdm@109d0000/out-ports/port/endpoint";
|
|
tpdm_prng = "/soc/tpdm@10841000";
|
|
tpdm_prng_out_tn_ag = "/soc/tpdm@10841000/out-ports/port/endpoint";
|
|
tpdm_gcc = "/soc/tpdm@1082c000";
|
|
tpdm_gcc_out_tn_ag = "/soc/tpdm@1082c000/out-ports/port/endpoint";
|
|
tpdm_dl_mm = "/soc/tpdm@109a5000";
|
|
tpdm_dl_mm_out_tn_ag = "/soc/tpdm@109a5000/out-ports/port/endpoint";
|
|
tpdm_north = "/soc/tpdm@109a6000";
|
|
tpdm_north_dsb_out_tn_ag = "/soc/tpdm@109a6000/out-ports/port/endpoint";
|
|
tpdm_south = "/soc/tpdm@109a7000";
|
|
tpdm_south_dsb_out_tn_ag = "/soc/tpdm@109a7000/out-ports/port/endpoint";
|
|
tpdm_ipcc_cmb = "/soc/tpdm@109a4000";
|
|
tpdm_ipcc_cmb_out_tn_ag = "/soc/tpdm@109a4000/out-ports/port/endpoint";
|
|
tpdm_pmu = "/soc/tpdm@109a3000";
|
|
tpdm_pmu_out_tn_ag = "/soc/tpdm@109a3000/out-ports/port/endpoint";
|
|
tpdm_rdpm_cmb0 = "/soc/tpdm@109a8000";
|
|
tpdm_rdpm_cmb0_out_tn_ag = "/soc/tpdm@109a8000/out-ports/port/endpoint";
|
|
tpdm_rdpm_cmb1 = "/soc/tpdm@109a9000";
|
|
tpdm_rdpm_cmb1_out_tn_ag = "/soc/tpdm@109a9000/out-ports/port/endpoint";
|
|
tpdm_rdpm_cmb2 = "/soc/tpdm@109aa000";
|
|
tpdm_rdpm_cmb2_out_tn_ag = "/soc/tpdm@109aa000/out-ports/port/endpoint";
|
|
tn_ag = "/soc/tn@109ab000";
|
|
tn_ag_in_tpda_mm = "/soc/tn@109ab000/in-ports/port@4/endpoint";
|
|
tn_ag_in_tpda_pcie = "/soc/tn@109ab000/in-ports/port@8/endpoint";
|
|
tn_ag_in_funnel_spss = "/soc/tn@109ab000/in-ports/port@9/endpoint";
|
|
tn_ag_in_tn_titan = "/soc/tn@109ab000/in-ports/port@b/endpoint";
|
|
tn_ag_in_funnel_tmess = "/soc/tn@109ab000/in-ports/port@c/endpoint";
|
|
tn_ag_in_funnel_modem_dl = "/soc/tn@109ab000/in-ports/port@d/endpoint";
|
|
tn_ag_in_funnel_dlmm = "/soc/tn@109ab000/in-ports/port@e/endpoint";
|
|
tn_ag_in_funnel_dlet = "/soc/tn@109ab000/in-ports/port@f/endpoint";
|
|
tn_ag_in_funnel_turing = "/soc/tn@109ab000/in-ports/port@10/endpoint";
|
|
tn_ag_in_tpdm_gcc = "/soc/tn@109ab000/in-ports/port@11/endpoint";
|
|
tn_ag_in_tpdm_prng = "/soc/tn@109ab000/in-ports/port@12/endpoint";
|
|
tn_ag_in_tpdm_qm = "/soc/tn@109ab000/in-ports/port@13/endpoint";
|
|
tn_ag_in_tpdm_vsense = "/soc/tn@109ab000/in-ports/port@14/endpoint";
|
|
tn_ag_in_tpdm_ipa = "/soc/tn@109ab000/in-ports/port@15/endpoint";
|
|
tn_ag_in_tpdm_sdcc5_2 = "/soc/tn@109ab000/in-ports/port@16/endpoint";
|
|
tn_ag_in_tpdm_sdcc5_4 = "/soc/tn@109ab000/in-ports/port@17/endpoint";
|
|
tn_ag_in_tpdm_ufs = "/soc/tn@109ab000/in-ports/port@18/endpoint";
|
|
tn_ag_in_tpdm_dl_mm = "/soc/tn@109ab000/in-ports/port@19/endpoint";
|
|
tn_ag_in_tpdm_north_dsb = "/soc/tn@109ab000/in-ports/port@1a/endpoint";
|
|
tn_ag_in_tpdm_south_dsb = "/soc/tn@109ab000/in-ports/port@1b/endpoint";
|
|
tn_ag_in_tpdm_ipcc_cmb = "/soc/tn@109ab000/in-ports/port@1c/endpoint";
|
|
tn_ag_in_tpdm_pmu = "/soc/tn@109ab000/in-ports/port@1d/endpoint";
|
|
tn_ag_in_tpdm_rdpm_cmb0 = "/soc/tn@109ab000/in-ports/port@1e/endpoint";
|
|
tn_ag_in_tpdm_rdpm_cmb1 = "/soc/tn@109ab000/in-ports/port@1f/endpoint";
|
|
tn_ag_in_tpdm_rdpm_cmb2 = "/soc/tn@109ab000/in-ports/port@20/endpoint";
|
|
tn_ag_in_funnel_apss = "/soc/tn@109ab000/in-ports/port@21/endpoint";
|
|
tn_ag_in_tn_ddr = "/soc/tn@109ab000/in-ports/port@22/endpoint";
|
|
tn_ag_in_tn_lpass = "/soc/tn@109ab000/in-ports/port@23/endpoint";
|
|
tn_ag_in_tn_soccp = "/soc/tn@109ab000/in-ports/port@24/endpoint";
|
|
tn_ag_out_funnel_in0 = "/soc/tn@109ab000/out-ports/port/endpoint";
|
|
tpdm_spdm = "/soc/tpdm@1000f000";
|
|
tpdm_spdm_out_tpda_qdss = "/soc/tpdm@1000f000/out-ports/port/endpoint";
|
|
tpda_qdss = "/soc/tpda@10004000";
|
|
tpda_qdss_in_tpdm_dcc = "/soc/tpda@10004000/in-ports/port@0/endpoint";
|
|
tpda_qdss_in_tpdm_spdm = "/soc/tpda@10004000/in-ports/port@1/endpoint";
|
|
tpda_qdss_out_funnel_in0 = "/soc/tpda@10004000/out-ports/port/endpoint";
|
|
funnel_in0 = "/soc/funnel@10041000";
|
|
funnel_in0_in_tn_ag = "/soc/funnel@10041000/in-ports/port@0/endpoint";
|
|
funnel_in0_in_tpda_qdss = "/soc/funnel@10041000/in-ports/port@6/endpoint";
|
|
funnel_in0_in_stm = "/soc/funnel@10041000/in-ports/port@7/endpoint";
|
|
funnel_in0_out_funnel_aoss = "/soc/funnel@10041000/out-ports/port/endpoint";
|
|
tpdm_swao_prio0 = "/soc/tpdm@10b09000";
|
|
tpdm_swao_prio0_out_tpda_aoss = "/soc/tpdm@10b09000/out-ports/port/endpoint";
|
|
tpdm_swao_prio1 = "/soc/tpdm@10b0a000";
|
|
tpdm_swao_prio1_out_tpda_aoss = "/soc/tpdm@10b0a000/out-ports/port/endpoint";
|
|
tpdm_swao_prio2 = "/soc/tpdm@10b0b000";
|
|
tpdm_swao_prio2_out_tpda_aoss = "/soc/tpdm@10b0b000/out-ports/port/endpoint";
|
|
tpdm_swao_prio3 = "/soc/tpdm@10b0c000";
|
|
tpdm_swao_prio3_out_tpda_aoss = "/soc/tpdm@10b0c000/out-ports/port/endpoint";
|
|
tpdm_swao = "/soc/tpdm@10b0d000";
|
|
tpdm_swao_out_tpda_aoss = "/soc/tpdm@10b0d000/out-ports/port/endpoint";
|
|
tpda_aoss = "/soc/tpda@10b08000";
|
|
tpda_aoss_in_tpdm_swao_prio0 = "/soc/tpda@10b08000/in-ports/port@0/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio1 = "/soc/tpda@10b08000/in-ports/port@1/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio2 = "/soc/tpda@10b08000/in-ports/port@2/endpoint";
|
|
tpda_aoss_in_tpdm_swao_prio3 = "/soc/tpda@10b08000/in-ports/port@3/endpoint";
|
|
tpda_aoss_in_tpdm_swao = "/soc/tpda@10b08000/in-ports/port@4/endpoint";
|
|
tpda_aoss_out_funnel_aoss = "/soc/tpda@10b08000/out-ports/port/endpoint";
|
|
funnel_aoss = "/soc/funnel@10b04000";
|
|
funnel_aoss_in_tpdm_ddr_lpi = "/soc/funnel@10b04000/in-ports/port@3/endpoint";
|
|
funnel_aoss_in_funnel_lpass_lpi = "/soc/funnel@10b04000/in-ports/port@5/endpoint";
|
|
funnel_aoss_in_tpda_aoss = "/soc/funnel@10b04000/in-ports/port@6/endpoint";
|
|
funnel_aoss_in_funnel_in0 = "/soc/funnel@10b04000/in-ports/port@7/endpoint";
|
|
funnel_aoss_out_tmc_etf = "/soc/funnel@10b04000/out-ports/port/endpoint";
|
|
tmc_etf = "/soc/tmc@10b05000";
|
|
tmc_etf_in_funnel_aoss = "/soc/tmc@10b05000/in-ports/port/endpoint";
|
|
tmc_etf_out_replicator_swao = "/soc/tmc@10b05000/out-ports/port/endpoint";
|
|
replicator_swao = "/soc/replicator@10b06000";
|
|
replicator_swao_in_tmc_etf = "/soc/replicator@10b06000/in-ports/port/endpoint";
|
|
replicator_swao_out_replicator_qdss = "/soc/replicator@10b06000/out-ports/port@0/endpoint";
|
|
replicator_swao_out_eud = "/soc/replicator@10b06000/out-ports/port@1/endpoint";
|
|
dummy_eud = "/soc/dummy-eud";
|
|
eud_in_replicator_swao = "/soc/dummy-eud/in-ports/port/endpoint";
|
|
replicator_qdss = "/soc/replicator@10046000";
|
|
replicator_qdss_in_replicator_swao = "/soc/replicator@10046000/in-ports/port/endpoint";
|
|
replicator_qdss_out_replicator_etr = "/soc/replicator@10046000/out-ports/port@0/endpoint";
|
|
replicator_etr = "/soc/replicator@1004e000";
|
|
replicator_etr_in_replicator_qdss = "/soc/replicator@1004e000/in-ports/port/endpoint";
|
|
replicator_etr_out_tmc_etr = "/soc/replicator@1004e000/out-ports/port@0/endpoint";
|
|
replicator_etr_out_replicator_dummy = "/soc/replicator@1004e000/out-ports/port@1/endpoint";
|
|
replicator_dummy_in_replicator_etr = "/soc/etr1-replicator/in-ports/port/endpoint";
|
|
replicator_dummy_out_tmc_modem = "/soc/etr1-replicator/out-ports/port@0/endpoint";
|
|
replicator_dummy_out_tmc_etr1 = "/soc/etr1-replicator/out-ports/port@1/endpoint";
|
|
tmc_modem = "/soc/tmc-modem";
|
|
tmc_modem_in_replicator_dummy = "/soc/tmc-modem/in-ports/port/endpoint";
|
|
tmc_modem_out_qmi = "/soc/tmc-modem/out-ports/port/endpoint";
|
|
tmc_etr = "/soc/tmc@10048000";
|
|
tmc_etr_in_replicator_etr = "/soc/tmc@10048000/in-ports/port/endpoint";
|
|
tmc_etr1 = "/soc/tmc@1004f000";
|
|
tmc_etr1_in_replicator_dummy = "/soc/tmc@1004f000/in-ports/port/endpoint";
|
|
qmi_in_turing_etm0 = "/soc/turing-qmi/in-ports/port/endpoint";
|
|
qmi_in_audio_etm0 = "/soc/audio-qmi/in-ports/port@0/endpoint";
|
|
qmi_in_lpass_stm = "/soc/audio-qmi/in-ports/port@1/endpoint";
|
|
qmi_in_lpass_lpi = "/soc/audio-qmi/in-ports/port@2/endpoint";
|
|
qmi_in_lpass_rscc = "/soc/audio-qmi/in-ports/port@3/endpoint";
|
|
qmi_in_lpass_audio = "/soc/audio-qmi/in-ports/port@4/endpoint";
|
|
qmi_in_ddr_lpi = "/soc/audio-qmi/in-ports/port@5/endpoint";
|
|
qmi_in_modem_etm0 = "/soc/modem0-qmi/in-ports/port@0/endpoint";
|
|
qmi_in_tmc_modem = "/soc/modem0-qmi/in-ports/port@1/endpoint";
|
|
qmi_in_modem2_etm0 = "/soc/modem2-qmi/in-ports/port/endpoint";
|
|
swao_cti = "/soc/cti@10b00000";
|
|
dcc = "/soc/dcc@100ff000";
|
|
kgsl_smmu = "/soc/kgsl-smmu@3da0000";
|
|
gpu_qtb = "/soc/kgsl-smmu@3da0000/gpu_qtb@3de8000";
|
|
apps_smmu = "/soc/apps-smmu@15000000";
|
|
anoc_1_qtb = "/soc/apps-smmu@15000000/anoc_1_qtb@16f2000";
|
|
anoc_2_qtb = "/soc/apps-smmu@15000000/anoc_2_qtb@171b000";
|
|
cam_hf_qtb = "/soc/apps-smmu@15000000/cam_hf_qtb@17d2000";
|
|
nsp_qtb = "/soc/apps-smmu@15000000/nsp_qtb@7d3000";
|
|
lpass_qtb = "/soc/apps-smmu@15000000/lpass_qtb@7b3000";
|
|
pcie_qtb = "/soc/apps-smmu@15000000/pcie_qtb@16cd000";
|
|
sf_qtb = "/soc/apps-smmu@15000000/sf_qtb@17d1000";
|
|
mdp_hf_qtb = "/soc/apps-smmu@15000000/mdp_hf_qtb@17d0000";
|
|
qup1_gpi_iommu_region = "/soc/qup1_gpi_iommu_region";
|
|
gpi_dma1 = "/soc/qcom,gpi-dma@a00000";
|
|
qup1_se_iommu_region = "/soc/qup1_se_iommu_region";
|
|
qupv3_1 = "/soc/qcom,qupv3_1_geni_se@ac0000";
|
|
qupv3_se0_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a80000";
|
|
qupv3_se0_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a80000";
|
|
i3c0 = "/soc/qcom,qupv3_1_geni_se@ac0000/i3c-master@a80000";
|
|
qupv3_se1_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a84000";
|
|
qupv3_se1_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a84000";
|
|
i3c1 = "/soc/qcom,qupv3_1_geni_se@ac0000/i3c-master@a84000";
|
|
qupv3_se2_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a88000";
|
|
qupv3_se2_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a88000";
|
|
qupv3_se3_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a8c000";
|
|
wcd_usbss = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a8c000/wcd939x_i2c@e";
|
|
qupv3_se3_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a8c000";
|
|
qupv3_se4_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a90000";
|
|
qupv3_se4_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a90000";
|
|
i3c2 = "/soc/qcom,qupv3_1_geni_se@ac0000/i3c-master@a90000";
|
|
qupv3_se5_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a94000";
|
|
qupv3_se5_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a94000";
|
|
qupv3_se6_i2c = "/soc/qcom,qupv3_1_geni_se@ac0000/i2c@a98000";
|
|
qupv3_se6_spi = "/soc/qcom,qupv3_1_geni_se@ac0000/spi@a98000";
|
|
qupv3_se7_2uart = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000";
|
|
qup2_gpi_iommu_region = "/soc/qup2_gpi_iommu_region";
|
|
gpi_dma2 = "/soc/qcom,gpi-dma@800000";
|
|
qup2_se_iommu_region = "/soc/qup2_se_iommu_region";
|
|
qupv3_2 = "/soc/qcom,qupv3_2_geni_se@8c0000";
|
|
qupv3_se8_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@880000";
|
|
qupv3_se8_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@880000";
|
|
i3c3 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@880000";
|
|
qupv3_se9_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@884000";
|
|
qupv3_se9_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@884000";
|
|
i3c4 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@884000";
|
|
qupv3_se10_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@888000";
|
|
qupv3_se10_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@888000";
|
|
i3c5 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@888000";
|
|
qupv3_se11_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@88c000";
|
|
qupv3_se11_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@88c000";
|
|
i3c6 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@88c000";
|
|
qupv3_se12_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@890000";
|
|
qupv3_se12_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@890000";
|
|
qupv3_se13_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@894000";
|
|
qupv3_se13_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@894000";
|
|
qupv3_se13_q2spi = "/soc/qcom,qupv3_2_geni_se@8c0000/q2spi@894000";
|
|
qupv3_se14_4uart = "/soc/qcom,qupv3_2_geni_se@8c0000/qcom,qup_uart@898000";
|
|
qupv3_se15_i2c = "/soc/qcom,qupv3_2_geni_se@8c0000/i2c@89c000";
|
|
qupv3_se15_spi = "/soc/qcom,qupv3_2_geni_se@8c0000/spi@89c000";
|
|
i3c7 = "/soc/qcom,qupv3_2_geni_se@8c0000/i3c-master@89c000";
|
|
qupv3_0_i2c_hub = "/soc/qcom,qupv3_i2c_geni_se@9c0000";
|
|
qupv3_hub_i2c0 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@980000";
|
|
qupv3_hub_i2c1 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@984000";
|
|
qupv3_hub_i2c2 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@988000";
|
|
qupv3_hub_i2c3 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@98c000";
|
|
qupv3_hub_i2c4 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@990000";
|
|
qupv3_hub_i2c5 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@994000";
|
|
qupv3_hub_i2c6 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@998000";
|
|
qupv3_hub_i2c7 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@99c000";
|
|
qupv3_hub_i2c8 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@9a0000";
|
|
qupv3_hub_i2c9 = "/soc/qcom,qupv3_i2c_geni_se@9c0000/i2c@9a4000";
|
|
usb0 = "/soc/ssusb@a600000";
|
|
dwc3_0 = "/soc/ssusb@a600000/dwc3@a600000";
|
|
dwc3_mem_region = "/soc/dwc3_mem_region";
|
|
eusb2_phy0 = "/soc/hsphy@88e3000";
|
|
usb_qmp_dp_phy = "/soc/ssphy@88e8000";
|
|
tsens0 = "/soc/tsens0@c228000";
|
|
tsens1 = "/soc/tsens1@c229000";
|
|
tsens2 = "/soc/tsens2@c22a000";
|
|
tsens3 = "/soc/tsens3@c22b000";
|
|
cpu0_pause = "/soc/qcom,cpu-pause/cpu0-pause";
|
|
cpu1_pause = "/soc/qcom,cpu-pause/cpu1-pause";
|
|
cpu2_pause = "/soc/qcom,cpu-pause/cpu2-pause";
|
|
cpu3_pause = "/soc/qcom,cpu-pause/cpu3-pause";
|
|
cpu4_pause = "/soc/qcom,cpu-pause/cpu4-pause";
|
|
cpu5_pause = "/soc/qcom,cpu-pause/cpu5-pause";
|
|
cpu6_pause = "/soc/qcom,cpu-pause/cpu6-pause";
|
|
cpu7_pause = "/soc/qcom,cpu-pause/cpu7-pause";
|
|
APC0_MX_CX_PAUSE = "/soc/qcom,cpu-pause/apc0-mx-cx-pause";
|
|
APC1_MX_CX_PAUSE = "/soc/qcom,cpu-pause/apc1-mx-cx-pause";
|
|
cpu0_hotplug = "/soc/qcom,cpu-hotplug/cpu0-hotplug";
|
|
cpu1_hotplug = "/soc/qcom,cpu-hotplug/cpu1-hotplug";
|
|
cpu2_hotplug = "/soc/qcom,cpu-hotplug/cpu2-hotplug";
|
|
cpu3_hotplug = "/soc/qcom,cpu-hotplug/cpu3-hotplug";
|
|
cpu4_hotplug = "/soc/qcom,cpu-hotplug/cpu4-hotplug";
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cpu5_hotplug = "/soc/qcom,cpu-hotplug/cpu5-hotplug";
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cpu6_hotplug = "/soc/qcom,cpu-hotplug/cpu6-hotplug";
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cpu7_hotplug = "/soc/qcom,cpu-hotplug/cpu7-hotplug";
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thermal_ddr_freq_table = "/soc/thermal-ddr-freq-table";
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ddr_cdev = "/soc/qcom,ddr-cdev";
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qmi_tmd = "/soc/qmi-tmd-devices";
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cdsp_sw = "/soc/qmi-tmd-devices/cdsp/cdsp";
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cdsp_sw_hvx = "/soc/qmi-tmd-devices/cdsp/cdsp_sw_hvx";
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cdsp_sw_hmx = "/soc/qmi-tmd-devices/cdsp/cdsp_sw_hmx";
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cdsp_hw = "/soc/qmi-tmd-devices/cdsp/cdsp_hw";
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modem_lte_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_dsc";
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modem_nr_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_dsc";
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modem_nr_scg_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_dsc";
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modem_lte_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_lte_sub1_dsc";
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modem_nr_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_sub1_dsc";
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modem_nr_scg_sub1_dsc = "/soc/qmi-tmd-devices/modem/modem_nr_scg_sub1_dsc";
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pa_lte_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_dsc";
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pa_nr_sdr0_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_dsc";
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pa_nr_sdr0_scg_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_scg_dsc";
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pa_lte_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_lte_sdr0_sub1_dsc";
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pa_nr_sdr0_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_sub1_dsc";
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pa_nr_sdr0_scg_sub1_dsc = "/soc/qmi-tmd-devices/modem/pa_nr_sdr0_scg_sub1_dsc";
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mmw0_dsc = "/soc/qmi-tmd-devices/modem/mmw0_dsc";
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mmw1_dsc = "/soc/qmi-tmd-devices/modem/mmw1_dsc";
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mmw2_dsc = "/soc/qmi-tmd-devices/modem/mmw2_dsc";
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mmw3_dsc = "/soc/qmi-tmd-devices/modem/mmw3_dsc";
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mmw0_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw0_sub1_dsc";
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mmw1_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw1_sub1_dsc";
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mmw2_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw2_sub1_dsc";
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mmw3_sub1_dsc = "/soc/qmi-tmd-devices/modem/mmw3_sub1_dsc";
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modem_vdd = "/soc/qmi-tmd-devices/modem/modem_vdd";
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modem_bcl = "/soc/qmi-tmd-devices/modem/modem_bcl";
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display_fps = "/soc/qcom,userspace-cdev/display-fps";
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limits_stat = "/soc/limits-stat";
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qmi_sensor = "/soc/qmi-ts-sensors";
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pcie0 = "/soc/pcie@1c00000";
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pcie0_rp = "/soc/pcie@1c00000/pcie0_rp";
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pcie0_msi = "/soc/qcom,pcie0_msi@16110040";
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ipcc_self_ping_apss = "/soc/ipcc-self-ping-apss";
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hypervisor = "/hypervisor";
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gh_watchdog = "/hypervisor/qcom,gh-watchdog";
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sched_walt = "/sched_walt";
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|
};
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|
};
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