53765c8d58
This change adds the entries of qusb phys and usb bam in yaml format. Change-Id: I5697f28cf786ab6cc61c462a164ff4b0e4e68aac Signed-off-by: Rajkumar Patel <quic_rajkpate@quicinc.com>
229 lines
6.0 KiB
YAML
229 lines
6.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/qcom,qusb2phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Qualcomm USB Phy
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maintainers:
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- Udipto Goswami <quic_ugoswami@quicinc.com>
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properties:
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compatible:
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enum:
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- qcom,qusb2phy
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- qcom,qusb2phy-v2
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reg:
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description: Address and length of the registers set for the phy.
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minItems: 1
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maxItems: 7
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reg-names:
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minItems: 1
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items:
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- const: qusb_phy_base
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- const: eud_enable_reg
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- const: efuse_addr
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- const: refgen_north_bg_reg_addr
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qcom,efuse-bit-pos:
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description: External fuse register bit required for phy functionality.
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$ref: /schemas/types.yaml#/definitions/uint32
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qcom,efuse-num-bits:
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description: External fuse register number of bit to be read.
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vdd-supply:
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description: vdd supply for HSPHY digital circuit operation.
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vdda18-supply:
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description: 1.8 V for HSPHY.
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vdda33-supply:
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description: 3.3 V for HSPHY.
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refgen-supply:
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description: Refgen regulator required for phy to work.
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qcom,vdd-voltage-level:
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description: Voltage level of the vdd supply.
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This is set to min value to vote from usb.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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clocks:
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description: |
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A list of phandles to the phy clocks::
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- ref_clk_src:: Reference clk source required for enumeration.
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- ref_clk:: Reference clk required for enumeration.
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minItems: 1
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maxItems: 3
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clock-names:
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minItems: 1
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items:
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- const: ref_clk_src
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- const: ref_clk
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: phy_reset
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phy_type:
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oneOf:
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- items:
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- const: utmi
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- items:
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- const: ulpi
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qcom,qusb-phy-init-seq:
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description: Phy Initialization sequence required for init.
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items:
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items:
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-
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description: address
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-
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description: value
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qcom,qusb-phy-reg-offset:
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description: Phy Register offsets required for probe.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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-
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description: address
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qcom,qusb-phy-host-init-seq:
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description: Host mode phy initialization sequence required for init.
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items:
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items:
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-
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description: address
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-
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description: value
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if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qusb2phy-v2
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then:
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required:
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- qcom,qusb-phy-reg-offset
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- qcom,qusb-phy-host-init-seq
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else:
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properties:
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qcom,qusb-phy-reg-offset: false
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qcom,qusb-phy-host-init-seq: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- vdd-supply
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- vdda18-supply
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- vdda33-supply
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- resets
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- phy_type
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- qcom,qusb-phy-init-seq
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-holi.h>
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qusb2_phy0: qusb@162b000 {
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compatible = "qcom,qusb2phy-v2";
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reg = <0x162B000 0x114>,
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<0x0162A000 0x1000>,
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<0x1b40268 0x4>,
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<0x0162f014 0x4>;
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reg-names = "qusb_phy_base",
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"eud_enable_reg",
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"efuse_addr",
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"refgen_north_bg_reg_addr";
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qcom,efuse-bit-pos = <25>;
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qcom,efuse-num-bits = <3>;
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vdd-supply = <&L18A>;
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vdda18-supply = <&L2A>;
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vdda33-supply = <&L3A>;
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refgen-supply = <&L22A>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "ref_clk_src", "ref_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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phy_type= "utmi";
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qcom,qusb-phy-reg-offset =
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<0x240 /* QUSB2PHY_PORT_TUNE1 */
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0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
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0x210 /* QUSB2PHY_PWR_CTRL1 */
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0x230 /* QUSB2PHY_INTR_CTRL */
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0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
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0x254 /* QUSB2PHY_TEST1 */
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0x198 /* PLL_BIAS_CONTROL_2 */
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0x27c /* QUSB2PHY_DEBUG_CTRL1 */
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0x280 /* QUSB2PHY_DEBUG_CTRL2 */
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0x284 /* QUSB2PHY_DEBUG_CTRL3 */
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0x288 /* QUSB2PHY_DEBUG_CTRL4 */
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0x2a0>; /* QUSB2PHY_STAT5 */
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qcom,qusb-phy-init-seq =
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/* <value reg_offset> */
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<0x23 0x210 /* PWR_CTRL1 */
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0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
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0x7c 0x18c /* PLL_CLOCK_INVERTERS */
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0x80 0x2c /* PLL_CMODE */
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0x0a 0x184 /* PLL_LOCK_DELAY */
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0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
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0x40 0x194 /* PLL_BIAS_CONTROL_1 */
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0x22 0x198 /* PLL_BIAS_CONTROL_2 */
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0x21 0x214 /* PWR_CTRL2 */
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0x08 0x220 /* IMP_CTRL1 */
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0x58 0x224 /* IMP_CTRL2 */
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0x45 0x240 /* TUNE1 */
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0x29 0x244 /* TUNE2 */
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0xca 0x248 /* TUNE3 */
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0x04 0x24c /* TUNE4 */
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0x03 0x250 /* TUNE5 */
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0x30 0x23c /* CHG_CTRL2 */
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0x22 0x210>; /* PWR_CTRL1 */
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qcom,qusb-phy-host-init-seq =
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/* <value reg_offset> */
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<0x23 0x210 /* PWR_CTRL1 */
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0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
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0x7c 0x18c /* PLL_CLOCK_INVERTERS */
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0x80 0x2c /* PLL_CMODE */
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0x0a 0x184 /* PLL_LOCK_DELAY */
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0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
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0x40 0x194 /* PLL_BIAS_CONTROL_1 */
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0x22 0x198 /* PLL_BIAS_CONTROL_2 */
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0x21 0x214 /* PWR_CTRL2 */
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0x08 0x220 /* IMP_CTRL1 */
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0x58 0x224 /* IMP_CTRL2 */
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0x45 0x240 /* TUNE1 */
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0x29 0x244 /* TUNE2 */
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0xca 0x248 /* TUNE3 */
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0x04 0x24c /* TUNE4 */
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0x03 0x250 /* TUNE5 */
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0x30 0x23c /* CHG_CTRL2 */
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0x22 0x210>; /* PWR_CTRL1 */
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};
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