6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
74 lines
2.0 KiB
YAML
74 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive PWM controller
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maintainers:
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- Sagar Kadam <sagar.kadam@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description:
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Unlike most other PWM controllers, the SiFive PWM controller currently
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only supports one period for all channels in the PWM. All PWMs need to
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run at the same period. The period also has significant restrictions on
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the values it can achieve, which the driver rounds to the nearest
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achievable period. PWM RTL that corresponds to the IP block version
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numbers can be found here -
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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items:
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- enum:
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- sifive,fu540-c000-pwm
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- sifive,fu740-c000-pwm
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- const: sifive,pwm0
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description:
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Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
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compatible strings are "sifive,fu540-c000-pwm" and
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"sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
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SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
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SiFive PWM v0 IP block with no chip integration tweaks.
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Please refer to sifive-blocks-ip-versioning.txt for details.
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#pwm-cells":
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const: 3
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interrupts:
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maxItems: 4
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description:
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Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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additionalProperties: false
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examples:
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- |
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pwm: pwm@10020000 {
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compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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reg = <0x10020000 0x1000>;
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clocks = <&tlclk>;
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interrupt-parent = <&plic>;
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interrupts = <42>, <43>, <44>, <45>;
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#pwm-cells = <3>;
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};
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