e3338c6885
Add clock controller bindings for RPMHCC/CAMCC/GCC/DISPCC/GPUCC and DEBUGCC on SM4450 Platform. Change-Id: I779f0915c24a12664e6566ac386cf4ac4dd911e6 Signed-off-by: Chetan C R <quic_cchinnad@quicinc.com>
56 lines
1.4 KiB
YAML
56 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on SM4450
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maintainers:
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- Ajit Pandey <quic_ajipan@quicinc.com>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm Technologies, Inc. global clock control module provides the clocks, resets and power
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domains on SM4450
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See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h
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properties:
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compatible:
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const: qcom,sm4450-gcc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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- description: UFS Phy Rx symbol 0 clock source
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- description: UFS Phy Rx symbol 1 clock source
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- description: UFS Phy Tx symbol 0 clock source
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- description: USB3 Phy wrapper pipe clock source
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required:
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,sm4450-gcc";
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reg = <0x00100000 0x001f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
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<&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
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<&ufs_mem_phy 2>, <&usb_1_qmpphy>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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