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android_kernel_samsung_sm87…/sun-camera.dtsi
Mukund Madhusudan Atre dfb7c5948a ARM: dts: msm: Fix reg cam base for camera nodes in sun 
Currently, the register base addresses in the reg cam base
property of camera nodes are incorrect. Update the values to
reflect the correct difference with camera base. Also, update
the reg base addresses in all the camera nodes for uniformity.

CRs-Fixed: 3762492
Change-Id: Idfa710a05b4e1f45ea6739b04ba739160b8b9f03
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
2024-03-28 18:00:21 -07:00

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#include <dt-bindings/msm-camera.h>
#include <dt-bindings/arm/msm/qti-smmu-proxy-dt-ids.h>
&tlmm {
cci_i2c_sda0_active: cci_i2c_sda0_active {
mux {
/* CLK, DATA */
pins = "gpio113";
function = "cci_i2c_sda0";
};
config {
pins = "gpio113";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda0_suspend: cci_i2c_sda0_suspend {
mux {
/* CLK, DATA */
pins = "gpio113";
function = "cci_i2c_sda0";
};
config {
pins = "gpio113";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl0_active: cci_i2c_scl0_active {
mux {
/* CLK, DATA */
pins = "gpio114";
function = "cci_i2c_scl0";
};
config {
pins = "gpio114";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl0_suspend: cci_i2c_scl0_suspend {
mux {
/* CLK, DATA */
pins = "gpio114";
function = "cci_i2c_scl0";
};
config {
pins = "gpio114";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_sda1_active: cci_i2c_sda1_active {
mux {
/* CLK, DATA */
pins = "gpio115";
function = "cci_i2c_sda1";
};
config {
pins = "gpio115";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda1_suspend: cci_i2c_sda1_suspend {
mux {
/* CLK, DATA */
pins = "gpio115";
function = "cci_i2c_sda1";
};
config {
pins = "gpio115";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl1_active: cci_i2c_scl1_active {
mux {
/* CLK, DATA */
pins = "gpio116";
function = "cci_i2c_scl1";
};
config {
pins = "gpio116";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl1_suspend: cci_i2c_scl1_suspend {
mux {
/* CLK, DATA */
pins = "gpio116";
function = "cci_i2c_scl1";
};
config {
pins = "gpio116";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_sda2_active: cci_i2c_sda2_active {
mux {
/* CLK, DATA */
pins = "gpio117";
function = "cci_i2c_sda2";
};
config {
pins = "gpio117";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda2_suspend: cci_i2c_sda2_suspend {
mux {
/* CLK, DATA */
pins = "gpio117";
function = "cci_i2c_sda2";
};
config {
pins = "gpio117";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl2_active: cci_i2c_scl2_active {
mux {
/* CLK, DATA */
pins = "gpio118";
function = "cci_i2c_scl2";
};
config {
pins = "gpio118";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl2_suspend: cci_i2c_scl2_suspend {
mux {
/* CLK, DATA */
pins = "gpio118";
function = "cci_i2c_scl2";
};
config {
pins = "gpio118";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl3_active: cci_i2c_scl3_active {
mux {
pins = "gpio164";
function = "cci_i2c_scl3";
};
config {
pins = "gpio164";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda3_suspend: cci_i2c_sda3_suspend {
mux {
pins = "gpio111";
function = "cci_i2c_sda3";
};
config {
pins = "gpio111";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_sda3_active: cci_i2c_sda3_active {
mux {
pins = "gpio111";
function = "cci_i2c_sda3";
};
config {
pins = "gpio111";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl3_suspend: cci_i2c_scl3_suspend {
mux {
pins = "gpio164";
function = "cci_i2c_scl3";
};
config {
pins = "gpio164";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_sda4_active: cci_i2c_sda4_active {
mux {
/* CLK, DATA */
pins = "gpio112";
function = "cci_i2c_sda4";
};
config {
pins = "gpio112";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda4_suspend: cci_i2c_sda4_suspend {
mux {
/* CLK, DATA */
pins = "gpio112";
function = "cci_i2c_sda4";
};
config {
pins = "gpio112";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl4_active: cci_i2c_scl4_active {
mux {
/* CLK, DATA */
pins = "gpio153";
function = "cci_i2c_scl4";
};
config {
pins = "gpio153";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl4_suspend: cci_i2c_scl4_suspend {
mux {
/* CLK, DATA */
pins = "gpio153";
function = "cci_i2c_scl4";
};
config {
pins = "gpio153";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_sda5_active: cci_i2c_sda5_active {
mux {
/* CLK, DATA */
pins = "gpio119";
function = "cci_i2c_sda5";
};
config {
pins = "gpio119";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_sda5_suspend: cci_i2c_sda5_suspend {
mux {
/* CLK, DATA */
pins = "gpio119";
function = "cci_i2c_sda5";
};
config {
pins = "gpio119";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci_i2c_scl5_active: cci_i2c_scl5_active {
mux {
/* CLK, DATA */
pins = "gpio120";
function = "cci_i2c_scl5";
};
config {
pins = "gpio120";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
qcom,i2c_pull;
};
};
cci_i2c_scl5_suspend: cci_i2c_scl5_suspend {
mux {
/* CLK, DATA */
pins = "gpio120";
function = "cci_i2c_scl5";
};
config {
pins = "gpio120";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
/* MCLK0 */
mux {
pins = "gpio89";
function = "cam_mclk";
};
config {
pins = "gpio89";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
/* MCLK0 */
mux {
pins = "gpio89";
function = "cam_mclk";
};
config {
pins = "gpio89";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk1_active: cam_sensor_mclk1_active {
/* MCLK1 */
mux {
pins = "gpio90";
function = "cam_mclk";
};
config {
pins = "gpio90";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
/* MCLK1 */
mux {
pins = "gpio90";
function = "cam_mclk";
};
config {
pins = "gpio90";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk2_active: cam_sensor_mclk2_active {
/* MCLK2 */
mux {
pins = "gpio91";
function = "cam_asc_mclk2";
};
config {
pins = "gpio91";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
/* MCLK2 */
mux {
pins = "gpio91";
function = "cam_asc_mclk2";
};
config {
pins = "gpio91";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk3_active: cam_sensor_mclk3_active {
/* MCLK3 */
mux {
pins = "gpio92";
function = "cam_mclk";
};
config {
pins = "gpio92";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
/* MCLK3 */
mux {
pins = "gpio92";
function = "cam_mclk";
};
config {
pins = "gpio92";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk4_active: cam_sensor_mclk4_active {
/* MCLK4 */
mux {
pins = "gpio93";
function = "cam_asc_mclk4";
};
config {
pins = "gpio93";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend {
/* MCLK4 */
mux {
pins = "gpio93";
function = "cam_asc_mclk4";
};
config {
pins = "gpio93";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk5_active: cam_sensor_mclk5_active {
/* MCLK5 */
mux {
pins = "gpio94";
function = "cam_mclk";
};
config {
pins = "gpio94";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend {
/* MCLK5 */
mux {
pins = "gpio94";
function = "cam_mclk";
};
config {
pins = "gpio94";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk6_active: cam_sensor_mclk6_active {
/* MCLK6 */
mux {
pins = "gpio96";
function = "cam_mclk";
};
config {
pins = "gpio96";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend {
/* MCLK6 */
mux {
pins = "gpio96";
function = "cam_mclk";
};
config {
pins = "gpio96";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk7_active: cam_sensor_mclk7_active {
/* MCLK7 */
mux {
pins = "gpio95";
function = "cam_mclk";
};
config {
pins = "gpio95";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk7_suspend: cam_sensor_mclk7_suspend {
/* MCLK7 */
mux {
pins = "gpio95";
function = "cam_mclk";
};
config {
pins = "gpio95";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_active_rst0: cam_sensor_active_rst0 {
mux {
pins = "gpio13";
function = "gpio";
};
config {
pins = "gpio13";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 {
mux {
pins = "gpio13";
function = "gpio";
};
config {
pins = "gpio13";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst1: cam_sensor_active_rst1 {
mux {
pins = "gpio15";
function = "gpio";
};
config {
pins = "gpio15";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 {
mux {
pins = "gpio15";
function = "gpio";
};
config {
pins = "gpio15";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst2: cam_sensor_active_rst2 {
mux {
pins = "gpio3";
function = "gpio";
};
config {
pins = "gpio3";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
qcom,apps;
};
};
cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 {
mux {
pins = "gpio3";
function = "gpio";
};
config {
pins = "gpio3";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
qcom,remote;
};
};
cam_sensor_active_rst3: cam_sensor_active_rst3 {
mux {
pins = "gpio109";
function = "gpio";
};
config {
pins = "gpio109";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 {
mux {
pins = "gpio109";
function = "gpio";
};
config {
pins = "gpio109";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst4: cam_sensor_active_rst4 {
mux {
pins = "gpio7";
function = "gpio";
};
config {
pins = "gpio7";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
qcom,apps;
};
};
cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 {
mux {
pins = "gpio7";
function = "gpio";
};
config {
pins = "gpio7";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
qcom,remote;
};
};
cam_sensor_active_rst5: cam_sensor_active_rst5 {
mux {
pins = "gpio110";
function = "gpio";
};
config {
pins = "gpio110";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 {
mux {
pins = "gpio110";
function = "gpio";
};
config {
pins = "gpio110";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst6: cam_sensor_active_rst6 {
mux {
pins = "gpio111";
function = "gpio";
};
config {
pins = "gpio111";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 {
mux {
pins = "gpio111";
function = "gpio";
};
config {
pins = "gpio111";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_active_rst7: cam_sensor_active_rst7 {
mux {
pins = "gpio164";
function = "gpio";
};
config {
pins = "gpio164";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_suspend_rst7: cam_sensor_suspend_rst7 {
mux {
pins = "gpio164";
function = "gpio";
};
config {
pins = "gpio164";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_i3cSelect_active: cam_sensor_i3cSelect_active {
mux {
pins = "gpio6";
function = "gpio";
};
config {
pins = "gpio6";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_i3cSelect_suspend: cam_sensor_i3cSelect_suspend {
mux {
pins = "gpio6";
function = "gpio";
};
config {
pins = "gpio6";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
};
};
cam_sensor_ponv_rear_active: cam_sensor_ponv_rear_active {
mux {
pins = "gpio2";
function = "gpio";
};
config {
pins = "gpio2";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
qcom,apps;
};
};
cam_sensor_ponv_rear_suspend: cam_sensor_ponv_rear_suspend {
mux {
pins = "gpio2";
function = "gpio";
};
config {
pins = "gpio2";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
output-low;
qcom,remote;
};
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
status = "ok";
};
qcom,cam-sync {
compatible = "qcom,cam-sync";
status = "ok";
};
qcom,cam-i3c-id-table {
i3c-sensor-id-table = <0x1B0 0x0858>;
i3c-eeprom-id-table = <>;
i3c-actuator-id-table = <>;
i3c-ois-id-table = <>;
status = "disabled";
};
cam_csiphy0: qcom,csiphy0@ada9000 {
cell-index = <0>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0ada9000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1a9000>;
interrupt-names = "CSIPHY0";
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_csiphy1: qcom,csiphy1@adab000 {
cell-index = <1>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0adab000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1ab000>;
interrupt-names = "CSIPHY1";
interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_csiphy2: qcom,csiphy2@adad000 {
cell-index = <2>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0adad000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1ad000>;
interrupt-names = "CSIPHY2";
interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L3I>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 912000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy2_clk",
"csi2phytimer_clk_src",
"csi2phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_csiphy3: qcom,csiphy3@adaf000 {
cell-index = <3>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0adaf000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1af000>;
interrupt-names = "CSIPHY3";
interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy3_clk",
"csi3phytimer_clk_src",
"csi3phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_csiphy4: qcom,csiphy4@adb1000 {
cell-index = <4>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0adb1000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1b1000>;
interrupt-names = "CSIPHY4";
interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L3I>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 912000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy4_clk",
"csi4phytimer_clk_src",
"csi4phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_csiphy5: qcom,csiphy5@adb3000 {
cell-index = <5>;
compatible = "qcom,csiphy-v2.3.0", "qcom,csiphy";
reg = <0x0adb3000 0x2000>;
reg-names = "csiphy";
reg-cam-base = <0x1b3000>;
interrupt-names = "CSIPHY5";
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
csi-vdd-1p2-supply = <&L3G>;
csi-vdd-0p9-supply = <&L1F>;
rgltr-cntrl-support;
rgltr-min-voltage = <0 1200000 880000>;
rgltr-max-voltage = <0 1256000 920000>;
rgltr-load-current = <0 6200 88200>;
shared-clks = <1 0 0 0>;
clock-names = "cphy_rx_clk_src",
"csiphy5_clk",
"csi5phytimer_clk_src",
"csi5phytimer_clk";
clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY5_CLK>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK>;
src-clock-name = "cphy_rx_clk_src";
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
clock-rates =
<266666667 0 400000000 0>,
<400000000 0 400000000 0>,
<480000000 0 400000000 0>;
status = "ok";
};
cam_cci0: qcom,cci0@ac7b000 {
cell-index = <0>;
compatible = "qcom,cci", "simple-bus";
reg = <0x0ac7b000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x7b000>;
interrupt-names = "CCI0";
interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cci_0_clk_src",
"cci_0_clk";
clocks = <&camcc CAM_CC_CCI_0_CLK_SRC>,
<&camcc CAM_CC_CCI_0_CLK>;
clock-rates = <37500000 0>, <37500000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs";
src-clock-name = "cci_0_clk_src";
pctrl-idx-mapping = <CCI_MASTER_0 CCI_MASTER_1>;
pctrl-map-names = "m0", "m1";
pinctrl-names = "m0_active", "m0_suspend",
"m1_active", "m1_suspend";
pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>;
pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>;
pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>;
pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>;
status = "ok";
i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci0: qcom,i2c_custom_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <1>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
cam_cci1: qcom,cci1@ac7c000 {
cell-index = <1>;
compatible = "qcom,cci", "simple-bus";
reg = <0x0ac7c000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x7c000>;
interrupt-names = "CCI1";
interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cci_1_clk_src",
"cci_1_clk";
clocks = <&camcc CAM_CC_CCI_1_CLK_SRC>,
<&camcc CAM_CC_CCI_1_CLK>;
clock-rates = <37500000 0>, <37500000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs";
src-clock-name = "cci_1_clk_src";
pctrl-idx-mapping = <CCI_MASTER_0 CCI_MASTER_1>;
pctrl-map-names = "m0", "m1";
pinctrl-names = "m0_active", "m0_suspend",
"m1_active", "m1_suspend";
pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>;
pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>;
pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_scl3_active>;
pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_scl3_suspend>;
status = "ok";
i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci1: qcom,i2c_custom_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <1>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
cam_cci2: qcom,cci2@ac7d000 {
cell-index = <2>;
compatible = "qcom,cci", "simple-bus";
reg = <0x0ac7d000 0x1000>;
reg-names = "cci";
reg-cam-base = <0x7d000>;
interrupt-names = "CCI2";
interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdscr";
gdscr-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cci_2_clk_src",
"cci_2_clk";
clocks = <&camcc CAM_CC_CCI_2_CLK_SRC>,
<&camcc CAM_CC_CCI_2_CLK>;
clock-rates = <37500000 0>, <37500000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs";
src-clock-name = "cci_2_clk_src";
pctrl-idx-mapping = <CCI_MASTER_0 CCI_MASTER_1>;
pctrl-map-names = "m0", "m1";
pinctrl-names = "m0_active", "m0_suspend",
"m1_active", "m1_suspend";
pinctrl-0 = <&cci_i2c_scl4_active &cci_i2c_sda4_active>;
pinctrl-1 = <&cci_i2c_scl4_suspend &cci_i2c_sda4_suspend>;
pinctrl-2 = <&cci_i2c_scl5_active &cci_i2c_sda5_active>;
pinctrl-3 = <&cci_i2c_scl5_suspend &cci_i2c_sda5_suspend>;
status = "ok";
i2c_freq_100Khz_cci2: qcom,i2c_standard_mode {
hw-thigh = <201>;
hw-tlow = <174>;
hw-tsu-sto = <204>;
hw-tsu-sta = <231>;
hw-thd-dat = <22>;
hw-thd-sta = <162>;
hw-tbuf = <227>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_400Khz_cci2: qcom,i2c_fast_mode {
hw-thigh = <38>;
hw-tlow = <56>;
hw-tsu-sto = <40>;
hw-tsu-sta = <40>;
hw-thd-dat = <22>;
hw-thd-sta = <35>;
hw-tbuf = <62>;
hw-scl-stretch-en = <0>;
hw-trdhld = <6>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_custom_cci2: qcom,i2c_custom_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <1>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
i2c_freq_1Mhz_cci2: qcom,i2c_fast_plus_mode {
hw-thigh = <16>;
hw-tlow = <22>;
hw-tsu-sto = <17>;
hw-tsu-sta = <18>;
hw-thd-dat = <16>;
hw-thd-sta = <15>;
hw-tbuf = <24>;
hw-scl-stretch-en = <0>;
hw-trdhld = <3>;
hw-tsp = <3>;
cci-clk-src = <37500000>;
status = "ok";
};
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu", "simple-bus";
status = "ok";
expanded_memory;
force_cache_allocs;
need_shared_buffer_padding;
#address-cells = <2>;
#size-cells = <2>;
msm_cam_smmu_ife: msm_cam_smmu_ife {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1C00 0x00>;
qcom,iommu-faults = "stall-disable", "non-fatal";
dma-coherent;
cam-smmu-label = "ife";
multiple-client-devices;
memory-region = <&cam_smmu_ife_resv_region>;
cam_smmu_ife_resv_region: cam_smmu_ife_resv_region {
iommu-addresses = <&msm_cam_smmu_ife 0x0 0x0 0x0 0x100000>,
<&msm_cam_smmu_ife 0xf 0xfff00000 0x0 0x100000>;
};
ife_iova_mem_map: iova-mem-map {
/* IO region is approximately 64 GB */
iova-mem-region-io {
iova-region-name = "io";
/* start address: 0x100000 */
/* leaving 1 MB pad at start */
iova-region-start = <0x0 0x100000>;
/* Length: 0xfffe00000 */
/* leaving 1 MB pad at end */
iova-region-len = <0xf 0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_jpeg: msm_cam_smmu_jpeg {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x18A0 0x00>;
cam-smmu-label = "jpeg";
qcom,iommu-faults = "stall-disable", "non-fatal";
dma-coherent;
memory-region = <&cam_smmu_jpeg_resv_region>;
cam_smmu_jpeg_resv_region: cam_smmu_jpeg_resv_region {
iommu-addresses = <&msm_cam_smmu_jpeg 0x0 0x0 0x0 0x100000>,
<&msm_cam_smmu_jpeg 0x0 0xfff00000 0xf 0x00100000>;
};
jpeg_iova_mem_map: iova-mem-map {
/* IO region is approximately 4.0 GB */
iova-mem-region-io {
iova-region-name = "io";
/* start address:0x100000 */
/* leaving 1 MB pad for start */
iova-region-start = <0x0 0x100000>;
/* Length: 0xffe00000 */
/* leaving 1 MB pad at end */
iova-region-len = <0x0 0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_icp: msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1820 0x00>,
<&apps_smmu 0x1800 0xC0>,
<&apps_smmu 0x1980 0x00>;
cam-smmu-label = "icp", "icp1";
multiple-client-devices;
multiple-same-region-clients = "icp", "icp1";
qcom,iommu-faults = "stall-disable", "non-fatal";
dma-coherent;
memory-region = <&cam_smmu_icp_resv_region>;
cam_smmu_icp_resv_region: cam_smmu_icp_resv_region {
iommu-addresses = <&msm_cam_smmu_icp 0x0 0x0 0x0 0xf1600000>;
};
icp_iova_mem_map: iova-mem-map {
iova-mem-region-shared1 {
/* Shared region is ~900MB long */
iova-region-name = "shared";
/* Start address: 0x80e00000 */
iova-region-start = <0x0 0x80e00000>;
/* Length: 0x38400000 */
iova-region-len = <0x0 0x38400000>;
iova-region-id = <0x1>;
status = "ok";
};
iova-mem-region-shared2 {
/* Shared region is ~900MB long */
iova-region-name = "shared";
/* Start address: 0xb9200000 */
iova-region-start = <0x0 0xb9200000>;
/* Length: 0x38400000 */
iova-region-len = <0x0 0x38400000>;
iova-region-id = <0x1>;
status = "ok";
};
iova-mem-region-fwuncached-region1 {
/* FW uncached region is 5 MB long */
iova-region-name = "fw_uncached";
/* Start address: 0x80400000 */
iova-region-start = <0x0 0x80400000>;
/* Length: 0x500000 */
iova-region-len = <0x0 0x500000>;
iova-region-id = <0x6>;
subregion_support;
status = "ok";
/* Used for HFI queues/sec heap */
iova-mem-region-generic-region {
iova-region-name = "icp_hfi";
iova-region-start = <0x0 0x80500000>;
/* Length: 0x200000 */
iova-region-len = <0x0 0x200000>;
iova-region-id = <0x0>;
};
/* Global Sync Memory for IPC */
iova-mem-region-global-sync-region {
iova-region-name = "global_sync";
iova-region-start = <0x0 0x80400000>;
/* Length: 0x100000 */
iova-region-len = <0x0 0x100000>;
iova-region-id = <0x3>;
phy-addr = <0x82600000>;
};
};
iova-mem-region-fwuncached-region2 {
/* FW uncached region is 5 MB long */
iova-region-name = "fw_uncached";
/* Start address: 0x80900000 */
iova-region-start = <0x0 0x80900000>;
/* Length: 0x500000 */
iova-region-len = <0x0 0x500000>;
iova-region-id = <0x6>;
subregion_support;
status = "ok";
/* Used for HFI queues/sec heap */
iova-mem-region-generic-region {
iova-region-name = "icp_hfi";
iova-region-start = <0x0 0x80a00000>;
/* Length: 0x200000 */
iova-region-len = <0x0 0x200000>;
iova-region-id = <0x0>;
};
/* Global Sync Memory for IPC */
iova-mem-region-global-sync-region {
iova-region-name = "global_sync";
iova-region-start = <0x0 0x80900000>;
/* Length: 0x100000 */
iova-region-len = <0x0 0x100000>;
iova-region-id = <0x3>;
phy-addr = <0x82600000>;
};
};
iova-mem-device-region {
/* Device region is appropriate 1MB */
iova-region-name = "device";
iova-region-start = <0x0 0x80100000>;
iova-region-len = <0x0 0x300000>;
iova-region-id = <0x7>;
subregion_support;
status = "ok";
iova-mem-region-synx-hwmutex {
iova-region-name = "synx_hwmutex";
iova-region-start = <0x0 0x80100000>;
iova-region-len = <0x0 0x1000>;
iova-region-id = <0x1>;
phy-addr = <0x1f4a000>;
};
iova-mem-region-ipc-hwmutex {
iova-region-name = "ipc_hwmutex";
iova-region-start = <0x0 0x80101000>;
iova-region-len = <0x0 0x1000>;
iova-region-id = <0x2>;
phy-addr = <0x1f4b000>;
};
iova-mem-region-global_cntr {
iova-region-name = "global_cntr";
iova-region-start = <0x0 0x80102000>;
iova-region-len = <0x0 0x1000>;
iova-region-id = <0x4>;
phy-addr = <0xc220000>;
};
iova-mem-region-llcc-register {
iova-region-name = "llcc-register";
iova-region-start = <0x0 0x80103000>;
iova-region-len = <0x0 0x200000>;
iova-region-id = <0x5>;
phy-addr = <0x26C00000>;
};
};
iova-mem-region-io {
/* IO region is approximately 60 GB */
iova-region-name = "io";
/* Start address: 0xf1600000 */
iova-region-start = <0x0 0xf1600000>;
/* Length: 0xf0ea00000 */
iova-region-len = <0xf 0x0ea00000>;
iova-region-id = <0x3>;
status = "ok";
};
iova-mem-qdss-region {
/* QDSS region is appropriate 1MB */
iova-region-name = "qdss";
/* Start address: 0x80000000 */
iova-region-start = <0x0 0x80000000>;
/* Length: 0x100000 */
iova-region-len = <0x0 0x100000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x37790000>;
status = "ok";
};
};
};
msm_cam_smmu_cdm: msm_cam_smmu_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1860 0x00>;
cam-smmu-label = "rt-cdm";
qcom,iommu-faults = "stall-disable", "non-fatal";
dma-coherent;
multiple-client-devices;
memory-region = <&cam_smmu_cdm_resv_region>;
cam_smmu_cdm_resv_region: cam_smmu_cdm_resv_region {
iommu-addresses = <&msm_cam_smmu_cdm 0x0 0x0 0x0 0x100000>,
<&msm_cam_smmu_cdm 0x0 0xfff00000 0xf 0x00100000>;
};
rt_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
iova-region-name = "io";
/* 1 MB pad for start */
iova-region-start = <0x0 0x100000>;
/* 1 MB pad for end */
iova-region-len = <0x0 0xffe00000>;
iova-region-id = <0x3>;
status = "ok";
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
cam-smmu-label = "cam-secure";
qcom,secure-cb;
qti,smmu-proxy-cb-id = <QTI_SMMU_PROXY_CAMERA_CB>;
};
};
qcom,cam-cpas@ac13000 {
cell-index = <0>;
compatible = "qcom,cam-cpas";
label = "cpas";
arch-compat = "cpas_top";
reg-names = "cam_cpas_top", "cam_camnoc_nrt", "cam_camnoc_rt", "cam_rpmh", "cam_cesta";
reg = <0x0ac04000 0x1000>,
<0x0ac62000 0x9200>,
<0x0ad90000 0x9000>,
<0x0bbf0000 0x1f00>,
<0x0adcb000 0x5000>;
reg-cam-base = <0x4000 0x62000 0x190000 0x0bbf0000 0x0adcb000>;
interrupt-names = "cpas_camnoc_rt", "cpas_camnoc_nrt";
interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
camnoc-axi-min-ib-bw = <3000000000>;
regulator-names = "top-gdsc";
top-gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"gcc_ahb_clk",
"gcc_axi_hf_clk",
"gcc_axi_sf_clk",
"cam_cc_slow_ahb_clk_src",
"cpas_ahb_clk",
"cpas_core_ahb_clk",
"cam_cc_drv_ahb_clk",
"cam_cc_fast_ahb_clk_src",
"cam_cc_top_fast_ahb_clk",
"camnoc_rt_axi_clk_src",
"camnoc_rt_axi_clk",
"camnoc_nrt_axi_clk",
"cam_cc_drv_xo_clk",
"cam_cc_pll0",
"cam_cc_qdss_debug_xo_clk";
clocks =
<&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&gcc GCC_CAMERA_SF_AXI_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CAM_TOP_AHB_CLK>,
<&camcc CAM_CC_CORE_AHB_CLK>,
<&camcc CAM_CC_DRV_AHB_CLK>,
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
<&camcc CAM_CC_CAMNOC_RT_AXI_CLK_SRC>,
<&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
<&camcc CAM_CC_DRV_XO_CLK>,
<&camcc CAM_CC_PLL0>,
<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
clock-rates =
<0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>,
<0 0 0 56470588 0 0 0 213333333 0 200000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 300000000 0 300000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 300000000 0 400000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>,
<0 0 0 80000000 0 0 0 400000000 0 400000000 0 0 0 0 0>;
clock-cntl-level = "suspend", "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "nominal_l1", "turbo";
src-clock-name = "camnoc_rt_axi_clk_src";
domain-id-support-clks = "ife_lite_csid_clk",
"ife_lite_ahb", "csid_clk_src", "csid_clk";
clock-names-option = "ife_lite_csid_clk",
"ife_lite_ahb", "csid_clk_src", "csid_clk";
clocks-option = <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK>;
clock-rates-option = <400000000>,
<0>, <0>, <0>, <0>;
shared-clks-option = <0 0 0 1 0>;
control-camnoc-axi-clk;
camnoc-bus-width = <32>;
camnoc-axi-clk-bw-margin-perc = <20>;
domain-id = <CAM_CPAS_SECURE_DOMAIN 16>,
<CAM_CPAS_NON_SECURE_DOMAIN 0>;
cam-icc-path-names = "cam_ahb";
interconnect-names = "cam_ahb",
"cam_hf_0",
"cam_ife_0_drv",
"cam_ife_1_drv",
"cam_ife_2_drv",
"cam_sf_0",
"cam_sf_icp";
interconnects = <&gem_noc MASTER_APPSS_PROC
&config_noc SLAVE_CAMERA_CFG>,
<&mmss_noc MASTER_CAMNOC_HF
&mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_0
&mc_virt SLAVE_EBI1_CAM_IFE_0>,
<&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_1
&mc_virt SLAVE_EBI1_CAM_IFE_1>,
<&mmss_noc MASTER_CAMNOC_HF_CAM_IFE_2
&mc_virt SLAVE_EBI1_CAM_IFE_2>,
<&mmss_noc MASTER_CAMNOC_SF
&mc_virt SLAVE_EBI1>,
<&mmss_noc MASTER_CAMNOC_NRT_ICP_SF
&mc_virt SLAVE_EBI1>;
rpmh-bcm-info = <13 0x4 0x800 0 4>;
cam-ahb-num-cases = <8>;
cam-ahb-bw-KBps =
<0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>,
<0 300000>, <0 300000>, <0 300000>;
vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
RPMH_REGULATOR_LEVEL_MIN_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_SVS
RPMH_REGULATOR_LEVEL_SVS_L1
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM_L1
RPMH_REGULATOR_LEVEL_NOM_L2
RPMH_REGULATOR_LEVEL_TURBO
RPMH_REGULATOR_LEVEL_TURBO_L1>;
vdd-corner-ahb-mapping = "suspend", "lowsvs",
"lowsvs", "svs", "svs_l1",
"nominal", "nominal", "nominal",
"turbo", "turbo";
client-id-based;
client-names =
"csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5",
"cci0", "cci1", "cci2", "csid0", "csid1", "csid2", "csid3", "csid4",
"ife0", "ife1", "ife2", "ife3", "ife4",
"ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2", "rt-cdm3", "rt-cdm4",
"cam-cdm-intf0", "icp0", "icp1", "ofe0", "cre0",
"jpeg-dma0", "jpeg-enc0", "jpeg-dma1", "jpeg-enc1",
"tpg13", "tpg14", "tpg15";
sys-cache-names = "ofe_ip", "ipe_rt_ip", "ipe_srt_ip", "ipe_rt_rf", "ipe_srt_rf";
sys-cache-uids = <71 72 73 74 75>;
sys-cache-concur = <1 1 1 0 0>;
enable-smart-qos;
enable-cam-drv = <(CAM_DDR_DRV | CAM_CLK_DRV)>;
rt-wr-priority-min = <4>;
rt-wr-priority-max = <5>;
rt-wr-priority-clamp = <6>;
rt-wr-slope-factor = <70>;
rt-wr-leaststressed-clamp-threshold = <10>;
rt-wr-moststressed-clamp-threshold = <6>;
rt-wr-highstress-indicator-threshold = <50>;
rt-wr-lowstress-indicator-threshold = <0>;
rt-wr-bw-ratio-scale-factor = <1>;
status = "ok";
camera-bus-nodes {
level3-nodes {
level-index = <3>;
level3_rt_rd_wr_sum: level3-rt-rd-wr-sum {
cell-index = <0>;
node-name = "level3-rt-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
ib-bw-voting-needed;
rt-axi-port;
qcom,axi-port-mnoc {
cam-icc-path-names = "cam_hf_0",
"cam_ife_0_drv",
"cam_ife_1_drv",
"cam_ife_2_drv";
};
};
level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
cell-index = <1>;
node-name = "level3-nrt0-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
cam-icc-path-names = "cam_sf_0";
};
};
level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
cell-index = <2>;
node-name = "level3-nrt1-rd-wr-sum";
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
qcom,axi-port-mnoc {
cam-icc-path-names =
"cam_sf_icp";
};
};
};
level2-nodes {
level-index = <2>;
camnoc-max-needed;
level2_rt_wr: level2-rt-wr {
cell-index = <3>;
node-name = "level2-rt-wr";
parent-node = <&level3_rt_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_rt_rd: level2-rt-rd {
cell-index = <4>;
node-name = "level2-rt-rd";
parent-node = <&level3_rt_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_nrt_wr: level2-nrt-wr {
cell-index = <5>;
node-name = "level2-nrt-wr";
parent-node = <&level3_nrt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_nrt_rd: level2-nrt-rd {
cell-index = <6>;
node-name = "level2-nrt-rd";
parent-node = <&level3_nrt0_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
};
level2_icp_rd: level2-icp-rd {
cell-index = <7>;
node-name = "level2-icp-rd";
parent-node = <&level3_nrt1_rd_wr_sum>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
bus-width-factor = <4>;
};
};
level1-nodes {
level-index = <1>;
camnoc-max-needed;
level1_rt1_wr: level1-rt1-wr {
cell-index = <8>;
node-name = " level1-rt1-ife-ubwc-wr";
parent-node = <&level2_rt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
rt-wr-niu;
niu-size = <134>;
priority-lut-low-offset = <0x4830>;
priority-lut-high-offset = <0x4834>;
};
level1_rt2_wr: level1-rt2-wr {
cell-index = <9>;
node-name = "level1-rt2-ife-stats";
parent-node = <&level2_rt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
rt-wr-niu;
niu-size = <36>;
priority-lut-low-offset = <0x4A30>;
priority-lut-high-offset = <0x4A34>;
};
level1_rt3_wr: level1-rt3-wr {
cell-index = <10>;
node-name = "level1-rt3-ife-pdaf-lite";
parent-node = <&level2_rt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
rt-wr-niu;
niu-size = <92>;
priority-lut-low-offset = <0x4C30>;
priority-lut-high-offset = <0x4C34>;
};
level1_rt4_wr: level1-rt4-wr1 {
cell-index = <11>;
node-name = "level1-rt4-ife-rdi-wr";
parent-node = <&level2_rt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
rt-wr-niu;
niu-size = <134>;
priority-lut-low-offset = <0x5230>;
priority-lut-high-offset = <0x5234>;
};
level1_rt3_rd: level1-rt3-rd {
cell-index = <12>;
node-name = "level1-rt3-cdm-rd";
parent-node = <&level2_rt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
rt-wr-niu;
niu-size = <92>;
priority-lut-low-offset = <0x4C30>;
priority-lut-high-offset = <0x4C34>;
};
level1_nrt2_wr: level1-nrt2-wr {
cell-index = <13>;
node-name = "level1-nrt2-wr";
parent-node = <&level2_nrt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt6_wr: level1-nrt6-wr {
cell-index = <14>;
node-name = "level1-nrt6-wr";
parent-node = <&level2_nrt_wr>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt6_rd: level1-nrt6-rd {
cell-index = <15>;
node-name = "level1-nrt6-rd";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt0_rd: level1-nrt0-rd {
cell-index = <16>;
node-name = "level1-nrt0-rd";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt5_rd: level1-nrt5-rd {
cell-index = <17>;
node-name = "level1-nrt5-rd";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt4_rd: level1-nrt4-rd {
cell-index = <18>;
node-name = "level1-nrt4-rd";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt3_wr: level1-nrt3-wr {
cell-index = <19>;
node-name = "level1-nrt3-wr";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
level1_nrt9_rd: level1-nrt9-rd {
cell-index = <20>;
node-name = "level1-nrt3-wr";
parent-node = <&level2_nrt_rd>;
traffic-merge-type =
<CAM_CPAS_TRAFFIC_MERGE_SUM>;
};
};
level0-nodes {
level-index = <0>;
ife0_ubwc_wr: ife0-ubwc-wr {
cell-index = <21>;
node-name = "ife0-ubwc-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_FULL
CAM_CPAS_PATH_DATA_IFE_DS2
CAM_CPAS_PATH_DATA_IFE_PDAF_1>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_0>;
parent-node = <&level1_rt1_wr>;
};
ife1_ubwc_wr: ife1-ubwc-wr {
cell-index = <22>;
node-name = "ife1-ubwc-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_FULL
CAM_CPAS_PATH_DATA_IFE_DS2
CAM_CPAS_PATH_DATA_IFE_PDAF_1>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_1>;
parent-node = <&level1_rt1_wr>;
};
ife2_ubwc_wr: ife2-ubwc-wr {
cell-index = <23>;
node-name = "ife2-ubwc-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_UBWC>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_FULL
CAM_CPAS_PATH_DATA_IFE_DS2
CAM_CPAS_PATH_DATA_IFE_PDAF_1>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_2>;
parent-node = <&level1_rt4_wr>;
};
ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr {
cell-index = <24>;
node-name = "ife0-rdi-pixel-raw-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3
CAM_CPAS_PATH_DATA_IFE_RDI4
CAM_CPAS_PATH_DATA_IFE_DS4
CAM_CPAS_PATH_DATA_IFE_DS16
CAM_CPAS_PATH_DATA_IFE_IR>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_0>;
parent-node = <&level1_rt4_wr>;
};
ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr {
cell-index = <25>;
node-name = "ife1-rdi-pixel-raw-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3
CAM_CPAS_PATH_DATA_IFE_RDI4
CAM_CPAS_PATH_DATA_IFE_DS4
CAM_CPAS_PATH_DATA_IFE_DS16
CAM_CPAS_PATH_DATA_IFE_IR>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_1>;
parent-node = <&level1_rt4_wr>;
};
ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr {
cell-index = <26>;
node-name = "ife2-rdi-pixel-raw-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3
CAM_CPAS_PATH_DATA_IFE_RDI4
CAM_CPAS_PATH_DATA_IFE_DS4
CAM_CPAS_PATH_DATA_IFE_DS16
CAM_CPAS_PATH_DATA_IFE_IR>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_2>;
parent-node = <&level1_rt1_wr>;
};
ife0_pdaf_linear_wr: ife0-pdaf-linear-wr {
cell-index = <27>;
node-name = "ife0-pdaf-linear-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_PDAF_LINEAR>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_PDAF
CAM_CPAS_PATH_DATA_IFE_PDAF_2
CAM_CPAS_PATH_DATA_IFE_PDAF_3
CAM_CPAS_PATH_DATA_IFE_FD>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_0>;
parent-node = <&level1_rt3_wr>;
};
ife1_pdaf_linear_wr: ife1-pdaf-linear-wr {
cell-index = <28>;
node-name = "ife1-pdaf-linear-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_PDAF_LINEAR>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_PDAF
CAM_CPAS_PATH_DATA_IFE_PDAF_2
CAM_CPAS_PATH_DATA_IFE_PDAF_3
CAM_CPAS_PATH_DATA_IFE_FD>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_1>;
parent-node = <&level1_rt3_wr>;
};
ife2_pdaf_linear_wr: ife2-pdaf-linear-wr {
cell-index = <29>;
node-name = "ife2-pdaf-linear-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_PDAF_LINEAR>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_PDAF
CAM_CPAS_PATH_DATA_IFE_PDAF_2
CAM_CPAS_PATH_DATA_IFE_PDAF_3
CAM_CPAS_PATH_DATA_IFE_FD>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_2>;
parent-node = <&level1_rt3_wr>;
};
ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr {
cell-index = <30>;
node-name = "ife4-rdi-stats-pixel-raw-wr";
client-name = "ife4";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3
CAM_CPAS_PATH_DATA_IFE_STATS>;
parent-node = <&level1_rt3_wr>;
};
ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr {
cell-index = <31>;
node-name = "ife3-rdi-stats-pixel-raw-wr";
client-name = "ife3";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IFE_RDI0
CAM_CPAS_PATH_DATA_IFE_RDI1
CAM_CPAS_PATH_DATA_IFE_RDI2
CAM_CPAS_PATH_DATA_IFE_RDI3
CAM_CPAS_PATH_DATA_IFE_STATS>;
parent-node = <&level1_rt3_wr>;
};
ife0_stats_wr: ife0-stats-wr {
cell-index = <32>;
node-name = "ife0-stats-wr";
client-name = "ife0";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_0>;
parent-node = <&level1_rt2_wr>;
};
ife1_stats_wr: ife1-stats-wr {
cell-index = <33>;
node-name = "ife1-stats-wr";
client-name = "ife1";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_1>;
parent-node = <&level1_rt2_wr>;
};
ife2_stats_wr: ife2-stats-wr {
cell-index = <34>;
node-name = "ife2-stats-wr";
client-name = "ife2";
traffic-data =
<CAM_CPAS_PATH_DATA_IFE_STATS>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
drv-voting-index =
<CAM_CPAS_PORT_DRV_2>;
parent-node = <&level1_rt2_wr>;
};
ipe0_all_wr: ipe0-all-wr {
cell-index = <35>;
node-name = "ipe0-all-wr";
client-name = "ipe0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_IPE_WR_VID
CAM_CPAS_PATH_DATA_IPE_WR_DISP
CAM_CPAS_PATH_DATA_IPE_WR_REF
CAM_CPAS_PATH_DATA_IPE_WR_APP>;
parent-node = <&level2_nrt_wr>;
};
cre0_all_wr: cre0-all-wr {
cell-index = <36>;
node-name = "cre0-all-wr";
client-name = "cre0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
parent-node = <&level1_nrt2_wr>;
};
jpeg_enc0_all_wr: jpeg-enc0-all-wr {
cell-index = <37>;
node-name = "jpeg-enc0-all-wr";
client-name = "jpeg-enc0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
parent-node = <&level1_nrt6_wr>;
};
jpeg_dma0_all_wr: jpeg-dma0-all-wr {
cell-index = <38>;
node-name = "jpeg-dma0-all-wr";
client-name = "jpeg-dma0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
parent-node = <&level1_nrt6_wr>;
};
jpeg_enc1_all_wr: jpeg-enc1-all-wr {
cell-index = <39>;
node-name = "jpeg-enc1-all-wr";
client-name = "jpeg-enc1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
parent-node = <&level1_nrt6_wr>;
};
jpeg_dma1_all_wr: jpeg-dma1-all-wr {
cell-index = <40>;
node-name = "jpeg-dma1-all-wr";
client-name = "jpeg-dma1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
parent-node = <&level1_nrt6_wr>;
};
cre0_all_rd: cre0-all-rd {
cell-index = <41>;
node-name = "cre0-all-rd";
client-name = "cre0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_nrt5_rd>;
};
jpeg_enc0_all_rd: jpeg0-enc0-all-rd {
cell-index = <42>;
node-name = "jpeg-enc0-rd";
client-name = "jpeg-enc0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_nrt6_rd>;
};
jpeg_dma0_all_rd: jpeg0-dma0-all-rd {
cell-index = <43>;
node-name = "jpeg-dma0-rd";
client-name = "jpeg-dma0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_nrt6_rd>;
};
jpeg_enc1_all_rd: jpeg1-enc1-all-rd {
cell-index = <44>;
node-name = "jpeg-enc1-rd";
client-name = "jpeg-enc1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_nrt6_rd>;
};
jpeg_dma1_all_rd: jpeg1-dma1-all-rd {
cell-index = <45>;
node-name = "jpeg-dma1-rd";
client-name = "jpeg-dma1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_nrt6_rd>;
};
ipe0_ref_rd: ipe0-ref-rd {
cell-index = <46>;
node-name = "ipe0-ref-rd";
client-name = "ipe0";
traffic-data =
<CAM_CPAS_PATH_DATA_IPE_RD_REF>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level2_nrt_rd>;
};
ipe0_in_rd: ipe0-in-rd {
cell-index = <47>;
node-name = "ipe0-in-rd";
client-name = "ipe0";
traffic-data =
<CAM_CPAS_PATH_DATA_IPE_RD_IN>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level2_nrt_rd>;
};
rt_cdm0_all_rd: rt-cdm0-all-rd {
cell-index = <48>;
node-name = "rt-cdm0-all-rd";
client-name = "rt-cdm0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt3_rd>;
};
rt_cdm1_all_rd: rt-cdm1-all-rd {
cell-index = <49>;
node-name = "rt-cdm1-all-rd";
client-name = "rt-cdm1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt3_rd>;
};
rt_cdm2_all_rd: rt-cdm2-all-rd {
cell-index = <50>;
node-name = "rt-cdm2-all-rd";
client-name = "rt-cdm2";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt3_rd>;
};
rt_cdm3_all_rd: rt-cdm3-all-rd {
cell-index = <51>;
node-name = "rt-cdm3-all-rd";
client-name = "rt-cdm3";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt3_rd>;
};
rt_cdm4_all_rd: rt-cdm4-all-rd {
cell-index = <52>;
node-name = "rt-cdm4-all-rd";
client-name = "rt-cdm4";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level1_rt3_rd>;
};
icp0_all_rd: icp0-all-rd {
cell-index = <53>;
node-name = "icp0-all-rd";
client-name = "icp0";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level2_icp_rd>;
};
icp1_all_rd: icp1-all-rd {
cell-index = <54>;
node-name = "icp1-all-rd";
client-name = "icp1";
traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
parent-node = <&level2_icp_rd>;
};
ofe0_linear_wr: ofe0-linear-wr {
cell-index = <55>;
node-name = "ofe0-linear-wr";
client-name = "ofe0";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_OFE_WR_DC4
CAM_CPAS_PATH_DATA_OFE_WR_AI
CAM_CPAS_PATH_DATA_OFE_WR_PDI
CAM_CPAS_PATH_DATA_OFE_WR_IDEALRAW
CAM_CPAS_PATH_DATA_OFE_WR_STATS>;
parent-node = <&level1_nrt2_wr>;
};
ofe0_in_rd: ofe0-in-rd {
cell-index = <56>;
node-name = "ofe0-in-rd";
client-name = "ofe0";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_READ>;
constituent-paths =
<CAM_CPAS_PATH_DATA_OFE_RD_EXT
CAM_CPAS_PATH_DATA_OFE_RD_INT_PDI
CAM_CPAS_PATH_DATA_OFE_RD_INT_HDR>;
parent-node = <&level1_nrt4_rd>;
};
ofe0_ubwc_wr: ofe0-ubwc-wr {
cell-index = <57>;
node-name = "ofe0-ubwc-wr";
client-name = "ofe0";
traffic-data =
<CAM_CPAS_PATH_DATA_ALL>;
traffic-transaction-type =
<CAM_CPAS_TRANSACTION_WRITE>;
constituent-paths =
<CAM_CPAS_PATH_DATA_OFE_WR_VID
CAM_CPAS_PATH_DATA_OFE_WR_DISP
CAM_CPAS_PATH_DATA_OFE_WR_IR
CAM_CPAS_PATH_DATA_OFE_WR_HDR_LTM>;
parent-node = <&level1_nrt3_wr>;
};
};
};
};
qcom,cam-cdm-intf {
compatible = "qcom,cam-cdm-intf";
cell-index = <0>;
label = "cam-cdm-intf";
num-hw-cdm = <1>;
cdm-client-names = "vfe",
"jpegdma",
"jpegenc";
status = "ok";
};
qcom,rt-cdm0@ac7f000 {
cell-index = <0>;
compatible = "qcom,cam-rt-cdm2_2";
label = "rt-cdm";
reg = <0x0ac7f000 0x580>;
reg-names = "rt-cdm0";
reg-cam-base = <0x7f000>;
interrupt-names = "rt-cdm0";
interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cam_top_ahb_clk";
clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>;
clock-rates = <0>;
clock-cntl-level = "turbo";
nrt-device;
cdm-client-names = "ife0";
config-fifo;
fifo-depths = <64 0 0 0>;
cam_hw_pid = <24>;
cam-hw-mid = <0>;
single-context-cdm;
status = "ok";
};
qcom,rt-cdm1@ac80000 {
cell-index = <1>;
compatible = "qcom,cam-rt-cdm2_2";
label = "rt-cdm";
reg = <0x0ac80000 0x580>;
reg-names = "rt-cdm1";
reg-cam-base = <0x80000>;
interrupt-names = "rt-cdm1";
interrupts = <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cam_top_ahb_clk";
clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>;
clock-rates = <0>;
clock-cntl-level = "turbo";
nrt-device;
cdm-client-names = "ife1";
config-fifo;
fifo-depths = <64 0 0 0>;
cam_hw_pid = <25>;
cam-hw-mid = <0>;
single-context-cdm;
status = "ok";
};
qcom,rt-cdm2@ac81000 {
cell-index = <2>;
compatible = "qcom,cam-rt-cdm2_2";
label = "rt-cdm";
reg = <0x0ac81000 0x580>;
reg-names = "rt-cdm2";
reg-cam-base = <0x81000>;
interrupt-names = "rt-cdm2";
interrupts = <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cam_top_ahb_clk";
clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>;
clock-rates = <0>;
clock-cntl-level = "turbo";
nrt-device;
cdm-client-names = "ife2";
config-fifo;
fifo-depths = <64 0 0 0>;
cam_hw_pid = <26>;
cam-hw-mid = <0>;
single-context-cdm;
status = "ok";
};
qcom,rt-cdm3@ac82000 {
cell-index = <3>;
compatible = "qcom,cam-rt-cdm2_2";
label = "rt-cdm";
reg = <0x0ac82000 0x580>;
reg-names = "rt-cdm3";
reg-cam-base = <0x82000>;
interrupt-names = "rt-cdm3";
interrupts = <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cam_top_ahb_clk";
clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>;
clock-rates = <0>;
clock-cntl-level = "turbo";
nrt-device;
cdm-client-names = "ife3";
config-fifo;
fifo-depths = <64 0 0 0>;
cam_hw_pid = <27>;
cam-hw-mid = <0>;
single-context-cdm;
status = "ok";
};
qcom,rt-cdm4@ac83000 {
cell-index = <4>;
compatible = "qcom,cam-rt-cdm2_2";
label = "rt-cdm";
reg = <0x0ac83000 0x580>;
reg-names = "rt-cdm4";
reg-cam-base = <0x83000>;
interrupt-names = "rt-cdm4";
interrupts = <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cam_top_ahb_clk";
clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>;
clock-rates = <0>;
clock-cntl-level = "turbo";
nrt-device;
cdm-client-names = "ife4";
config-fifo;
fifo-depths = <64 0 0 0>;
cam_hw_pid = <28>;
cam-hw-mid = <0>;
single-context-cdm;
status = "ok";
};
qcom,cam-isp {
compatible = "qcom,cam-isp";
arch-compat = "mc_tfe";
status = "ok";
};
cam_csid0: qcom,csid0@ad26000 {
cell-index = <0>;
compatible = "qcom,csid980";
reg-names = "csid";
reg = <0x0ad27000 0x2b00>;
reg-cam-base = <0x127000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "csid0";
interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <1 0 0>;
clock-names =
"csid_clk_src",
"csid_clk",
"csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0 0>,
<400000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe0: qcom,ife0@ac86000{
cell-index = <0>;
compatible = "qcom,mc_tfe980";
reg-names = "ife", "cam_camnoc_rt";
reg = <0x0ac86000 0x10000>,
<0x0ad90000 0x9000>;
reg-cam-base = <0x86000 0x19000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "tfe0";
interrupts = <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc", "tfe0";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
tfe0-supply = <&cam_cc_tfe_0_gdsc>;
clock-names =
"tfe_0_main_fast_ahb",
"tfe_0_clk_src",
"tfe_0_main_clk",
"cam_cc_camnoc_rt_tfe_0_main_clk",
"tfe_0_bayer_fast_ahb",
"tfe_0_bayer_clk",
"cam_cc_camnoc_rt_tfe_0_bayer_clk";
clocks =
<&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_0_CLK_SRC>,
<&camcc CAM_CC_TFE_0_MAIN_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
<&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_0_BAYER_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK>;
clock-rates =
<0 360280000 0 0 0 0 0>,
<0 480000000 0 0 0 0 0>,
<0 630000000 0 0 0 0 0>,
<0 716000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "tfe_0_clk_src";
clock-control-debugfs = "true";
ubwc-static-cfg = <0x1026 0x1036>;
cam_hw_pid = <8 13 16 4>;
status = "ok";
};
cam_csid1: qcom,csid1@ad29000 {
cell-index = <1>;
compatible = "qcom,csid980";
reg-names = "csid";
reg = <0x0ad2a000 0x2b00>;
reg-cam-base = <0x12a000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "csid1";
interrupts = <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <1 0 0>;
clock-names =
"csid_clk_src",
"csid_clk",
"csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0 0>,
<400000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe1: qcom,ife1@ac96000 {
cell-index = <1>;
compatible = "qcom,mc_tfe980";
reg-names = "ife", "cam_camnoc_rt";
reg = <0x0ac96000 0x10000>,
<0x0ad90000 0x9000>;
reg-cam-base = <0x96000 0x19000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "tfe1";
interrupts = <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc", "tfe1";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
tfe1-supply = <&cam_cc_tfe_1_gdsc>;
clock-names =
"tfe_1_main_fast_ahb",
"tfe_1_clk_src",
"tfe_1_main_clk",
"cam_cc_camnoc_rt_tfe_1_main_clk",
"tfe_1_bayer_fast_ahb",
"tfe_1_bayer_clk",
"cam_cc_camnoc_rt_tfe_1_bayer_clk";
clocks =
<&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_1_CLK_SRC>,
<&camcc CAM_CC_TFE_1_MAIN_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
<&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_1_BAYER_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK>;
clock-rates =
<0 360280000 0 0 0 0 0>,
<0 480000000 0 0 0 0 0>,
<0 630000000 0 0 0 0 0>,
<0 716000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "tfe_1_clk_src";
clock-control-debugfs = "true";
ubwc-static-cfg = <0x1026 0x1036>;
cam_hw_pid = <9 14 17 5>;
status = "ok";
};
cam_csid2: qcom,csid2@ad2c000 {
cell-index = <2>;
compatible = "qcom,csid980";
reg-names = "csid";
reg = <0x0ad2d000 0x2b00>;
reg-cam-base = <0x12d000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "csid2";
interrupts = <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <1 0 0>;
clock-names =
"csid_clk_src",
"csid_clk",
"csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CSID_CLK_SRC>,
<&camcc CAM_CC_CSID_CLK>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0 0>,
<400000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>,
<480000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe2: qcom,ife2@aca6000 {
cell-index = <2>;
compatible = "qcom,mc_tfe980";
reg-names = "ife", "cam_camnoc_rt";
reg = <0x0aca6000 0x10000>,
<0x0ad90000 0x9000>;
reg-cam-base = <0xa6000 0x19000>;
rt-wrapper-base = <0x86000>;
interrupt-names = "tfe2";
interrupts = <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc", "tfe2";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
tfe2-supply = <&cam_cc_tfe_2_gdsc>;
clock-names =
"tfe_2_main_fast_ahb",
"tfe_2_clk_src",
"tfe_2_main_clk",
"cam_cc_camnoc_rt_tfe_2_main_clk",
"tfe_2_bayer_fast_ahb",
"tfe_2_bayer_clk",
"cam_cc_camnoc_rt_tfe_2_bayer_clk";
clocks =
<&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_2_CLK_SRC>,
<&camcc CAM_CC_TFE_2_MAIN_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
<&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>,
<&camcc CAM_CC_TFE_2_BAYER_CLK>,
<&camcc CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK>;
clock-rates =
<0 360280000 0 0 0 0 0>,
<0 480000000 0 0 0 0 0>,
<0 630000000 0 0 0 0 0>,
<0 716000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>,
<0 833000000 0 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "tfe_2_clk_src";
clock-control-debugfs = "true";
ubwc-static-cfg = <0x1026 0x1036>;
cam_hw_pid = <10 12 18 6>;
status = "ok";
};
cam_csid_lite0: qcom,csid-lite0@ad6c000 {
cell-index = <3>;
compatible = "qcom,csid-lite980";
reg-names = "csid-lite";
reg = <0x0ad6d000 0xa00>;
reg-cam-base = <0x16d000>;
rt-wrapper-base = <0x16c000>;
interrupt-names = "csid-lite0";
interrupts = <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <0 1 0 0 0 0>;
clock-names =
"ife_lite_ahb",
"ife_lite_csid_clk_src",
"ife_lite_csid_clk",
"ife_lite_cphy_rx_clk",
"ife_lite_clk",
"cam_cc_camnoc_rt_ife_lite_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>;
clock-rates =
<0 266666667 0 0 0 0>,
<0 400000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "ife_lite_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe_lite0: qcom,ife-lite0@ad6c000 {
cell-index = <3>;
compatible = "qcom,vfe-lite980";
reg-names = "ife-lite";
reg = <0x0ad6d000 0x2800>;
reg-cam-base = <0x16d000>;
rt-wrapper-base = <0x16c000>;
interrupt-names = "ife-lite0";
interrupts = <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <0 0 0 1 0 0>;
clock-names =
"ife_lite_ahb",
"ife_lite_csid_clk",
"ife_lite_cphy_rx_clk",
"ife_lite_clk_src",
"ife_lite_clk",
"cam_cc_camnoc_rt_ife_lite_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>;
clock-rates =
<0 0 0 266666667 0 0>,
<0 0 0 400000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "ife_lite_clk_src";
clock-control-debugfs = "true";
cam_hw_pid = <19>;
status = "ok";
};
cam_csid_lite1: qcom,csid-lite1@ad71000 {
cell-index = <4>;
compatible = "qcom,csid-lite980";
reg-names = "csid-lite";
reg = <0x0ad72000 0xa00>;
reg-cam-base = <0x172000>;
rt-wrapper-base = <0x16c000>;
interrupt-names = "csid-lite1";
interrupts = <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <0 1 0 0 0 0>;
clock-names =
"ife_lite_ahb",
"ife_lite_csid_clk_src",
"ife_lite_csid_clk",
"ife_lite_cphy_rx_clk",
"ife_lite_clk",
"cam_cc_camnoc_rt_ife_lite_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>;
clock-rates =
<0 266666667 0 0 0 0>,
<0 400000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>,
<0 480000000 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "ife_lite_csid_clk_src";
clock-control-debugfs = "true";
status = "ok";
};
cam_vfe_lite1: qcom,ife-lite1@ad71000 {
cell-index = <4>;
compatible = "qcom,vfe-lite980";
reg-names = "ife-lite";
reg = <0x0ad72000 0x2800>;
reg-cam-base = <0x172000>;
rt-wrapper-base = <0x16c000>;
interrupt-names = "ife-lite1";
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <0 0 0 1 0 0>;
clock-names =
"ife_lite_ahb",
"ife_lite_csid_clk",
"ife_lite_cphy_rx_clk",
"ife_lite_clk_src",
"ife_lite_clk",
"cam_cc_camnoc_rt_ife_lite_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>;
clock-rates =
<0 0 0 266666667 0 0>,
<0 0 0 400000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>,
<0 0 0 480000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs",
"svs_l1", "nominal", "turbo";
src-clock-name = "ife_lite_clk_src";
clock-control-debugfs = "true";
cam_hw_pid = <20>;
status = "ok";
};
cam_csiphy_tpg13: qcom,tpg13@ad8b000 {
cell-index = <13>;
phy-id = <0>;
compatible = "qcom,cam-tpg104";
reg-names = "tpg0", "cam_cpas_top";
reg = <0x0ad8b000 0x400>,
<0x0ac04000 0x1000>;
reg-cam-base = <0x18b000 0x04000>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
interrupt-names = "tpg0";
interrupts = <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>;
shared-clks = <1 0>;
clock-names =
"cphy_rx_clk_src",
"csid_csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0>,
<400000000 0>,
<480000000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
src-clock-name = "cphy_rx_clk_src";
status = "ok";
};
cam_csiphy_tpg14: qcom,tpg14@ad8c000 {
cell-index = <14>;
phy-id = <1>;
compatible = "qcom,cam-tpg104";
reg-names = "tpg1", "cam_cpas_top";
reg = <0x0ad8c000 0x400>,
<0x0ac04000 0x1000>;
reg-cam-base = <0x18c000 0x04000>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
interrupt-names = "tpg1";
interrupts = <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>;
shared-clks = <1 0>;
clock-names =
"cphy_rx_clk_src",
"csid_csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0>,
<400000000 0>,
<480000000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
src-clock-name = "cphy_rx_clk_src";
status = "ok";
};
cam_csiphy_tpg15: qcom,tpg15@ad8d000 {
cell-index = <15>;
phy-id = <2>;
compatible = "qcom,cam-tpg104";
reg-names = "tpg2", "cam_cpas_top";
reg = <0x0ad8d000 0x400>,
<0x0ac04000 0x1000>;
reg-cam-base = <0x18d000 0x04000>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
interrupt-names = "tpg2";
interrupts = <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
shared-clks = <1 0>;
clock-names =
"cphy_rx_clk_src",
"csid_csiphy_rx_clk";
clocks =
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>;
clock-rates =
<266666667 0>,
<400000000 0>,
<480000000 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "nominal";
src-clock-name = "cphy_rx_clk_src";
status = "ok";
};
qcom,cam-icp0 {
compatible = "qcom,cam-icp0";
cell-index = <0>;
compat-hw-name = "qcom,icp0",
"qcom,ipe0";
num-icp = <1>;
num-ipe = <1>;
status = "ok";
icp_pc_en;
icp_use_pil;
ipe_bps_pc_en;
synx_signaling_en;
};
qcom,cam-icp1 {
compatible = "qcom,cam-icp1";
cell-index = <1>;
compat-hw-name = "qcom,icp1",
"qcom,ofe";
num-icp = <1>;
num-ofe = <1>;
status = "ok";
icp_pc_en;
icp_use_pil;
ipe_bps_pc_en;
synx_signaling_en;
};
cam_icp0: qcom,icp0@ac05000 {
cell-index = <0>;
compatible = "qcom,cam-icp_v2_1";
icp-version = <0x0201>;
reg = <0x0ac06000 0x1000>,
<0x0ac09000 0x1000>;
reg-names = "icp_csr", "icp_wd0";
reg-cam-base = <0x6000 0x9000>;
interrupt-names = "icp";
interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
memory-region = <&camera_mem>;
clock-names =
"icp_ahb_clk",
"icp_clk_src",
"icp_clk",
"camcc_debug_clk";
clocks =
<&camcc CAM_CC_ICP_0_AHB_CLK>,
<&camcc CAM_CC_ICP_0_CLK_SRC>,
<&camcc CAM_CC_ICP_0_CLK>,
<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
clock-rates =
<0 300000000 0 0>,
<0 400000000 0 0>,
<0 480000000 0 0>,
<0 600000000 0 0>,
<0 600000000 0 0>,
<0 600000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
nrt-device;
src-clock-name = "icp_clk_src";
clock-control-debugfs = "true";
fw_name = "CAMERA_ICP";
ubwc-ipe-fetch-cfg = <0x3f083 0x3f083>;
ubwc-ipe-write-cfg = <0x1620F 0x1620F>;
qos-val = <0x808>;
fw-pas-id = <33>;
cam_hw_pid = <11>;
status = "ok";
};
cam_icp1: qcom,icp1@ac150000 {
cell-index = <1>;
compatible = "qcom,cam-icp_v2_1";
icp-version = <0x0201>;
reg = <0x0ac16000 0x1000>,
<0x0ac19000 0x1000>;
reg-names = "icp_csr", "icp_wd0";
reg-cam-base = <0x16000 0x19000>;
interrupt-names = "icp1";
interrupts = <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
memory-region = <&camera_2_mem>;
clock-names =
"icp_1_ahb_clk",
"icp_1_clk_src",
"icp_1_clk",
"camcc_debug_clk";
clocks =
<&camcc CAM_CC_ICP_1_AHB_CLK>,
<&camcc CAM_CC_ICP_1_CLK_SRC>,
<&camcc CAM_CC_ICP_1_CLK>,
<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
clock-rates =
<0 300000000 0 0>,
<0 400000000 0 0>,
<0 480000000 0 0>,
<0 600000000 0 0>,
<0 600000000 0 0>,
<0 600000000 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
nrt-device;
src-clock-name = "icp_1_clk_src";
clock-control-debugfs = "true";
fw_name = "CAMERA_ICP_1";
ubwc-ofe-fetch-cfg = <0x3f083 0x3f083>;
ubwc-ofe-write-cfg = <0x16209 0x16209>;
qos-val = <0x808>;
fw-pas-id = <50>;
cam_hw_pid = <10>;
status = "ok";
};
cam_ipe0: qcom,ipe0@ac42000 {
cell-index = <0>;
compatible = "qcom,cam-ipe680";
reg = <0x0ac42000 0x18000>;
reg-names = "ipe0_top";
reg-cam-base = <0x42000>;
regulator-names = "ipe0-vdd";
ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
clock-names =
"ipe_nps_ahb_clk",
"ipe_nps_fast_ahb_clk",
"ipe_pps_fast_ahb_clk",
"ipe_nps_clk_src",
"ipe_nps_clk",
"ipe_pps_clk",
"cam_cc_camnoc_nrt_ipe_nps_clk";
clocks =
<&camcc CAM_CC_IPE_NPS_AHB_CLK>,
<&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>,
<&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>,
<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
<&camcc CAM_CC_IPE_NPS_CLK>,
<&camcc CAM_CC_IPE_PPS_CLK>,
<&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>;
clock-rates =
<0 0 0 332500000 0 0 0>,
<0 0 0 475000000 0 0 0>,
<0 0 0 575000000 0 0 0>,
<0 0 0 675000000 0 0 0>,
<0 0 0 825000000 0 0 0>,
<0 0 0 825000000 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
nrt-device;
src-clock-name = "ipe_nps_clk_src";
clock-control-debugfs = "true";
cam_hw_pid = <15 14 26 27>;
status = "ok";
};
cam_ofe: qcom,ofe@ac2a000 {
cell-index = <0>;
compatible = "qcom,cam-ofe";
reg = <0x0ac2a000 0x18000>;
reg-names = "ofe0_top";
reg-cam-base = <0x2a000>;
regulator-names = "ofe0-vdd";
ofe0-vdd-supply = <&cam_cc_ofe_gdsc>;
clock-names =
"camnoc_nrt_ofe_anchor",
"camnoc_nrt_ofe_hdr",
"ofe_clk_src",
"ofe_main_clk",
"camnoc_nrt_ofe_main_clk",
"ofe_ahb_clk",
"ofe_anchor_clk",
"ofe_anchor_fast_ahb",
"ofe_hdr_fast_ahb",
"ofe_hdr_clk",
"ofe_main_fast_ahb";
clocks =
<&camcc CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK>,
<&camcc CAM_CC_CAMNOC_NRT_OFE_HDR_CLK>,
<&camcc CAM_CC_OFE_CLK_SRC>,
<&camcc CAM_CC_OFE_MAIN_CLK>,
<&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>,
<&camcc CAM_CC_OFE_AHB_CLK>,
<&camcc CAM_CC_OFE_ANCHOR_CLK>,
<&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>,
<&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>,
<&camcc CAM_CC_OFE_HDR_CLK>,
<&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>;
clock-rates =
<0 0 338800000 0 0 0 0 0 0 0 0>,
<0 0 484000000 0 0 0 0 0 0 0 0>,
<0 0 586000000 0 0 0 0 0 0 0 0>,
<0 0 688000000 0 0 0 0 0 0 0 0>,
<0 0 841000000 0 0 0 0 0 0 0 0>,
<0 0 841000000 0 0 0 0 0 0 0 0>;
clock-cntl-level = "lowsvsd1", "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
nrt-device;
src-clock-name = "ofe_clk_src";
clock-control-debugfs = "true";
cam_hw_pid = <13 28 6>;
status = "ok";
};
qcom,cam-jpeg {
compatible = "qcom,cam-jpeg";
compat-hw-name = "qcom,jpegenc0",
"qcom,jpegdma0";
num-jpeg-enc = <1>;
num-jpeg-dma = <1>;
status = "ok";
};
cam_jpeg_enc0: qcom,jpegenc0@ac25000 {
cell-index = <0>;
compatible = "qcom,cam_jpeg_enc_780";
reg-names = "jpegenc_hw", "cam_camnoc_nrt";
reg = <0x0ac25000 0x1000>,
<0x0ac62000 0x9200>;
reg-cam-base = <0x25000 0x62000>;
interrupt-names = "jpeg_enc0";
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <1 0 0>;
clock-names =
"jpegenc_clk_src",
"jpegenc_0_clk",
"jpegenc_1_clk";
clocks =
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_JPEG_0_CLK>,
<&camcc CAM_CC_JPEG_1_CLK>;
clock-rates = <600000000 0 0>;
src-clock-name = "jpegenc_clk_src";
clock-cntl-level = "nominal";
nrt-device;
cam_hw_pid = <17 19>;
cam_hw_rd_mid = <0>;
cam_hw_wr_mid = <1>;
status = "ok";
};
cam_jpeg_dma0: qcom,jpegdma0@ac26000 {
cell-index = <0>;
compatible = "qcom,cam_jpeg_dma_780";
reg-names = "jpegdma_hw", "cam_camnoc_nrt";
reg = <0x0ac26000 0x1000>,
<0x0ac62000 0x9200>;
reg-cam-base = <0x26000 0x62000>;
interrupt-names = "jpeg_dma0";
interrupts = <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>;
regulator-names = "gdsc";
gdsc-supply = <&cam_cc_titan_top_gdsc>;
shared-clks = <1 0 0>;
clock-names =
"jpegdma_clk_src",
"jpegdma_0_clk",
"jpegdma_1_clk";
clocks =
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_JPEG_0_CLK>,
<&camcc CAM_CC_JPEG_1_CLK>;
clock-rates = <600000000 0 0>;
src-clock-name = "jpegdma_clk_src";
clock-cntl-level = "nominal";
nrt-device;
cam_hw_pid = <16 18>;
cam_hw_rd_mid = <0>;
cam_hw_wr_mid = <1>;
status = "ok";
};
};
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