03f3cfccb9
Add display cesta related DT node on kera target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d Signed-off-by: Sailesh Reddy Male <quic_reddymal@quicinc.com>
91 lines
2.4 KiB
Plaintext
91 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include "kera-sde-common.dtsi"
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&soc {
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/* dummy display clock provider */
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clock_cpucc: qcom,cpucc {
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compatible = "qcom,dummycc";
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clock-output-names = "cpucc_clocks";
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#clock-cells = <1>;
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x804 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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dma-coherent;
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};
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};
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&mdss_mdp {
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reg = <0x0ae00000 0x93800>,
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<0x0aeb0000 0x2008>,
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<0x0af80000 0x7000>,
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<0x0ae44000 0x02c>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"sid_phys";
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qcom,sde-vm-exclude-reg-names = "sid_phys";
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qcom,tvm-include-reg = <0x0af20000 0x850>,
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<0xaf30000 0x60>,
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<0xaf31000 0x30>,
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<0xaf32000 0x30>,
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<0xaf33000 0x30>,
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<0xaf34000 0x30>,
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<0xaf35000 0x30>,
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<0xaf36000 0x30>;
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qcom,sde-hw-version = <0xC0040000>;
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clocks = <&clock_cpucc GCC_DISP_AHB_CLK>,
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<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
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<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
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<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk",
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"core_clk", "vsync_clk", "lut_clk";
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qcom,sde-trusted-vm-env;
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};
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&mdss_dsi0 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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};
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&mdss_dsi1 {
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clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
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<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
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<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk";
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};
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&mdss_dsi_phy0 {
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qcom,dsi-pll-in-trusted-vm;
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};
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&mdss_dsi_phy1 {
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qcom,dsi-pll-in-trusted-vm;
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};
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