eee44c7cf2
Add support for platforms like ATP, CDP, MTP, QRD and RCM for TUIVM and OEMVM on Kera. Also, add support for additional Kera variant. Change-Id: I872c5a535c7bf79c5c9923f383796f7f70de5897 Signed-off-by: Hrishabh Rajput <quic_hrishabh@quicinc.com>
418 lines
9.6 KiB
Plaintext
418 lines
9.6 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <659 0x10000>, <686 0x10000>;
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interrupt-parent = <&vgic>;
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chosen {
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bootargs = "nokaslr log_buf_len=256K console=hvc0 loglevel=8 swiotlb=noforce";
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Medium C4 latencies */
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compatible = "arm,idle-state";
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status = "disabled";
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};
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CLUSTER_PWR_DWN: ss3 { /* C4+CL5+SS3 */
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compatible = "arm,idle-state";
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status = "disabled";
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};
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "QTI";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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qcom,qtee-config-info = "p=3,9,C,39,77,78,7C,8F,96,97,C8,FE,10C,11B,159,199,47E,7F1,CDF;";
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qcom,secdomain-ids = <45>;
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qcom,primary-vm-index = <0>;
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vm-uri = "vmuid/trusted-ui";
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vm-guid = "598085da-c516-5b25-a9c1-927a02819770";
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qcom,sensitive;
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vm-attrs = "context-dump", "crash-restart";
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iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
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0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
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/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
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* QUP1_SE4: GPII5 : IRQ_316
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* QUP2_SE7: GPII5 : IRQ_625
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*/
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gic-irq-ranges = <316 316
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625 625 /* PVM->SVM IRQ transfer */
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279 279>;
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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/*
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* IPA address linux image is loaded at. Must be within
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* first 1GB due to memory hotplug requirement.
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*/
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base-address = <0x0 0x88800000 >;
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};
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segments {
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config_cpio = <2>;
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};
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vcpus {
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config = "/cpus";
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affinity = "proxy";
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affinity-map = <0x0 0x0>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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minidump {
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vdevice-type = "minidump";
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push-compatible = "qcom,minidump_rm";
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minidump_allowed;
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};
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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virtio-mmio@0 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x1>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x0>;
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memory {
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qcom,label = <0x11>; //for persist.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6F8000>;
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};
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};
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virtio-mmio@1 {
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vdevice-type = "virtio-mmio";
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generate = "/virtio-mmio";
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peer-default;
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vqs-num = <0x2>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x4000>;
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memory {
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qcom,label = <0x10>; //for system.img
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#address-cells = <0x2>;
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base = <0x0 0xDA6FC000>;
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};
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};
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virtio-mmio@2 {
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vdevice-type = "virtio-mmio";
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patch = "/soc/virtio-mmio";
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peer-default;
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vqs-num = <0x3>;
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push-compatible = "virtio,mmio";
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dma-coherent;
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dma_base = <0x0 0x8000>;
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memory {
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qcom,label = <0x15>; //for virtio-vsock
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#address-cells = <0x2>;
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base = <0x0 0xDA700000>;
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};
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};
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swiotlb-shm {
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vdevice-type = "shm";
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generate = "/swiotlb";
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push-compatible = "swiotlb";
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peer-default;
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dma_base = <0x0 0x14000>;
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memory {
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qcom,label = <0x12>;
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#address-cells = <0x2>;
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base = <0x0 0xDA70c000>;
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};
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};
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vrtc {
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vdevice-type = "vrtc-pl031";
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peer-default;
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allocate-base;
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};
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};
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};
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firmware: firmware {
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qcom_scm: qcom_scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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virtio-mmio {
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wakeup-source;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x200000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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qcom,custom-bridge-size = <64>;
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qcom,support-hypervisor;
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};
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/*
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* QUP1 : SE0 - Secondary touch
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* QUP2 : SE0 - Primary touch
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*/
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qup_iommu_group: qup_common_iommu_group {
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iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
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<&qupv3_1 0x00000000 0x00020000>,
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<&gpi_dma2 0x00000000 0x00020000>,
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<&qupv3_2 0x00000000 0x00020000>;
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};
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/* GPI Instance */
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gpi_dma1: qcom,gpi-dma@a00000 {
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compatible = "qcom,gpi-dma";
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reg = <0xa00000 0x60000>;
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#dma-cells = <5>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0xb8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,static-gpii-mask = <0x20>;
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qcom,gpii-mask = <0x0>;
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qcom,ev-factor = <1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_1 wrapper instance */
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qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0xac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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iommus = <&apps_smmu 0xb8 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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ranges;
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status = "ok";
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/* Secondary Tounch */
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qupv3_se0_i2c: i2c@a80000 {
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compatible = "qcom,i2c-geni";
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reg = <0xa80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma1 0 0 3 64 0xc>,
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<&gpi_dma1 1 0 3 64 0xc>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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/* Secondary Touch */
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qupv3_se0_spi: spi@a80000 {
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compatible = "qcom,spi-geni";
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reg = <0xa80000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma1 0 0 1 64 0xc>,
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<&gpi_dma1 1 0 1 64 0xc>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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/* GPI Instance */
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gpi_dma2: qcom,gpi-dma@800000 {
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compatible = "qcom,gpi-dma";
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reg = <0x800000 0x60000>;
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#dma-cells = <5>;
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reg-names = "gpi-top";
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iommus = <&apps_smmu 0x438 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,static-gpii-mask = <0x20>;
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qcom,gpii-mask = <0x0>;
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qcom,ev-factor = <1>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok";
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};
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/* QUPv3_2 wrapper instance */
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qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x8c0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
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iommus = <&apps_smmu 0x438 0x0>;
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qcom,iommu-group = <&qup_iommu_group>;
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dma-coherent;
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ranges;
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status = "ok";
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/* Touchscreen I2C Instance */
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qupv3_se8_i2c: i2c@880000 {
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compatible = "qcom,i2c-geni";
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reg = <0x880000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma2 0 0 3 64 0xc>,
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<&gpi_dma2 1 0 3 64 0xc>;
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dma-names = "tx", "rx";
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qcom,le-vm;
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status = "disabled";
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};
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/* Touchscreen SPI Instance */
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qupv3_se8_spi: spi@880000 {
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compatible = "qcom,spi-geni";
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reg = <0x880000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "se_phys";
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dmas = <&gpi_dma2 0 0 1 64 0xc>,
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<&gpi_dma2 1 0 1 64 0xc>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,le-vm;
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status = "disabled";
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};
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};
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};
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#include "msm-arm-smmu-kera-vm.dtsi"
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