ee7d6850f6
git-subtree-dir: qcom/graphics git-subtree-mainline:2bb579edb5git-subtree-split:96de6303a2
82 lines
2.9 KiB
Plaintext
82 lines
2.9 KiB
Plaintext
Qualcomm Technologies, Inc. GPU IOMMU
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Required properties:
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Required properties:
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- compatible : one of:
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- "qcom,kgsl-smmu-v1"
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- "qcom,kgsl-smmu-v2"
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- reg : Base address and size of the SMMU.
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- clocks : List of clocks to be used during SMMU register access. See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for information about the format. For each clock specified
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here, there must be a corresponding entry in clock-names
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(see below).
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- clock-names : List of clock names corresponding to the clocks specified in
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the "clocks" property (above). See
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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for more info.
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- qcom,protect : The GPU register region which must be protected by a CP
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protected mode. On some targets this region must cover
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the entire SMMU register space, on others there
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is a separate aperture for CP to program context banks.
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Optional properties:
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- qcom,retention : A boolean specifying if retention is supported on this target
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- qcom,global_pt : A boolean specifying if global pagetable should be used.
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When not set we use per process pagetables
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- qcom,hyp_secure_alloc : A bool specifying if the hypervisor is used on this target
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for secure buffer allocation
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- List of sub nodes, one for each of the translation context banks supported.
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The driver uses the names of these nodes to determine how they are used,
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currently supported names are:
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- gfx3d_user : Used for the 'normal' GPU address space.
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- gfx3d_secure : Used for the content protection address space.
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- gfx3d_secure_alt : Used for the content protection address space for alternative SID.
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Each sub node has the following required properties:
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- compatible : "qcom,smmu-kgsl-cb"
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- iommus : Specifies the SID's used by this context bank, this needs to be
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<kgsl_smmu SID> pair, kgsl_smmu is the string parsed by iommu
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driver to match this context bank with the kgsl_smmu device
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defined in iommu device tree. On targets where the msm iommu
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driver is used rather than the arm smmu driver, this property
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may be absent.
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Example:
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msm_iommu: qcom,kgsl-iommu@2ca0000 {
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compatible = "qcom,kgsl-smmu-v2";
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reg = <0x2ca0000 0x10000>;
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qcom,protect = <0xa0000 0xc000>;
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clocks = <&clock_mmss clk_gpu_ahb_clk>,
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<&clock_gcc clk_gcc_mmss_bimc_gfx_clk>,
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<&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>;
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clock-names = "gpu_ahb_clk", "bimc_gfx_clk", "mmagic_ahb_clk", "mmagic_cfg_ahb_clk";
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qcom,secure_align_mask = <0xfff>;
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qcom,retention;
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qcom,global_pt;
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gfx3d_user: gfx3d_user {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 0>,
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<&kgsl_smmu 1>;
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};
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gfx3d_secure: gfx3d_secure {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 2>;
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};
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gfx3d_secure_alt: gfx3d_secure_alt {
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compatible = "qcom,smmu-kgsl-cb";
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iommus = <&kgsl_smmu 2>, <&kgsl_smmu 1>;
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};
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};
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