e684cfa2ed
Add stub regulator devices for the SMPS, LDO, and BOB regulators found on the PMICs used on kera boards to allow the regulator clients to vote on them. Change-Id: I1ff88145cdfb7111e473653d4a26e332f93267a8 Signed-off-by: Kavya Nunna <quic_knunna@quicinc.com>
913 lines
20 KiB
Plaintext
913 lines
20 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,cambistmclkcc-sun.h>
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#include <dt-bindings/clock/qcom,camcc-sun.h>
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#include <dt-bindings/clock/qcom,dispcc-tuna.h>
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#include <dt-bindings/clock/qcom,gcc-kera.h>
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#include <dt-bindings/clock/qcom,gpucc-kera.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include <dt-bindings/clock/qcom,videocc-tuna.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Kera";
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compatible = "qcom,kera";
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qcom,msm-id = <659 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory {
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device_type = "memory";
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reg = <0 0 0 0>;
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};
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chosen: chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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};
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reserved_memory: reserved-memory {};
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firmware: firmware {
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qcom_scm: qcom_scm { };
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};
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aliases {
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serial0 = &qupv3_se13_2uart;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "spin-table"; /* TODO: Update to psci */
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cpu-release-addr = <0x0 0xE3940000>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU3>;
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};
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core1 {
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cpu = <&CPU4>;
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};
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core2 {
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cpu = <&CPU5>;
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};
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core3 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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};
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&firmware {
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qcom_scm {
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compatible = "qcom,scm";
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qcom,dload-mode = <&tcsr 0x19000>;
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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};
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};
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#include "kera-reserved-memory.dtsi"
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#include "msm-arm-smmu-kera.dtsi"
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#include "kera-dma-heaps.dtsi"
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17100000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x17100000 0x10000>, /* GICD */
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<0x17180000 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17420000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17420000 0x1000>;
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clock-frequency = <19200000>;
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frame@17421000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17421000 0x1000>,
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<0x17422000 0x1000>;
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};
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frame@17423000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17423000 0x1000>;
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status = "disabled";
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};
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frame@17425000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17425000 0x1000>;
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status = "disabled";
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};
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frame@17427000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17427000 0x1000>;
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status = "disabled";
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};
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frame@17429000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17429000 0x1000>;
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status = "disabled";
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};
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frame@1742b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742b000 0x1000>;
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status = "disabled";
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};
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frame@1742d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1742d000 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@17a00000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x17a00000 0x10000>,
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<0x17a10000 0x10000>,
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<0x17a20000 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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qcom,drv-count = <3>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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apps_rsc_drv2: drv@2 {
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qcom,drv-id = <2>;
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qcom,tcs-offset = <0xd00>;
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qcom,tcs-distance = <0x2a0>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 3>,
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<SLEEP_TCS 2>,
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<WAKE_TCS 2>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 1>;
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};
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};
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};
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disp_rsc: rsc@af20000 {
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label = "disp_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0xaf20000 0x1000>;
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reg-names = "drv-0";
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qcom,drv-count = <1>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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disp_rsc_drv0: drv@0 {
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qcom,drv-id = <0>;
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qcom,tcs-offset = <0x520>;
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qcom,tcs-distance = <0x150>;
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channel@0 {
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qcom,tcs-config = <ACTIVE_TCS 0>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>,
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<FAST_PATH_TCS 0>;
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};
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,kera-pdc", "qcom,pdc";
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reg = <0xb220000 0x10000>, <0x17c000f0 0x60>;
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qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>,
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<10 230 1>, <11 724 1>, <12 716 1>,
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<13 727 1>, <14 720 1>, <15 726 1>,
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<16 721 1>, <17 262 1>, <18 70 1>,
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<19 723 1>, <20 234 1>, <22 725 1>,
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<23 231 1>, <24 504 5>, <30 510 8>,
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<40 520 6>, <51 531 4>, <58 538 2>,
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<61 541 5>, <66 92 1>, <67 547 13>,
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<80 240 1>, <81 235 1>, <82 310 2>,
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<84 248 1>, <85 241 1>, <86 238 2>,
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<88 254 1>, <89 509 1>, <90 563 1>,
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<91 259 2>, <93 201 1>, <94 246 1>,
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<95 93 1>, <96 611 29>, <125 63 1>,
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<126 366 2>, <128 374 1>, <129 377 1>,
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<130 428 1>, <131 434 2>, <133 437 1>,
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<134 452 2>, <136 458 2>, <138 464 11>,
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<149 671 1>, <150 688 1>, <151 714 2>,
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<153 722 1>, <154 255 1>, <155 269 2>,
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<157 276 1>, <158 287 1>, <159 306 4>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,kera-tlmm";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wakeup-parent = <&pdc>;
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qcom,gpios-reserved = <20 21 22 23 100 111 112 116>;
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};
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tcsr_mutex_block: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x1f40000 0x20000>;
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_block 0 0x1000>;
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#hwlock-cells = <1>;
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};
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ipcc_mproc: qcom,ipcc@406000 {
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compatible = "qcom,ipcc";
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reg = <0x406000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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aoss_qmp: power-controller@c300000 {
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compatible = "qcom,aoss-qmp";
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reg = <0xc300000 0x400>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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#power-domain-cells = <1>;
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#clock-cells = <0>;
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};
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qmp_aop: qcom,qmp-aop {
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compatible = "qcom,qmp-mbox";
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qcom,qmp = <&aoss_qmp>;
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label = "aop";
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#mbox-cells = <1>;
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};
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qmp_tme: qcom,qmp-tme {
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compatible = "qcom,qmp-mbox";
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qcom,remote-pid = <14>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP>;
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mbox-names = "tme_qmp";
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_TME
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IPCC_MPROC_SIGNAL_GLINK_QMP
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IRQ_TYPE_EDGE_RISING>;
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label = "tme";
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qcom,early-boot;
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priority = <0>;
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mbox-desc-offset = <0x0>;
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#mbox-cells = <1>;
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};
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cache-controller@24800000 {
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compatible = "qcom,kera-llcc";
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reg = <0x24800000 0x200000>, <0x24C00000 0x200000>,
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<0x26800000 0x200000>, <0x26C00000 0x200000>;
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reg-names = "llcc0_base", "llcc2_base",
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"llcc_broadcast_or_base", "llcc_broadcast_and_base";
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interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
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cap-based-alloc-and-pwr-collapse;
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};
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tcsr: syscon@1fc0000 {
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compatible = "syscon";
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reg = <0x1fc0000 0x30000>;
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};
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qcom,smp2p-adsp {
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compatible = "qcom,smp2p";
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qcom,smem = <443>, <429>;
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interrupt-parent = <&ipcc_mproc>;
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interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
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IRQ_TYPE_EDGE_RISING>;
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mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
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IPCC_MPROC_SIGNAL_SMP2P>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <2>;
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adsp_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
sleepstate_smp2p_out: sleepstate-out {
|
|
qcom,entry-name = "sleepstate";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
sleepstate_smp2p_in: qcom,sleepstate-in {
|
|
qcom,entry-name = "sleepstate_see";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
|
|
qcom,smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
|
|
qcom,entry-name = "ipa";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
/* ipa - inbound entry from mss */
|
|
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
|
|
qcom,entry-name = "ipa";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_smem_mailbox_1_out: qcom,smp2p-smem-mailbox-1-out {
|
|
qcom,entry-name = "smem-mailbox";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_smem_mailbox_1_in: qcom,smp2p-smem-mailbox-1-in {
|
|
qcom,entry-name = "smem-mailbox";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-soccp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_SOCCP IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <19>;
|
|
|
|
soccp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
soccp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <&sleepstate_smp2p_out 0>;
|
|
interrupt-parent = <&sleepstate_smp2p_in>;
|
|
interrupts = <0 0>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
eud: qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupt-parent = <&pdc>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x88e0000 0x2000>,
|
|
<0x88e2000 0x1000>;
|
|
reg-names = "eud_base", "eud_mode_mgr2";
|
|
qcom,secure-eud-en;
|
|
qcom,eud-utmi-delay = /bits/ 16 <255>;
|
|
status = "ok";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem_heap>;
|
|
restrict-access;
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo_board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie_0_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_1_pipe_clk: pcie_1_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_rx_symbol_1_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "ufs_phy_tx_symbol_0_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "fixed-clock";
|
|
clock-output-names = "rpmh_clocks";
|
|
clock-frequency = <19200000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cambistmclkcc: clock-controller@1760000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "cambistmclkcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ade0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "dispcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gpucc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
tcsrcc: clock-controller@1f40000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "tcsrcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@aaf0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "videocc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
#include "tuna-gdsc.dtsi"
|
|
|
|
&cam_cc_ipe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_ofe_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_tfe_2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&cam_cc_titan_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&disp_cc_mdss_core_int2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_0_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_pcie_1_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_mem_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gcc_usb3_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc_hw_ctrl {
|
|
reg = <0x3d99124 0x4>;
|
|
};
|
|
|
|
&gpu_cc_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0x3d99110 0x4>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cc_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&video_cc_mvs0c_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok";
|
|
};
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
reg = <0x0 0x81c60000 0x0 0x20000>;
|
|
};
|
|
|
|
adsp_mem_heap: adsp_heap_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0xC00000>;
|
|
};
|
|
|
|
cdsp_secure_heap_cma: secure_cdsp_region { /* Secure DSP */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x4800000>;
|
|
};
|
|
};
|
|
|
|
#include "kera-pinctrl.dtsi"
|
|
#include "kera-stub-regulators.dtsi"
|
|
#include "kera-usb.dtsi"
|
|
#include "kera-qupv3.dtsi"
|
|
|
|
&qupv3_se13_2uart {
|
|
status = "ok";
|
|
};
|