a2a1c398f5
Add a description for the "qcom,mid" property which corresponds to the SPMI master ID of the SPMI PMIC arbiter controller. It is most useful in systems with multiple masters, e.g. when there are multiple SoCs connected to a single SPMI bus. Change-Id: I376e6f569f9bbea44ba3930480a330fb1dd2c2de Signed-off-by: Ayyagari Ushasreevalli <quic_aushasre@quicinc.com>
125 lines
2.9 KiB
YAML
125 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm SPMI Controller (PMIC Arbiter)
|
|
|
|
maintainers:
|
|
- Stephen Boyd <sboyd@kernel.org>
|
|
|
|
description: |
|
|
The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
|
|
controller with wrapping arbitration logic to allow for multiple on-chip
|
|
devices to control a single SPMI master.
|
|
|
|
The PMIC Arbiter can also act as an interrupt controller, providing interrupts
|
|
to slave devices.
|
|
|
|
allOf:
|
|
- $ref: spmi.yaml
|
|
|
|
properties:
|
|
compatible:
|
|
const: qcom,spmi-pmic-arb
|
|
|
|
reg:
|
|
oneOf:
|
|
- items: # V1
|
|
- description: core registers
|
|
- description: interrupt controller registers
|
|
- description: configuration registers
|
|
- items: # V2
|
|
- description: core registers
|
|
- description: tx-channel per virtual slave regosters
|
|
- description: rx-channel (called observer) per virtual slave registers
|
|
- description: interrupt controller registers
|
|
- description: configuration registers
|
|
|
|
reg-names:
|
|
oneOf:
|
|
- items:
|
|
- const: core
|
|
- const: intr
|
|
- const: cnfg
|
|
- items:
|
|
- const: core
|
|
- const: chnls
|
|
- const: obsrvr
|
|
- const: intr
|
|
- const: cnfg
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
interrupt-names:
|
|
const: periph_irq
|
|
|
|
interrupt-controller: true
|
|
|
|
'#address-cells': true
|
|
|
|
'#interrupt-cells':
|
|
const: 4
|
|
description: |
|
|
cell 1: slave ID for the requested interrupt (0-15)
|
|
cell 2: peripheral ID for requested interrupt (0-255)
|
|
cell 3: the requested peripheral interrupt (0-7)
|
|
cell 4: interrupt flags indicating level-sense information,
|
|
as defined in dt-bindings/interrupt-controller/irq.h
|
|
|
|
'#size-cells': true
|
|
|
|
qcom,ee:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
minimum: 0
|
|
maximum: 5
|
|
description: >
|
|
indicates the active Execution Environment identifier
|
|
|
|
qcom,channel:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
minimum: 0
|
|
maximum: 5
|
|
description: >
|
|
which of the PMIC Arb provided channels to use for accesses
|
|
|
|
qcom,mid:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
minimum: 0
|
|
maximum: 3
|
|
description: >
|
|
SPMI master ID of this controller.
|
|
|
|
required:
|
|
- compatible
|
|
- reg-names
|
|
- qcom,ee
|
|
- qcom,channel
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
spmi@fc4cf000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg-names = "core", "intr", "cnfg";
|
|
reg = <0xfc4cf000 0x1000>,
|
|
<0xfc4cb000 0x1000>,
|
|
<0xfc4ca000 0x1000>;
|
|
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <0 190 0>;
|
|
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|