0c7716908d
Snapshot the gic interrupt router documentation from
qcom-6.1 commit e3266c8e04f8 ("dt-bindings: Add device-tree
bindings for gic-interrupt-router").
Change-Id: I5ad2acfe88680f77d85131bd52383674d118bcd3
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
37 lines
976 B
YAML
37 lines
976 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/qcom/qcom,gic-interrupt-router.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. GIC Interrupt Router
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description: |
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The ARM GIC peripheral supports "1 of N" selection of SPI interrupts. CPUs
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may be classified as class0 and/or class1 and SPIs may be routed to any CPU
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in a particular class.
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properties:
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compatible:
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const: "qcom,gic-intr-routing"
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Usage: required
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qcom,gic-class0-cpus:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of CPUs in GIC class 0.
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qcom,gic-class1-cpus:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: List of CPUs in GIC class 1.
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examples:
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- |
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qcom,gic-interrupt-router {
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compatible = "qcom,gic-intr-routing";
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qcom,gic-class0-cpus = <0 1 2 3>;
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qcom,gic-class1-cpus = <4 5 6 7>;
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};
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...
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