6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
58 lines
1.4 KiB
YAML
58 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
|
|
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|
|
|
title: MediaTek System Clock Controller for MT8186
|
|
|
|
maintainers:
|
|
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
|
|
|
description: |
|
|
The clock architecture in MediaTek like below
|
|
PLLs -->
|
|
dividers -->
|
|
muxes
|
|
-->
|
|
clock gate
|
|
|
|
The apmixedsys provides most of PLLs which generated from SoC 26m.
|
|
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
|
|
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
|
The mcusys provides mux control to select the clock source in AP MCU.
|
|
The device nodes also provide the system control capacity for configuration.
|
|
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- enum:
|
|
- mediatek,mt8186-mcusys
|
|
- mediatek,mt8186-topckgen
|
|
- mediatek,mt8186-infracfg_ao
|
|
- mediatek,mt8186-apmixedsys
|
|
- const: syscon
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
'#clock-cells':
|
|
const: 1
|
|
|
|
'#reset-cells':
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
topckgen: syscon@10000000 {
|
|
compatible = "mediatek,mt8186-topckgen", "syscon";
|
|
reg = <0x10000000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|