6f18ce8026
Add snapshot of device tree bindings from keystone common kernel, branch
"android-mainline-keystone-qcom-release" at c4c12103f9c0 ("Snap for 9228065
from e32903b9a63bb558df8b803b076619c53c16baad to
android-mainline-keystone-qcom-release").
Change-Id: I7682079615cbd9f29340a5c1f2a1d84ec441a1f1
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
97 lines
2.4 KiB
Plaintext
97 lines
2.4 KiB
Plaintext
Binding for TI DaVinci PLL Controllers
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The PLL provides clocks to most of the components on the SoC. In addition
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to the PLL itself, this controller also contains bypasses, gates, dividers,
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an multiplexers for various clock signals.
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Required properties:
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- compatible: shall be one of:
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- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
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- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
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- reg: physical base address and size of the controller's register area.
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- clocks: phandles corresponding to the clock names
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- clock-names: names of the clock sources - depends on compatible string
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- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
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- for "ti,da850-pll1", shall be "clksrc"
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Optional properties:
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- ti,clkmode-square-wave: Indicates that the board is supplying a square
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wave input on the OSCIN pin instead of using a crystal oscillator.
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This property is only valid when compatible = "ti,da850-pll0".
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Optional child nodes:
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pllout
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Describes the main PLL clock output (before POSTDIV). The node name must
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be "pllout".
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Required properties:
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- #clock-cells: shall be 0
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sysclk
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Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
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domains. The node name must be "sysclk". Consumers of this node should
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use "n" in "SYSCLKn" as the index parameter for the clock cell.
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Required properties:
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- #clock-cells: shall be 1
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auxclk
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Describes the AUXCLK output of the PLL. The node name must be "auxclk".
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This child node is only valid when compatible = "ti,da850-pll0".
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Required properties:
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- #clock-cells: shall be 0
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obsclk
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Describes the OBSCLK output of the PLL. The node name must be "obsclk".
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Required properties:
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- #clock-cells: shall be 0
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Examples:
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pll0: clock-controller@11000 {
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compatible = "ti,da850-pll0";
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reg = <0x11000 0x1000>;
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clocks = <&ref_clk>, <&pll1_sysclk 3>;
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clock-names = "clksrc", "extclksrc";
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ti,clkmode-square-wave;
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pll0_pllout: pllout {
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#clock-cells = <0>;
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};
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pll0_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll0_auxclk: auxclk {
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#clock-cells = <0>;
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};
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pll0_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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pll1: clock-controller@21a000 {
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compatible = "ti,da850-pll1";
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reg = <0x21a000 0x1000>;
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clocks = <&ref_clk>;
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clock-names = "clksrc";
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pll0_sysclk: sysclk {
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#clock-cells = <1>;
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};
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pll0_obsclk: obsclk {
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#clock-cells = <0>;
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};
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};
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Also see:
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- Documentation/devicetree/bindings/clock/clock-bindings.txt
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