dd4580033b
Add stub regulator devices for the SMPS, LDO, and BOB regulators found on the PMIC chips which are used on Sun boards. This ensures that consumers can use the regulators successfully. Change-Id: I23a02c960adbb46b09c7648458d7c367636993c3 Signed-off-by: David Collins <quic_collinsd@quicinc.com>
765 lines
16 KiB
Plaintext
765 lines
16 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,camcc-sun.h>
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#include <dt-bindings/clock/qcom,dispcc-sun.h>
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#include <dt-bindings/clock/qcom,evacc-sun.h>
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#include <dt-bindings/clock/qcom,gcc-sun.h>
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#include <dt-bindings/clock/qcom,gpucc-sun.h>
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#include <dt-bindings/clock/qcom,gxclkctl-sun.h>
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#include <dt-bindings/clock/qcom,tcsrcc-sun.h>
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#include <dt-bindings/clock/qcom,videocc-sun.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Sun";
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compatible = "qcom,sun";
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qcom,msm-id = <618 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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chosen: chosen {
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bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7";
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};
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aliases { };
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firmware: firmware { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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};
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CPU6: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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};
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};
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CPU7: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_6>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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reserved_memory: reserved-memory { };
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soc: soc { };
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};
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&firmware {
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qcom-scm {
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compatible = "qcom,scm";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sun-tlmm";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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intc: interrupt-controller@16000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x16000000 0x10000>, /* GICD */
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<0x16080000 0x200000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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memtimer: timer@16800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x16800000 0x1000>;
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clock-frequency = <19200000>;
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frame@16801000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16801000 0x1000>,
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<0x16802000 0x1000>;
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};
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frame@16803000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16803000 0x1000>;
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status = "disabled";
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};
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frame@16805000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16805000 0x1000>;
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status = "disabled";
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};
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frame@16807000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16807000 0x1000>;
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status = "disabled";
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};
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frame@16809000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x16809000 0x1000>;
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status = "disabled";
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};
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frame@1680b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1680b000 0x1000>;
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status = "disabled";
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};
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frame@1680d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1680d000 0x1000>;
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status = "disabled";
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_0_pipe_clk: pcie_0_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_rx_symbol_0_clk";
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#clock-cells = <0>;
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};
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ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_rx_symbol_1_clk";
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#clock-cells = <0>;
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};
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ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "ufs_phy_tx_symbol_0_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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cxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clocks = <&xo_board>;
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clock-mult = <1>;
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clock-div = <4>;
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#clock-cells = <0>;
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clock-output-names = "bi_tcxo";
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};
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cxo_a: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clocks = <&xo_board>;
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clock-mult = <1>;
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clock-div = <4>;
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#clock-cells = <0>;
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clock-output-names = "bi_tcxo_ao";
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};
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rpmhcc: clock-controller {
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compatible = "fixed-clock";
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clock-output-names = "rpmh_clocks";
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clock-frequency = <19200000>;
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#clock-cells = <1>;
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};
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cambistmclkcc: clock-controller@1760000 {
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compatible = "qcom,dummycc";
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clock-output-names = "cambistmclkcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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camcc: clock-controller@ade0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "camcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,dummycc";
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clock-output-names = "dispcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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evacc: clock-controller@abf0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "evacc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gpucc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gxclkctl: clock-controller@3d64000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gxclkctl_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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tcsrcc: clock-controller@f100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "tcsrcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "videocc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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apsscc: syscon@16450000 {
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compatible = "syscon";
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reg = <0x16450000 0x3553000>;
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};
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mccc: syscon@240ba000 {
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compatible = "syscon";
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reg = <0x240ba000 0x800>;
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};
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/* CAM_CC GDSCs */
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cam_cc_ipe_0_gdsc: qcom,gdsc@adf017c {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_ipe_0_gdsc";
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qcom,support-hw-trigger;
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};
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cam_cc_ofe_gdsc: qcom,gdsc@adf00c8 {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_ofe_gdsc";
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qcom,support-hw-trigger;
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};
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cam_cc_tfe_0_gdsc: qcom,gdsc@adf1004 {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_tfe_0_gdsc";
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};
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cam_cc_tfe_1_gdsc: qcom,gdsc@adf1084 {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_tfe_1_gdsc";
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};
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cam_cc_tfe_2_gdsc: qcom,gdsc@adf10ec {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_tfe_2_gdsc";
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};
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cam_cc_titan_top_gdsc: qcom,gdsc@adf134c {
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compatible = "qcom,stub-regulator";
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regulator-name = "cam_cc_titan_top_gdsc";
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};
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/* DISP_CC GDSCs */
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disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
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compatible = "qcom,stub-regulator";
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regulator-name = "disp_cc_mdss_core_gdsc";
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qcom,support-hw-trigger;
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};
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disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
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compatible = "qcom,stub-regulator";
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regulator-name = "disp_cc_mdss_core_int2_gdsc";
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qcom,support-hw-trigger;
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};
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/* EVA_CC GDSCs */
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eva_cc_mvs0_gdsc: qcom,gdsc@abf8068 {
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compatible = "qcom,stub-regulator";
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regulator-name = "eva_cc_mvs0_gdsc";
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qcom,support-hw-trigger;
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};
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eva_cc_mvs0c_gdsc: qcom,gdsc@abf8034 {
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compatible = "qcom,stub-regulator";
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regulator-name = "eva_cc_mvs0c_gdsc";
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};
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/* GCC GDSCs */
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gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_pcie_0_gdsc";
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};
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gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_pcie_0_phy_gdsc";
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};
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gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_ufs_mem_phy_gdsc";
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};
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gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_ufs_phy_gdsc";
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};
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gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_usb30_prim_gdsc";
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};
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gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gcc_usb3_phy_gdsc";
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};
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/* GPU_CC GDSCs */
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gpu_cc_cx_gdsc_hw_ctrl: syscon@3d99094 {
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compatible = "syscon";
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reg = <0x3d99094 0x4>;
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};
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gpu_cc_cx_gdsc: qcom,gdsc@3d99080 {
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compatible = "qcom,stub-regulator";
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regulator-name = "gpu_cc_cx_gdsc";
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};
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/* GX_CLKCTL GDSCs */
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gx_clkctl_gx_gdsc: qcom,gdsc@3d68024 {
|
|
compatible = "qcom,stub-regulator";
|
|
regulator-name = "gx_clkctl_gx_gdsc";
|
|
};
|
|
|
|
/* VIDEO_CC GDSCs */
|
|
video_cc_mvs0_gdsc: qcom,gdsc@aaf8068 {
|
|
compatible = "qcom,stub-regulator";
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
|
qcom,support-hw-trigger;
|
|
};
|
|
|
|
video_cc_mvs0c_gdsc: qcom,gdsc@aaf8034 {
|
|
compatible = "qcom,stub-regulator";
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
|
};
|
|
};
|
|
|
|
&reserved_memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gunyah_hyp_mem: gunyah_hyp_region@80000000 {
|
|
no-map;
|
|
reg = <0x0 0x80000000 0x0 0xe00000>;
|
|
};
|
|
|
|
cpusys_vm_mem: cpusys_vm_region@80e00000 {
|
|
no-map;
|
|
reg = <0x0 0x80e00000 0x0 0x400000>;
|
|
};
|
|
|
|
cpucp_mem: cpucp_region@81200000 {
|
|
no-map;
|
|
reg = <0x0 0x81200000 0x0 0x200000>;
|
|
};
|
|
|
|
/*
|
|
* hyp_tags_mem is dynamically removed from the RAM
|
|
* partition tables before boot occurs. Size of region
|
|
* varies.
|
|
*/
|
|
|
|
/* merged xbl_dtlog, xbl_ramdump and aop_image regions */
|
|
xbl_aop_merged_mem: xbl_aop_merged_region@81a00000 {
|
|
no-map;
|
|
reg = <0x0 0x81a00000 0x0 0x260000>;
|
|
};
|
|
|
|
aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
|
|
compatible = "qcom,cmd-db";
|
|
no-map;
|
|
reg = <0x0 0x81c60000 0x0 0x20000>;
|
|
};
|
|
|
|
/* merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
|
|
aop_tme_uefi_merged_mem: aop_tme_uefi_merged_region@81c80000 {
|
|
no-map;
|
|
reg = <0x0 0x81c80000 0x0 0x74000>;
|
|
};
|
|
|
|
/* secdata region can be reused by apps */
|
|
|
|
smem_mem: smem_region@81d00000 {
|
|
no-map;
|
|
reg = <0x0 0x81d00000 0x0 0x200000>;
|
|
};
|
|
|
|
adsp_mhi_mem: adsp_mhi_region@81f00000 {
|
|
no-map;
|
|
reg = <0x0 0x81f00000 0x0 0x20000>;
|
|
};
|
|
|
|
cpucp_scandump_mem: cpucp_scandump_region@81f20000 {
|
|
no-map;
|
|
reg = <0x0 0x81f20000 0x0 0x380000>;
|
|
};
|
|
|
|
pdp_ns_shared_mem: pdp_ns_shared_region@822a0000 {
|
|
no-map;
|
|
reg = <0x0 0x822a0000 0x0 0x100000>;
|
|
};
|
|
|
|
soccp_sdi_mem: soccp_sdi_region@823a0000 {
|
|
no-map;
|
|
reg = <0x0 0x823a0000 0x0 0x40000>;
|
|
};
|
|
|
|
pmic_minii_dump_mem: pmic_minii_dump_region@823e0000 {
|
|
no-map;
|
|
reg = <0x0 0x823e0000 0x0 0x80000>;
|
|
};
|
|
|
|
pvm_fw_mem: pvm_fw_region@824a0000 {
|
|
no-map;
|
|
reg = <0x0 0x824a0000 0x0 0x100000>;
|
|
};
|
|
|
|
/* hyp_mem_database_mem is removed by HYP in the RAM partition table */
|
|
|
|
global_sync_mem: global_sync_region@82600000 {
|
|
no-map;
|
|
reg = <0x0 0x82600000 0x0 0x100000>;
|
|
};
|
|
|
|
tz_stat_mem: tz_stat_region@82700000 {
|
|
no-map;
|
|
reg = <0x0 0x82700000 0x0 0x100000>;
|
|
};
|
|
|
|
qdss_apps_mem: qdss_apps_region@82800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0x82800000 0x0 0x2000000>;
|
|
reusable;
|
|
};
|
|
|
|
dsm_partition_1_mem: dsm_partition_1_region@86b00000 {
|
|
no-map;
|
|
reg = <0x0 0x86b00000 0x0 0x4900000>;
|
|
};
|
|
|
|
dsm_partition_2_mem: dsm_partition_2_region@8b400000 {
|
|
no-map;
|
|
reg = <0x0 0x8b400000 0x0 0x800000>;
|
|
};
|
|
|
|
mpss_mem: mpss_region@8bc00000 {
|
|
no-map;
|
|
reg = <0x0 0x8bc00000 0x0 0xf400000>;
|
|
};
|
|
|
|
q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
|
|
no-map;
|
|
reg = <0x0 0x9b000000 0x0 0x80000>;
|
|
};
|
|
|
|
ipa_fw_mem: ipa_fw_region@9b080000 {
|
|
no-map;
|
|
reg = <0x0 0x9b080000 0x0 0x10000>;
|
|
};
|
|
|
|
ipa_gsi_mem: ipa_gsi_region@9b090000 {
|
|
no-map;
|
|
reg = <0x0 0x9b090000 0x0 0xa000>;
|
|
};
|
|
|
|
gpu_microcode_mem: gpu_microcode_region@9b09a000 {
|
|
no-map;
|
|
reg = <0x0 0x9b09a000 0x0 0x2000>;
|
|
};
|
|
|
|
spss_region_mem: spss_region_region@9b100000 {
|
|
no-map;
|
|
reg = <0x0 0x9b100000 0x0 0x180000>;
|
|
};
|
|
|
|
spu_secure_shared_memory_mem: spu_secure_shared_memory_region@9b280000 {
|
|
no-map;
|
|
reg = <0x0 0x9b280000 0x0 0x80000>;
|
|
};
|
|
|
|
camera_mem: camera_region@9b300000 {
|
|
no-map;
|
|
reg = <0x0 0x9b300000 0x0 0x800000>;
|
|
};
|
|
|
|
video_mem: video_region@9bb00000 {
|
|
no-map;
|
|
reg = <0x0 0x9bb00000 0x0 0x800000>;
|
|
};
|
|
|
|
cvp_mem: cvp_region@9c300000 {
|
|
no-map;
|
|
reg = <0x0 0x9c300000 0x0 0x700000>;
|
|
};
|
|
|
|
cdsp_mem: cdsp_region@9ca00000 {
|
|
no-map;
|
|
reg = <0x0 0x9ca00000 0x0 0x2000000>;
|
|
};
|
|
|
|
q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9ea00000 {
|
|
no-map;
|
|
reg = <0x0 0x9ea00000 0x0 0x80000>;
|
|
};
|
|
|
|
q6_adsp_dtb_mem: q6_adsp_dtb_region@9ea80000 {
|
|
no-map;
|
|
reg = <0x0 0x9ea80000 0x0 0x80000>;
|
|
};
|
|
|
|
adspslpi_mem: adspslpi_region@9eb00000 {
|
|
no-map;
|
|
reg = <0x0 0x9eb00000 0x0 0x4080000>;
|
|
};
|
|
|
|
soccp_mem: soccp_region@a2b80000 {
|
|
no-map;
|
|
reg = <0x0 0xa2b80000 0x0 0x100000>;
|
|
};
|
|
|
|
/* uefi region can be reused by apps */
|
|
|
|
/* Linux kernel image is loaded at 0xa8000000 */
|
|
|
|
/* merged tz_reserved, xbl_sc, and qtee regions */
|
|
tz_merged_mem: tz_merged_region@d8000000 {
|
|
no-map;
|
|
reg = <0x0 0xd8000000 0x0 0x600000>;
|
|
};
|
|
|
|
/*
|
|
* ta/tags mem is dynamically removed from the RAM
|
|
* partition tables before boot occurs. Size of region
|
|
* varies.
|
|
*/
|
|
|
|
trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0xf3800000 0x0 0x4400000>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
};
|
|
|
|
oem_vm_mem: oem_vm_region@f7c00000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0xf7c00000 0x0 0x4c00000>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
};
|
|
|
|
llcc_lpi_mem: llcc_lpi_region@ff800000 {
|
|
no-map;
|
|
reg = <0x0 0xff800000 0x0 0x800000>;
|
|
};
|
|
|
|
system_cma: linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0x0 0x400000>;
|
|
size = <0x0 0x400000>;
|
|
linux,cma-default;
|
|
};
|
|
};
|
|
|
|
#include "msm-arm-smmu-sun.dtsi"
|
|
#include "sun-pinctrl.dtsi"
|
|
#include "sun-regulators.dtsi"
|