168 lines
4.6 KiB
Plaintext
168 lines
4.6 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
|
|
|
|
&msm_gpu {
|
|
compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0";
|
|
status = "ok";
|
|
reg = <0x3d00000 0x40000>, <0x3d50000 0x10000>,
|
|
<0x3d61000 0x800>, <0x3d9e000 0x1000>,
|
|
<0x10048000 0x8000>, <0x10900000 0x80000>,
|
|
<0x10b05000 0x1000>;
|
|
reg-names = "kgsl_3d0_reg_memory", "rscc", "cx_dbgc",
|
|
"cx_misc", "qdss_etr", "qdss_gfx", "qdss_tmc";
|
|
|
|
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "kgsl_3d0_irq";
|
|
|
|
clocks = <&gcc GCC_GPU_GEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&aoss_qmp>;
|
|
clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb",
|
|
"gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk";
|
|
|
|
qcom,gpu-model = "Adreno716";
|
|
|
|
qcom,chipid = <0x43020100>;
|
|
|
|
qcom,min-access-length = <32>;
|
|
|
|
qcom,ubwc-mode = <4>;
|
|
|
|
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
|
|
interconnect-names = "gpu_icc_path";
|
|
|
|
qcom,bus-table-cnoc =
|
|
<0>, /* Off */
|
|
<100>; /* On */
|
|
|
|
qcom,bus-table-ddr7 =
|
|
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
|
<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
|
|
<MHZ_TO_KBPS(451, 4)>, /* LowSVS index=2 */
|
|
<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=3 */
|
|
<MHZ_TO_KBPS(681, 4)>, /* SVS index=4 */
|
|
<MHZ_TO_KBPS(768, 4)>, /* SVS index=5 */
|
|
<MHZ_TO_KBPS(1017, 4)>, /* SVS index=6 */
|
|
<MHZ_TO_KBPS(1353, 4)>, /* NOM index=7 */
|
|
<MHZ_TO_KBPS(1555, 4)>, /* NOM index=8 */
|
|
<MHZ_TO_KBPS(1708, 4)>, /* TURBO index=9 */
|
|
<MHZ_TO_KBPS(2092, 4)>; /* TURBO_L1 index=10 */
|
|
|
|
qcom,bus-table-ddr8 =
|
|
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
|
|
<MHZ_TO_KBPS(200, 4)>, /* LowSVS index=1 */
|
|
<MHZ_TO_KBPS(547, 4)>, /* LowSVS index=2 */
|
|
<MHZ_TO_KBPS(1353, 4)>, /* LowSVS index=3 */
|
|
<MHZ_TO_KBPS(1555, 4)>, /* SVS index=4 */
|
|
<MHZ_TO_KBPS(1708, 4)>, /* SVS index=5 */
|
|
<MHZ_TO_KBPS(2092, 4)>, /* SVS index=6 */
|
|
<MHZ_TO_KBPS(2736, 4)>, /* NOM index=7 */
|
|
<MHZ_TO_KBPS(3187, 4)>, /* TURBO index=8 */
|
|
<MHZ_TO_KBPS(3686, 4)>, /* TURBO index=9 */
|
|
<MHZ_TO_KBPS(4224, 4)>; /* TURBO_L1 index=10 */
|
|
|
|
zap-shader {
|
|
memory-region = <&gpu_microcode_mem>;
|
|
};
|
|
|
|
qcom,gpu-mempools {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "qcom,gpu-mempools";
|
|
|
|
/* 4K Page Pool configuration */
|
|
qcom,gpu-mempool@0 {
|
|
reg = <0>;
|
|
qcom,mempool-page-size = <4096>;
|
|
qcom,mempool-reserved = <2048>;
|
|
};
|
|
/* 8K Page Pool configuration */
|
|
qcom,gpu-mempool@1 {
|
|
reg = <1>;
|
|
qcom,mempool-page-size = <8192>;
|
|
qcom,mempool-reserved = <1024>;
|
|
};
|
|
/* 64K Page Pool configuration */
|
|
qcom,gpu-mempool@2 {
|
|
reg = <2>;
|
|
qcom,mempool-page-size = <65536>;
|
|
qcom,mempool-reserved = <256>;
|
|
};
|
|
/* 128K Page Pool configuration */
|
|
qcom,gpu-mempool@3 {
|
|
reg = <3>;
|
|
qcom,mempool-page-size = <131072>;
|
|
qcom,mempool-reserved = <128>;
|
|
};
|
|
/* 256K Page Pool configuration */
|
|
qcom,gpu-mempool@4 {
|
|
reg = <4>;
|
|
qcom,mempool-page-size = <262144>;
|
|
qcom,mempool-reserved = <80>;
|
|
};
|
|
/* 1M Page Pool configuration */
|
|
qcom,gpu-mempool@5 {
|
|
reg = <5>;
|
|
qcom,mempool-page-size = <1048576>;
|
|
qcom,mempool-reserved = <32>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&soc {
|
|
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
|
|
compatible = "qcom,kgsl-smmu-v2";
|
|
reg = <0x3da0000 0x40000>;
|
|
|
|
power-domains = <&gpucc GPU_CC_CX_GDSC>;
|
|
|
|
gfx3d_user: gfx3d_user {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 0x0 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
|
|
gfx3d_secure: gfx3d_secure {
|
|
compatible = "qcom,smmu-kgsl-cb";
|
|
iommus = <&kgsl_smmu 0x2 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|
|
|
|
gmu: qcom,gmu@3d68000 {
|
|
compatible = "qcom,gen7-gmu";
|
|
|
|
reg = <0x3d68000 0x37000>, <0xb290000 0x10000>, <0x3d40000 0x10000>;
|
|
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
|
|
|
|
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hfi", "gmu";
|
|
|
|
power-domains = <&gpucc GPU_CC_CX_GDSC>,
|
|
<&gpucc GPU_CC_CX_GMU_GDSC>,
|
|
<&gpucc GPU_CC_GX_GDSC>;
|
|
power-domain-names = "cx", "gmu_cx", "gx";
|
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_CXO_CLK>,
|
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
|
|
<&gcc GCC_GPU_GEMNOC_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
|
|
|
|
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
|
|
"memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote";
|
|
|
|
qcom,gmu-freq-table = <220000000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
|
|
<550000000 RPMH_REGULATOR_LEVEL_SVS>;
|
|
|
|
iommus = <&kgsl_smmu 0x5 0x000>;
|
|
qcom,iommu-dma = "disabled";
|
|
};
|
|
};
|