a7ea1feb1b
Add support for Kera GPU. Change-Id: I46ac3fd2e4a21a5b95e7f5d372e546ab2dec11ca Signed-off-by: Harshitha Sai Neelati <quic_hsaineel@quicinc.com>
152 lines
3.0 KiB
Plaintext
152 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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&msm_gpu {
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qcom,initial-pwrlevel = <7>;
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/* Power levels */
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qcom,gpu-pwrlevels {
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compatible="qcom,gpu-pwrlevels";
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#address-cells = <1>;
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#size-cells = <0>;
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/* Turbo_L1 */
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <1075000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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qcom,bus-freq-ddr7 = <10>;
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qcom,bus-min-ddr7 = <10>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <9>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <10>;
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};
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/* Turbo */
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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qcom,gpu-freq = <975000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,bus-freq-ddr7 = <10>;
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qcom,bus-min-ddr7 = <10>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <9>;
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};
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/* Nom_L1 */
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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qcom,gpu-freq = <900000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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qcom,bus-freq-ddr7 = <10>;
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qcom,bus-min-ddr7 = <9>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <8>;
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qcom,bus-min-ddr8 = <8>;
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qcom,bus-max-ddr8 = <8>;
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};
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/* Nom */
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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qcom,gpu-freq = <796000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
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qcom,bus-freq-ddr7 = <10>;
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qcom,bus-min-ddr7 = <9>;
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qcom,bus-max-ddr7 = <10>;
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qcom,bus-freq-ddr8 = <7>;
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qcom,bus-min-ddr8 = <6>;
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qcom,bus-max-ddr8 = <8>;
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};
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/* SVS_L2 */
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qcom,gpu-pwrlevel@4 {
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reg = <4>;
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qcom,gpu-freq = <724000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
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qcom,bus-freq-ddr7 = <9>;
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qcom,bus-min-ddr7 = <8>;
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qcom,bus-max-ddr7 = <9>;
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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};
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/* SVS_L1 */
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qcom,gpu-pwrlevel@5 {
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reg = <5>;
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qcom,gpu-freq = <645000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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qcom,bus-freq-ddr7 = <8>;
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qcom,bus-min-ddr7 = <7>;
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qcom,bus-max-ddr7 = <9>;
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qcom,bus-freq-ddr8 = <6>;
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qcom,bus-min-ddr8 = <5>;
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qcom,bus-max-ddr8 = <7>;
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};
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/* SVS */
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qcom,gpu-pwrlevel@6 {
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reg = <6>;
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qcom,gpu-freq = <515000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
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qcom,bus-freq-ddr7 = <6>;
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qcom,bus-min-ddr7 = <3>;
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qcom,bus-max-ddr7 = <6>;
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qcom,bus-freq-ddr8 = <4>;
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qcom,bus-min-ddr8 = <2>;
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qcom,bus-max-ddr8 = <5>;
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};
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/* Low_SVS */
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qcom,gpu-pwrlevel@7 {
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reg = <7>;
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qcom,gpu-freq = <345000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <2>;
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qcom,bus-max-ddr7 = <6>;
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qcom,bus-freq-ddr8 = <2>;
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qcom,bus-min-ddr8 = <2>;
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qcom,bus-max-ddr8 = <4>;
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};
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/* Low_SVS_D1 */
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qcom,gpu-pwrlevel@8 {
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reg = <8>;
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qcom,gpu-freq = <259000000>;
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qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
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qcom,bus-freq-ddr7 = <2>;
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qcom,bus-min-ddr7 = <1>;
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qcom,bus-max-ddr7 = <6>;
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qcom,bus-freq-ddr8 = <2>;
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qcom,bus-min-ddr8 = <2>;
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qcom,bus-max-ddr8 = <4>;
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};
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};
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};
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